EP0794492A3 - Exécution répartie de commandes à mode inadapté dans des systèmes multiprocesseurs - Google Patents

Exécution répartie de commandes à mode inadapté dans des systèmes multiprocesseurs Download PDF

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Publication number
EP0794492A3
EP0794492A3 EP97301416A EP97301416A EP0794492A3 EP 0794492 A3 EP0794492 A3 EP 0794492A3 EP 97301416 A EP97301416 A EP 97301416A EP 97301416 A EP97301416 A EP 97301416A EP 0794492 A3 EP0794492 A3 EP 0794492A3
Authority
EP
European Patent Office
Prior art keywords
processor
alternate
mode
command
mismatched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP97301416A
Other languages
German (de)
English (en)
Other versions
EP0794492B1 (fr
EP0794492A2 (fr
Inventor
Thomas J. Bonola
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Compaq Computer Corp
Original Assignee
Compaq Computer Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Compaq Computer Corp filed Critical Compaq Computer Corp
Publication of EP0794492A2 publication Critical patent/EP0794492A2/fr
Publication of EP0794492A3 publication Critical patent/EP0794492A3/fr
Application granted granted Critical
Publication of EP0794492B1 publication Critical patent/EP0794492B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45504—Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/5044—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering hardware capabilities
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00—Indexing scheme relating to G06F9/00
    • G06F2209/50—Indexing scheme relating to G06F9/50
    • G06F2209/509—Offload

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Hardware Redundancy (AREA)
EP97301416A 1996-03-04 1997-03-04 Exécution répartie de commandes à mode inadapté dans des systèmes multiprocesseurs Expired - Lifetime EP0794492B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US610027 1996-03-04
US08/610,027 US5706514A (en) 1996-03-04 1996-03-04 Distributed execution of mode mismatched commands in multiprocessor computer systems

Publications (3)

Publication Number Publication Date
EP0794492A2 EP0794492A2 (fr) 1997-09-10
EP0794492A3 true EP0794492A3 (fr) 1998-09-23
EP0794492B1 EP0794492B1 (fr) 2004-02-04

Family

ID=24443312

Family Applications (1)

Application Number Title Priority Date Filing Date
EP97301416A Expired - Lifetime EP0794492B1 (fr) 1996-03-04 1997-03-04 Exécution répartie de commandes à mode inadapté dans des systèmes multiprocesseurs

Country Status (3)

Country Link
US (1) US5706514A (fr)
EP (1) EP0794492B1 (fr)
DE (1) DE69727407T2 (fr)

Families Citing this family (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6058465A (en) * 1996-08-19 2000-05-02 Nguyen; Le Trong Single-instruction-multiple-data processing in a multimedia signal processor
US6247091B1 (en) * 1997-04-28 2001-06-12 International Business Machines Corporation Method and system for communicating interrupts between nodes of a multinode computer system
US6058466A (en) * 1997-06-24 2000-05-02 Sun Microsystems, Inc. System for allocation of execution resources amongst multiple executing processes
US5890008A (en) * 1997-06-25 1999-03-30 Sun Microsystems, Inc. Method for dynamically reconfiguring a processor
US5913058A (en) * 1997-09-30 1999-06-15 Compaq Computer Corp. System and method for using a real mode bios interface to read physical disk sectors after the operating system has loaded and before the operating system device drivers have loaded
US8539112B2 (en) 1997-10-14 2013-09-17 Alacritech, Inc. TCP/IP offload device
US6434620B1 (en) * 1998-08-27 2002-08-13 Alacritech, Inc. TCP/IP offload network interface device
US8782199B2 (en) * 1997-10-14 2014-07-15 A-Tech Llc Parsing a packet header
US8621101B1 (en) 2000-09-29 2013-12-31 Alacritech, Inc. Intelligent network storage interface device
US6226680B1 (en) 1997-10-14 2001-05-01 Alacritech, Inc. Intelligent network interface system method for protocol processing
US6757746B2 (en) * 1997-10-14 2004-06-29 Alacritech, Inc. Obtaining a destination address so that a network interface device can write network data without headers directly into host memory
US6697868B2 (en) * 2000-02-28 2004-02-24 Alacritech, Inc. Protocol processing stack for use with intelligent network interface device
DE69822591T2 (de) * 1997-11-19 2005-03-24 Imec Vzw System und Verfahren zur Kontextumschaltung über vorbestimmte Unterbrechungspunkte
US6154785A (en) * 1998-07-17 2000-11-28 Network Equipment Technologies, Inc. Inter-processor communication system
JP2000200218A (ja) * 1998-09-01 2000-07-18 Texas Instr Inc <Ti> キャッシュメモリを有するマイクロプロセッサ
US6560629B1 (en) * 1998-10-30 2003-05-06 Sun Microsystems, Inc. Multi-thread processing
US6757762B1 (en) * 1999-10-29 2004-06-29 Unisys Corporation Multi-mode processor bus bridge
US7661107B1 (en) * 2000-01-18 2010-02-09 Advanced Micro Devices, Inc. Method and apparatus for dynamic allocation of processing resources
WO2001069372A2 (fr) * 2000-03-10 2001-09-20 Koninklijke Philips Electronics N.V. Dispositif de traitement de donnees, procede de fonctionnement d'un dispositif de traitement de donnees, et procede permettant de compiler un programme
US8019901B2 (en) 2000-09-29 2011-09-13 Alacritech, Inc. Intelligent network storage interface system
JP3561506B2 (ja) * 2001-05-10 2004-09-02 東京エレクトロンデバイス株式会社 演算システム
US6789048B2 (en) * 2002-04-04 2004-09-07 International Business Machines Corporation Method, apparatus, and computer program product for deconfiguring a processor
US7543087B2 (en) * 2002-04-22 2009-06-02 Alacritech, Inc. Freeing transmit memory on a network interface device prior to receiving an acknowledgement that transmit data has been received by a remote device
JP3856737B2 (ja) * 2002-07-19 2006-12-13 株式会社ルネサステクノロジ データ処理装置
AU2003250575A1 (en) 2002-08-07 2004-02-25 Mmagix Technology Limited Apparatus, method and system for a synchronicity independent, resource delegating, power and instruction optimizing processor
US7092265B2 (en) * 2002-11-14 2006-08-15 Fyre Storm, Inc. Switching power converter controller
US7694304B2 (en) * 2003-08-28 2010-04-06 Mips Technologies, Inc. Mechanisms for dynamic configuration of virtual processor resources
US9032404B2 (en) * 2003-08-28 2015-05-12 Mips Technologies, Inc. Preemptive multitasking employing software emulation of directed exceptions in a multithreading processor
US7870553B2 (en) 2003-08-28 2011-01-11 Mips Technologies, Inc. Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts
US7849297B2 (en) * 2003-08-28 2010-12-07 Mips Technologies, Inc. Software emulation of directed exceptions in a multithreading processor
US7836450B2 (en) * 2003-08-28 2010-11-16 Mips Technologies, Inc. Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts
US20050050305A1 (en) * 2003-08-28 2005-03-03 Kissell Kevin D. Integrated mechanism for suspension and deallocation of computational threads of execution in a processor
US6996070B2 (en) * 2003-12-05 2006-02-07 Alacritech, Inc. TCP/IP offload device with reduced sequential processing
US7240182B2 (en) * 2004-09-16 2007-07-03 International Business Machines Corporation System and method for providing a persistent function server
US8248939B1 (en) 2004-10-08 2012-08-21 Alacritech, Inc. Transferring control of TCP connections between hierarchy of processing mechanisms
CN100362481C (zh) * 2005-09-15 2008-01-16 上海华为技术有限公司 多处理器设备单元主备保护方法
US7516301B1 (en) * 2005-12-16 2009-04-07 Nvidia Corporation Multiprocessor computing systems with heterogeneous processors
FR2893156B1 (fr) 2005-11-04 2008-02-15 Commissariat Energie Atomique Procede et systeme de calcul intensif multitache et multiflot en temps reel.
US20080263171A1 (en) * 2007-04-19 2008-10-23 Alacritech, Inc. Peripheral device that DMAS the same data to different locations in a computer
US8341286B1 (en) 2008-07-31 2012-12-25 Alacritech, Inc. TCP offload send optimization
US9306793B1 (en) 2008-10-22 2016-04-05 Alacritech, Inc. TCP offload device that batches session layer headers to reduce interrupts as well as CPU copies
US9984083B1 (en) 2013-02-25 2018-05-29 EMC IP Holding Company LLC Pluggable storage system for parallel query engines across non-native file systems
US9454573B1 (en) * 2013-02-25 2016-09-27 Emc Corporation Parallel processing database system with a shared metadata store
US10362093B2 (en) * 2014-01-09 2019-07-23 Netronome Systems, Inc. NFA completion notification
US11908541B2 (en) 2020-01-07 2024-02-20 SK Hynix Inc. Processing-in-memory (PIM) systems
US20210210125A1 (en) * 2020-01-07 2021-07-08 SK Hynix Inc. Processing-in-memory (pim) system and operating methods of the pim system

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4943915A (en) * 1987-09-29 1990-07-24 Digital Equipment Corporation Apparatus and method for synchronization of a coprocessor unit in a pipelined central processing unit
EP0385136A2 (fr) * 1989-02-03 1990-09-05 Nec Corporation Microprocesseur coopérant avec un coprocesseur
EP0442041A2 (fr) * 1990-01-18 1991-08-21 National Semiconductor Corporation Processeur de traitement de signaux numériques et processeur universel integrés avec mémoire interne partagée
EP0623875A2 (fr) * 1988-02-29 1994-11-09 Convex Computer Corporation Système d'ordinateur multi-processeur avec adressage de registres de communication indépendant des processus
EP0668560A2 (fr) * 1994-02-18 1995-08-23 International Business Machines Corporation Méthode de co-exécution et dispositif pour performer un traitement parallèle dans des types conventionnels de systèmes de traitement de données

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4394727A (en) * 1981-05-04 1983-07-19 International Business Machines Corporation Multi-processor task dispatching apparatus
US5283897A (en) * 1990-04-30 1994-02-01 International Business Machines Corporation Semi-dynamic load balancer for periodically reassigning new transactions of a transaction type from an overload processor to an under-utilized processor based on the predicted load thereof
EP0519348B1 (fr) * 1991-06-19 1999-07-28 Hewlett-Packard Company Architecture supportant co-processeur, adaptée à un processeur qui ne comprend pas lui-même de processeur adjoint
JP2791236B2 (ja) * 1991-07-25 1998-08-27 三菱電機株式会社 プロトコル並列処理装置
EP0562251A2 (fr) * 1992-03-24 1993-09-29 Universities Research Association, Inc. Réseau de transmission de données parallèles au moyen d'un réseau série dynamiquement reconfigurable
US5301324A (en) * 1992-11-19 1994-04-05 International Business Machines Corp. Method and apparatus for dynamic work reassignment among asymmetric, coupled processors

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4943915A (en) * 1987-09-29 1990-07-24 Digital Equipment Corporation Apparatus and method for synchronization of a coprocessor unit in a pipelined central processing unit
EP0623875A2 (fr) * 1988-02-29 1994-11-09 Convex Computer Corporation Système d'ordinateur multi-processeur avec adressage de registres de communication indépendant des processus
EP0385136A2 (fr) * 1989-02-03 1990-09-05 Nec Corporation Microprocesseur coopérant avec un coprocesseur
EP0442041A2 (fr) * 1990-01-18 1991-08-21 National Semiconductor Corporation Processeur de traitement de signaux numériques et processeur universel integrés avec mémoire interne partagée
EP0668560A2 (fr) * 1994-02-18 1995-08-23 International Business Machines Corporation Méthode de co-exécution et dispositif pour performer un traitement parallèle dans des types conventionnels de systèmes de traitement de données

Also Published As

Publication number Publication date
DE69727407D1 (de) 2004-03-11
EP0794492B1 (fr) 2004-02-04
US5706514A (en) 1998-01-06
EP0794492A2 (fr) 1997-09-10
DE69727407T2 (de) 2004-12-16

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