EP0791281B1 - System for operating a lamp - Google Patents

System for operating a lamp Download PDF

Info

Publication number
EP0791281B1
EP0791281B1 EP96923024A EP96923024A EP0791281B1 EP 0791281 B1 EP0791281 B1 EP 0791281B1 EP 96923024 A EP96923024 A EP 96923024A EP 96923024 A EP96923024 A EP 96923024A EP 0791281 B1 EP0791281 B1 EP 0791281B1
Authority
EP
European Patent Office
Prior art keywords
lamp
control period
supply voltage
perturbed
period
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP96923024A
Other languages
German (de)
English (en)
French (fr)
Other versions
EP0791281A1 (en
Inventor
Yongping Xia
Sreeraman Venkitasubrahmanian
Raj Jayaraman
Thomas Farkas
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of EP0791281A1 publication Critical patent/EP0791281A1/en
Application granted granted Critical
Publication of EP0791281B1 publication Critical patent/EP0791281B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B41/00—Circuit arrangements or apparatus for igniting or operating discharge lamps
    • H05B41/14—Circuit arrangements
    • H05B41/36—Controlling
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B41/00—Circuit arrangements or apparatus for igniting or operating discharge lamps
    • H05B41/14—Circuit arrangements
    • H05B41/36—Controlling
    • H05B41/38—Controlling the intensity of light
    • H05B41/39—Controlling the intensity of light continuously
    • H05B41/392—Controlling the intensity of light continuously using semiconductor devices, e.g. thyristor
    • H05B41/3921—Controlling the intensity of light continuously using semiconductor devices, e.g. thyristor with possibility of light intensity variations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B47/00—Circuit arrangements for operating light sources in general, i.e. where the type of light source is not relevant
    • H05B47/10—Controlling the light source
    • H05B47/175—Controlling the light source by remote control
    • H05B47/185—Controlling the light source by remote control via power line carrier transmission

Definitions

  • the invention relates to a system for operating a lamp comprising
  • the invention also relates to encoding means and to a ballast circuit for use in such a system.
  • US 5,227,762 discloses a system in which a high frequency control signal is superimposed on the supply voltage.
  • US 4,329,678 discloses a system in which the control signal is formed by generating a pulse in each period of the current supplied by the supply voltage.
  • a system as described in the opening paragraph is known from U.S. 5,068,576.
  • the encoding means completely cuts or reduces the magnitude of an entire half period, so that there is a missing pulse or a pulse of significantly reduced voltage in the rectified DC output of the of a rectifier comprised in the ballast circuit.
  • the operating characteristic of the lamp that is controlled is the light output. The time period between successive missing pulses represents a dimming command.
  • time “n" between missing pulses may represent a 70% dim level while time “m” between missing pulses represents a 90% dim level.
  • a missing pulse means an interruption of the supply voltage and will cause a lamp operated by the ballast to flicker.
  • the flicker is not so objectionable as the user expects a significant and abrupt change in the light output of the lamp when switching from one light level, e.g. 90% to the next, e.g. 75%.
  • a continuous dimming effect is desired, i.e. where the light should be smoothly adjustable in very small increments, the cutting of entire pulses from the mains supply (and the resulting flicker) would be objectionable to the user.
  • the invention aims to provide a system for operating a lamp comprising an improved communication between encoding means and the ballast circuit which overcomes the above-mentioned disadvantage.
  • a system for operating a lamp as described in the opening paragraph is therefore according to the invention characterized in that the perturbations applied by the encoding are phase cuts.
  • the encoded perturbations in the line voltage in the coded technique according to the invention can be chosen small enough so that lamp flicker is avoided even with encoded signals on the supply voltage.
  • the part of the half period that is perturbed can be chosen between 10% and 50% of a half period, preferably between 10% and 25%.
  • phase cuts can be chosen less than 45 degrees, preferably about 30 degrees. In this way the encoded perturbations in the line voltage in the coded technique according to the invention can be very small so that lamp flicker is very effectively avoided.
  • the means for controlling an operating characteristic of the lamp can for instance be dimming means for controlling the light output of the lamp. No perturbations are introduced on the line voltage unless a change in the operating characteristic of the electric lamp is desired.
  • This has the advantage that when lamp operation is to be kept constant, no distortions are imposed on the mains voltage, so that flicker of the lamp is completely avoided. This is significant, since for general lighting purposes the amount of time that a lamp remains at the same light level far exceeds the very limited time frame in which the light level is actually changing. This is in contrast to triac and electronic dimmers where at intermediate light levels, phase cuts are continuously imposed on every cycle of the mains voltage.
  • Said control period can be formed by two successive perturbed half periods of the supply voltage and the unperturbed half periods therebetween, and the signal can depend on the time duration of the control period.
  • said control period may comprise a fixed number of half periods of the sinusoidal supply voltage.
  • the signal may depend on the amount of perturbations in a control period.
  • the encoding and decoding means can be of relatively simple construction.
  • the control period represents a binary figure, each unperturbed half period of the control period corresponding to a "0" (zero) and each perturbed half period corresponding to a "1" (one). This way many commands can be accommodated in a control period.
  • control period represents a binary figure, each unperturbed half period of the control period corresponding to a "1" (one) and each perturbed half period corresponding to a "0" (zero).
  • the fluorescent lamp ballast circuit shown in Figure 1 includes an EMI and triac damping filter "A” connected to full bridge input rectifier “B”, which together convert a sinusoidal AC power line voltage into a rectified, filtered DC voltage at an output thereof.
  • the pre-conditioner circuit “C” includes circuitry for active power factor correction, as well as for increasing and controlling the DC voltage from the rectifier circuit B, which DC voltage is provided across a pair of DC rails RL1, RL2.
  • the ballast circuit includes a DC-AC converter, or inverter, "E” and a controller “G” which controls the inverter.
  • the inverter E is a half-bridge configuration which under control of the half-bridge controller, or driver, circuit G provides a high frequency lamp current to the lamp La coupled to the inverter E.
  • the means I for generating a lamp current are formed by filter "A”, rectifier "B” , preconditioner circuit “C” and inverter "E".
  • Controller G forms means II for controlling an operating characteristic (the light output) of the lamp in dependency of a control signal.
  • a dimming interface circuit "I" is connected between an output of the rectifier circuit B and a control input of ballast circuit present at the controller G to control dimming of the lamp.
  • the dimming interface circuitry provides a dimming voltage signal (the control signal) to the controller G and forms the decoding means for generating a signal depending on the shape of the control period.
  • a selected number of line cycles or fundamental periods forms a control period.
  • the occurrence signature of preselected perturbation within the control period is indicative of a control command, for example to change an operating characteristic of the lamp, such as the light level.
  • the "occurrence signature" of the perturbation within the control period may simply be the number of times that the perturbation occurs within the control period.
  • the occurrence signature may also be the location pattern of the perturbation within the control period. For example, the perturbation may be encoded to from a binary number within the control period.
  • a first fixed number of perturbations represents a command to increase the light level by a pre-selected incremental amount and a second, different number of perturbations represents a command to lower the light level by the pre-selected incremental amount.
  • a third number of cuts in the control period represents the command to keep the light level the same.
  • no (zero) cuts per control period represents the command to maintain a constant light level.
  • Figures 4(a) to 4(c) represent three power line waveforms from a wall controller forming encoding means illustrating this particular dimming implementation.
  • the control period selected is three (3) full line cycles at the encoding means or wall controller, which after rectification is six (6) half-wave cycles at the interface circuit in the ballast.
  • Figure 4(d) is a waveform on the receiver side, i.e. of the dimming interface, and is the differential of the power line waveform of Figure 4(c). If there is no light intensity change requirement, the power line waveform will not be modified as shown in Figure 4(a). Thus, no additional distortion will be added into the line. In this case, there would be no pulse on the differential receiver waveform since the line voltage is a smooth sine signal.
  • a control signal to decrease the light is represented by a phase cut in one positive side waveform during every three line cycles ( Figure 4(b)), which would result in one pulse on the receiver waveform after decoding (differentiation) by the receiver.
  • a control signal to increase the light level is represented by two cuts in the control period ( Figure 4(c)) such that the receiver waveform will have two pulses during every three line cycles, as illustrated in Fig. 4(d).
  • the light will remain unchanged if no pulse is detected by the receiver in the rectified power line waveform. If one pulse or two pulses are detected during every three line cycles (six half-wave cycles after rectification), the light will change one step, i.e. by the pre-selected increment, to the corresponding direction.
  • the number of steps is selected to be 100. If an increase or decrease control signal is generated continuously by the wall controller, it will take about 5 seconds to change the light intensity from the lowest level to the highest level.
  • the main function of the wall controller or encoding means for the coded dimming technique is to generate the control patterns illustrated in Figures 4(a)- 4(c).
  • the circuit diagram of a suitable transmitter, in the form of a wall controller, is shown in Figure 3.
  • Two input terminals W1 and W3 are for connection to the white (neutral) and black (hot) lines of the power line, respectively.
  • Output terminal W2 connects to the red output line which carries the encoded, hot AC signal to the ballast.
  • a triac WU1 is connected between the terminals W1 and W2.
  • a step-down transformer WT1 has each end of its primary winding WP1 connected to a respective one of the terminals W1 and W3.
  • the ends of the secondary winding WS1 are connected to respective nodes W4, W5 of a full-bridge rectifier formed by the diodes WD1-WD4.
  • the cathodes of the diodes WD1 and WD2 are connected to node W4 and the anodes of the diodes WD3 and WD4 are connected to node W5.
  • the cathode of the diode WD3 and the anode of the diode WD1 are connected at node W6 and the cathode of the diode WD4 and the anode of the diode WD2 are connected at node W7.
  • the triggering of the triac WU1 is controlled by an 8-bit microcontroller IC1 with a built-in oscillator.
  • a suitable controller for IC1 is the Motorola MC68HC05k1.
  • the microcontroller IC1 has two ports A, B. Port A has eight terminals and Port B has two terminals. There are four push button switches WS1 - WS4 to control the following functions: on, off, light increase and light decrease.
  • the microcontroller IC-1 reads the status of these switches through its terminals PA4-PA7 of port A.
  • the node W7 of the rectifier is connected to terminal IC1's power supply VDD via line WRL2 which includes a 5V voltage regulator WU2.
  • An electrolytic capacitor WC1 is connected between the lines WRL3 and WRL2 at the input (A) side of regulator WU2 to filter the DC ripple from the rectifier.
  • a capacitor WC2 is connected between these same lines at the output side (B) of regulator W2 to filter noise.
  • the zener diode WD5 bridges lines WRL3 and WRL5, with its cathode connected to the latter line. Terminals RST (reset) and IRQ (interrupt request) are also connected to the + 5V output of regulator WU2.
  • the ceramic resonator XT is connected across oscillator terminals OSC1 and OSC2, with the components WC3, WC4, and WR2 being specified by the resonator manufacturer to ensure proper operation of the resonator XT.
  • the microcontroller IC1 needs a line voltage zero-crossing signal as a reference to trigger the triac WU1.
  • This signal is provided by the resistor WR1 and the zener diode WD5, and is input at terminals PB0 and PB1. Since the voltage at the cathode of the diode WD5 is only 4.7V, which is much less than the power line peak voltage, it provides the logic signal "1" and "0" on terminals PB0 and PB1 when the line voltage is crossing zero.
  • Controller IC1 sends the triac trigger signal out through terminals PA0 through PA3 via line WRL4 to the triac WU1.
  • the resistor WR3 limits the current to the triac WU1 from the triac trigger signal.
  • the microcontroller IC1 sends out a trigger signal immediately upon detection of the line voltage zero-crossing, there is no modification for the power line waveform. This provides the waveform of Fig. 4(a) for a constant light level.
  • the trigger signal is delayed about 1.39ms after the zero-crossing for the respective half-cycle. This provides a small phase cut of about 30 degrees.
  • Figure 5 is a program flow chart for the wall controller. After initializing port directions, the program goes into a loop that reads the status of the four switches WS1-WS4. If a switch is activated, the program will perform the corresponding function. For example, when switch WS4 (down key) is pressed, the wall controller will produce the waveform of Fig. 4(b) to dim the light and when the switch WS3 (up key) is pressed the waveform of Fig. 4(c) will be produced to increase the light level. When switch WS1 (on key) is pushed, power will be supplied to the connected lamp controller without any perturbations imposed on the AC power line signal. When switch WS2 is pressed, the AC power line signal is completely interrupted so that no power is supplied to the connected ballast.
  • switch WS4 down key
  • the wall controller will produce the waveform of Fig. 4(b) to dim the light and when the switch WS3 (up key) is pressed the waveform of Fig. 4(c) will be produced to increase the light
  • FIG. 2 is a schematic of the decoding means or receiver, or interface circuit, in the ballast circuit.
  • the heart of the interface circuit is the microcontroller IC2 (for example, a Z86C04 from Zilog, Inc.) which converts the dimming control signals to a corresponding PWM (Pulse Width Modulation) output.
  • the microcontroller IC2 has an inputs P31 which accepts the coded dimming signals.
  • the PWM output (dim) signal is formed on terminal P27 and is converted to a DC signal present at terminal Z7 for input to the half-bridge driver at the 'dim' input of controller "G" to adjust the power to the lamp.
  • Node A (also ref. Z8) of the rectifier circuit B is connected to ground (ref.
  • the input P31 is connected to a node B through a differential circuit formed by GC2 and GR5.
  • a zener diode GD6 parallel connects with GR5 to protect the input of the microcontroller IC2.
  • the microcontroller is powered at terminal VCC with a 5V voltage source, in this case from voltage regulator U3.
  • An external ceramic resonator XL1 (2MHZ) is connected between the clock terminals X1, X2.
  • the clock terminals are connected to ground via the capacitors GC3 and GC4, respectively, which ensure proper resonator operation.
  • the capacitor GC5 is connected between ground and the voltage supply to suppress noise.
  • the resistors GR6, GR7 and capacitors GC6 and GC7 smooth the PWM output signal from terminal P27 to an average DC signal for input to the dim input of the controller G.
  • the microcontroller IC2 When power turns on, i.e. the mains voltage from the wall controller is provided at ballast input terminals 1',2', the microcontroller IC2 is initialized and the output P27 is set at a default PWM value for a default light level, for example 85% light output.
  • the microcontroller input threshold level is about 2.5V. This means that it is logic "1” if the input is above 2.5V and logic “0" if the input is below 2.5V. A logic "1" will be received on terminal P31 only when the voltage on P31 exceeds 2.5V.
  • the differentiating circuit provides a pulse to terminal P31 of greater than 2.5V (logic "1") whenever the sinusoidal half-cycle includes a phase cut as with the coded dimmer (Fig. 4(d)).
  • the rectified DC output fed to the interface circuit is 120 HZ pulsed DC. If a standard ON/OFF wall switch is installed instead of any dimming control device, the PWM output signal is set to the default level, since the power line is unmodified and the microcontroller U2 will not detect any pulses at its inputs.
  • the microprocessor IC2 includes an 8-bit register named PWM which controls the substantially square wave shaped PWM output signal present at the PWM register output at P27.
  • a timer 0 in the microcontroller determines the duration of t h (the time interval during which the PWM output signal is high) and t L (the time interval during which the output signal is low) based on the PWM value in the register. After the timer 0 times out, an interrupt 4 will be generated.
  • the first test is the current PWM register output status. If the current PWM register output is logic "0", then it sets the PWM register output to 1 and installs the PWM value into timer 0.
  • the current PWM register output is logic "1"
  • the time to invoke the next interruption is proportional to the value installed into the timer 0.
  • the time of t h plus t L is set to be independent of the PWM value so that the PWM signal frequency is a constant.
  • the PWM register has more time to stay in logic "1” condition and provides a higher average output dimming control voltage at pin 27.
  • the dimming control voltage range is set from 0.4V to 3V which means the PWM duty cycle should be 8% to 60%, since logic "0" is zero volts and logic "1" is 5 volts.
  • a pulse on the terminal P31 invokes a subroutine "interrupt 1".
  • the "interrupt 1" procedure increases the value of a register named "pulse number" by 1.
  • the coded dimming control (CDL) loop installed in the microcontroller IC2 checks the value in the register "pulse number" every 50ms. Since 50ms equals 3 line cycles, the value of the register "pulse number” will determine if the light level should change. When the value in the register "pulse number” equals zero (0) there is no pulse, so no change in the light level or in the PWM value occurs. When the register "pulse number” equals one (1), the PWM value is decreased until it reaches the preset minimum value.
  • the interface circuitry enables the ballast to automatically accept dimming inputs from the wall controller and produces a DC signal, input to the controller G to control the light level of the fluorescent lamps.
  • the disclosed ballast maintains a power factor >0.99, THD ⁇ 10%, and a crest factor ⁇ 1.6, so the circuit satisfies both the need for a dimmable ballast while also providing a high power factor and keeping THD, EMI and component stress very low even at the lowest dimming levels.

Landscapes

  • Discharge-Lamp Control Circuits And Pulse- Feed Circuits (AREA)
  • Circuit Arrangements For Discharge Lamps (AREA)
EP96923024A 1995-08-09 1996-07-31 System for operating a lamp Expired - Lifetime EP0791281B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US512856 1983-07-11
US51285695A 1995-08-09 1995-08-09
PCT/IB1996/000762 WO1997006654A1 (en) 1995-08-09 1996-07-31 System for operating a lamp

Publications (2)

Publication Number Publication Date
EP0791281A1 EP0791281A1 (en) 1997-08-27
EP0791281B1 true EP0791281B1 (en) 2001-10-17

Family

ID=24040879

Family Applications (1)

Application Number Title Priority Date Filing Date
EP96923024A Expired - Lifetime EP0791281B1 (en) 1995-08-09 1996-07-31 System for operating a lamp

Country Status (8)

Country Link
EP (1) EP0791281B1 (zh)
JP (1) JPH10507578A (zh)
CN (1) CN1179607C (zh)
CA (1) CA2202070A1 (zh)
DE (1) DE69616018T2 (zh)
MX (1) MX9702563A (zh)
TW (1) TW354176U (zh)
WO (1) WO1997006654A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100420351C (zh) * 2001-05-08 2008-09-17 皇家菲利浦电子有限公司 用于操作高压灯的脉冲宽度调制
CN1787708B (zh) * 2004-12-06 2013-06-19 苏昭荣 集中控制灯光的方法及其系统
US20100072909A1 (en) * 2008-09-23 2010-03-25 O'gorman Tony System for Field-Programmed Determination of Illumination Set Points in Ballasts
WO2010150183A1 (en) 2009-06-25 2010-12-29 Koninklijke Philips Electronics N.V. Driver for cooperating with a wall dimmer
US8330384B2 (en) * 2010-04-09 2012-12-11 Exscitron Gmbh Power supply unit, light emitting apparatus and dimming method thereof

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4024528A (en) * 1975-10-30 1977-05-17 Boggs Luther M Remote switching system
US4329678A (en) * 1980-03-24 1982-05-11 Hatfield Jerry M Method and apparatus for remotely controlling an electrical appliance
DE69130349T2 (de) * 1990-08-13 1999-06-24 Electronic Ballast Tech Fernsteuerung für ein elektrisches Gerät
US5227762A (en) * 1990-10-26 1993-07-13 Thomas Industries Inc. Power line carrier controlled lighting system

Also Published As

Publication number Publication date
DE69616018T2 (de) 2002-06-06
EP0791281A1 (en) 1997-08-27
DE69616018D1 (de) 2001-11-22
WO1997006654A1 (en) 1997-02-20
JPH10507578A (ja) 1998-07-21
CN1161126A (zh) 1997-10-01
CA2202070A1 (en) 1997-02-20
MX9702563A (es) 1997-06-28
CN1179607C (zh) 2004-12-08
TW354176U (en) 1999-03-01

Similar Documents

Publication Publication Date Title
EP0786193B1 (en) Ballast circuit
US5872429A (en) Coded communication system and method for controlling an electric lamp
US5055746A (en) Remote control of fluorescent lamp ballast using power flow interruption coding with means to maintain filament voltage substantially constant as the lamp voltage decreases
CA2049075C (en) Remote control of fluorescent lamp ballast using power flow interruptioncoding with means to maintain filament voltage substantially constant as the lamp voltage decreases
US5107184A (en) Remote control of fluorescent lamp ballast using power flow interruption coding with means to maintain filament voltage substantially constant as the lamp voltage decreases
CA2327961C (en) Dual control dimming ballast
US5068576A (en) Remote control of fluorescent lamp ballast using power flow interruption coding with means to maintain filament voltage substantially constant as the lamp voltage decreases
US5394064A (en) Electronic ballast circuit for fluorescent lamps
US6963178B1 (en) Apparatus for controlling operation of gas discharge devices
EP1400154B1 (en) Electronic ballast for a high intensity discharge lamp
KR101759613B1 (ko) 월 디머와 협력하기 위한 드라이버
EP0791281B1 (en) System for operating a lamp
EP1433365A1 (en) Electronic ballast with lamp run-up current regulation
EP2078445B1 (en) A circuit for driving light sources and related method
MXPA97002563A (en) System to operate a lamp
EP1211915B1 (en) Arrangement in connection with discharge lamp
US6385068B2 (en) Circuit device
US6495974B1 (en) Power supply for brightness control of a gas-discharge tube
GB2319678A (en) Dimming discharge lamps

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR GB

17P Request for examination filed

Effective date: 19970820

17Q First examination report despatched

Effective date: 20000105

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB

REF Corresponds to:

Ref document number: 69616018

Country of ref document: DE

Date of ref document: 20011122

REG Reference to a national code

Ref country code: GB

Ref legal event code: IF02

ET Fr: translation filed
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
REG Reference to a national code

Ref country code: FR

Ref legal event code: D6

REG Reference to a national code

Ref country code: GB

Ref legal event code: 746

Effective date: 20021205

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20050727

Year of fee payment: 10

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20050729

Year of fee payment: 10

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20050913

Year of fee payment: 10

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20060731

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20070201

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20060731

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

Effective date: 20070330

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20060731