EP0789382A1 - Structure et procédé de fabrication d'un dispositif d'émission de champ - Google Patents

Structure et procédé de fabrication d'un dispositif d'émission de champ Download PDF

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Publication number
EP0789382A1
EP0789382A1 EP96101877A EP96101877A EP0789382A1 EP 0789382 A1 EP0789382 A1 EP 0789382A1 EP 96101877 A EP96101877 A EP 96101877A EP 96101877 A EP96101877 A EP 96101877A EP 0789382 A1 EP0789382 A1 EP 0789382A1
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EP
European Patent Office
Prior art keywords
tip
insulating layer
field emission
layer
tips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP96101877A
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German (de)
English (en)
Inventor
Johann Dr. Bartha
Gerhard Dr. Elsner
Johann Dr. Greschner
Samuel Kalt
Klaus Meissner
Rudolf Paul
Roland Schleicher
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International Business Machines Corp
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International Business Machines Corp
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Publication date
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Priority to EP96101877A priority Critical patent/EP0789382A1/fr
Priority to JP3705897A priority patent/JPH09223454A/ja
Publication of EP0789382A1 publication Critical patent/EP0789382A1/fr
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J3/00—Details of electron-optical or ion-optical arrangements or of ion traps common to two or more basic types of discharge tubes or lamps
    • H01J3/02—Electron guns
    • H01J3/021—Electron guns using a field emission, photo emission, or secondary emission electron source
    • H01J3/022—Electron guns using a field emission, photo emission, or secondary emission electron source with microengineered cathode, e.g. Spindt-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J1/00—Details of electrodes, of magnetic control means, of screens, or of the mounting or spacing thereof, common to two or more basic types of discharge tubes or lamps
    • H01J1/02—Main electrodes
    • H01J1/30—Cold cathodes, e.g. field-emissive cathode
    • H01J1/304—Field-emissive cathodes
    • H01J1/3042—Field-emissive cathodes microengineered, e.g. Spindt-type

Definitions

  • the present invention relates to the technical field of devices using the effect to emit electrons out of a solid into vacuum due to high electric field strength. Such devices are usually called "field emission devices".
  • the invention relates to the structure of a field emission device, to the method of fabricating a field emission device, and, more specifically, to the use of a multitude of field emission devices in the technical field of flat panel displays.
  • Field emission devices can be used to replace conventional thermal emission devices as electron sources for e.g. scanning electron microscopes, high performance and high frequency vacuum tubes, and, more general, for vacuum microelectronic devices.
  • a typical field emission device comprises a conductive tip placed on a conductive electrode which usually forms the cathode electrode.
  • the tip end is surrounded by a gate electrode.
  • An appropriate voltage is applied between the cathode and the gate electrode to emit electrons into the vacuum.
  • the tip and gate arrangement is encapsulated by an upper and lower glass plate.
  • the upper glass plate contains the anode electrode and a phosphorous layer.
  • An applied voltage between the cathode and the anode electrode accelerates the electrons emitted by the tips towards the phosphorous layer which emits visible light as usable in a display device.
  • Gate and cathode electrodes are typically arranged in orthogonal stripes which allows matrix addressing of the electron emitting tips. Usually, an array of typically 1,000 tips is forming one pixel.
  • each pixel was divided in 50 groups of tips, each group consists of 36 tips. Each tip within a group is connected via a common polysilicon resistive layer to the cathode electrode which is meshed. Therefore, there is no cathode electrode metallization directly underneath the tips. Therefore, in case of a short circuit between one tip and its respective gate electrode the whole pixel (made of 50 groups) will not be affected. However, it is still disadvantageous that in case of a failure of one tip the respective complete group of tips will fail. It is also disadvantageous that there is a considerable voltage drop within one group of tips caused by the various distances between individual tips and the cathode electrode which leads to different values of the series resistance for each individual tip. This voltage drop requires a considerably higher driving voltage and also power consumption and results in less tip emission current. Furthermore, the voltage drop causes a non-uniform emission within one group of tips and therefore causes a non-uniformity in pixel brightness.
  • the unpublished application EP-A-94113601 discloses a structure of a field emission device which comprises an individual series resistor for each electron emitting tip, wherein the series resistor is formed by the tip itself.
  • the tip comprises a body of a first material with high resistivity and an at least partial coating of a second material with low work function, wherein the body of the first material forms the series resistor and the coating of the second material provides for electron emission.
  • the method for fabricating a field emission device uses depositing and sacrificial layer etch back techniques to provide easy and precise control of tip height and shape and also easy and precise control of the lateral tip-to-gate distance and geometry.
  • the method requires a bonding process for bonding a first substrate to a second substrate. This bonding step imposes objectives onto the manufacturability of the structure which might limit the size of the flat panel display substrates.
  • a field emission device with a series resistor formed by the tip itself can be directly connected to the supply electrode, e.g. the cathode electrode.
  • the supply electrode e.g. the cathode electrode.
  • the tip-individual series resistor offers higher tip to tip homogeneity of electron emission, since there is no voltage drop within a group of tips.
  • the "no voltage drop" has the advantage of a lower supply voltage and therefore less power consumption. The less supply voltage also has the advantage to use a more convenient control electronics.
  • the tip is centered in relation to a particularly circular gate aperture that is forming an electrode, the gate electrode.
  • This gate electrode allows advantageously easy and precise emission control. Furthermore, the emission and the acceleration of the emitted electrons can be controlled separately. It is extremely advantageous for the tips to project above the surface of the electrode forming the gate aperture. If the tip apex sticks out of the gate electrode surface level to a defined amount the voltage for a constant current stays constant. Building field emission devices with this kind of geometry offers a large process window at the same ideal performance. This makes the manufacturing of such devices easier and increases their reliability.
  • the tip comprises a body of a first material forming the series resistor and a coating of a second material providing for electron emission.
  • This separation of the tip in two components allows more flexibility in view to the optimization of both materials with respect to their objects.
  • a particularly thin coating of the tip body with the relatively expensive electron emission material offers the possibility of cost reduction during the fabrication process.
  • a high resistivity material is used for the body of the tip and a material with a low work function is used for the coating of the tip. This is advantageous since the high resistivity material allows the realization of a small tip geometry with significant resistance value.
  • the low work function material is also advantageous since it allows a high emission efficiency already at relatively low voltages.
  • the high resistivity material is an amorphous or polycrystalline silicon, which is no- or low-doped and the low work function material is tungsten (W) or molybdenum (Mo).
  • the use of silicon for the high resistivity material is advantageous, because the resistivity of silicon can be easily modified, either at the time of deposition of the silicon film or after deposition of the silicon film by using diffusion or ion implantation methods.
  • silicon is a very usual material, available in very high purity, relatively low in cost, and can be deposited by various depositing methods.
  • the use of tungsten or molybdenum as a low work function material is advantageous, because those material are very usual for electron emission devices and can be deposited by using standard depositing techniques and equipment.
  • the tip is low-ohmic or directly connected to a first electrode, which is usually the cathode electrode, and which is formed on a substrate.
  • a first electrode which is usually the cathode electrode, and which is formed on a substrate.
  • the tip may be opposed to an electrode on a second substrate which comprises also a photon emitting layer, in particular a phosphorous layer.
  • This electrode is used for the acceleration of the emitted electrons and allows easy and precise control for the energy of electrons when arriving at the second substrate.
  • the photo emitting layer allows advantageously the use of field emission devices as light emitting sources.
  • Field emission devices may be used in the technical field of flat panel displays. Therefore, it is advantageous that field emission devices offer the possibility of realizing light emitting sources with high brightness, high contrast, low power consumption, and easy fabricating processes using standard semiconductor technology leading to a flexible and relatively cheap production method.
  • the fabrication method as disclosed in the present application offers the advantage of relaxed lithographic, etching, and depositing process requirements. Furthermore, this offers a higher flexibility concerning the selection of process technology and is in particular advantageous in view of large-size flat panel displays. It is also advantageous, that the disclosed fabrication method offers the possibility of easy and precise control of the lateral and vertical tip-to-gate distance. Using the relaxed lithographic, etching, and depositing technology requirements the lateral and vertical tip-to-gate distance can be well controlled even in the submicron region.
  • a small lateral tip-to-gate distance offers a high field emission efficiency at lower voltages and less power consumption which is in particular advantageous for battery powered arrangements as flat panel displays for mobile computers.
  • the low supply voltage is furthermore advantageous because it allows a more convenient control electronics. It is a further advantage of the disclosed fabrication method that it provides a complete cathode, electron emission tip, and gate electrode. Furthermore, it is advantageous that the tip height, shape and the amount to which the tip projects above the surface level of the gate electrode can be controlled easily.
  • the separation in first and second dielectric layer as described in the fabrication method is advantageous for providing a reliable etch stop on the first dielectric layer when etching back the second dielectric layer.
  • the accuracy which is defined by this etch stop defines later on the tip-to-gate electrode distance and the gate opening size which is one of the most important factors for electron emission efficiency and reliability.
  • the combination of SiO 2 - and Si 3 N 4 -layers offers the possibility of selective etching with a high selectivity and a reliable etch stop.
  • the polymer can be removed by laser irradiation or can be dissolved chemically.
  • the tip height and radius is extremely uniform.
  • the lateral and vertical tip-to-gate electrode distance can easily be controlled down to submicron dimensions which allows field emission at low supply voltages. This leads to a lower power consumption which is an important fact for battery recharge cycles in portable display systems but allows also the use of a more convenient electronic control circuit.
  • the disclosed method for fabrication allows a high degree of freedom in the choice of the critical materials like tip emitter metal and substrate sizes.
  • Figs. 1A to 1F show a process sequence as an embodiment of the method for fabricating field emission devices.
  • the semiconductor substrate 7 in Fig. 1A already contains a multitude of tips 1.
  • a preferred material for the substrate 7 is silicon.
  • the tips 1 can be fabricated as shown in Fig. 2B to 2D by masking the substrate with tip masks 8, by creating tips 1 by underetching the tip mask and by subsequently removing the tip masks.
  • a SEM picture of a silicon tip array according to the process level of Fig. 1A is shown in Fig. 6.
  • a first insulating layer 9 is deposited or grown on the surface and coats the total surface of the substrate.
  • the first insulating layer 9 can be thermal SiO 2 or silicon nitride.
  • a second insulating layer 10 is deposited on the first insulating layer 9.
  • This second insulating layer is used for planarizing the surface of the substrate and is made of a material which allows to planarize an array of tips. Suitable materials are polymers and silicate glass, preferable polyimide or resist materials.
  • the thickness of the planarizing layer has to be chosen; in one embodiment with a tip height of about 8 ⁇ m the planarizing layer had a thickness of about 10 ⁇ m.
  • Fig. 7 shows a SEM micrograph of a field emitter array after oxidation of the tips, after coating the tips with polyimide and after the back etch of the polyimide layer.
  • Fig. 1E those portions of the first insulating layer 9 which are directly coating the tips are removed by a wet selective etchant.
  • the etchant is HF or buffered HF.
  • the substrate is metallized by depositing a metal layer 4 on the upper portion 5 of the tip and on the surface of the second insulating layer 10.
  • the metal layer 4 deposited on the insulating layer 10 forms the gate electrode of the device.
  • the metal layer deposited should be stable and offer a low work function.
  • gold or Cr/Au is chosen.
  • the deposition process has to be controlled very carefully to avoid electrical shortening between the tips and the surrounding gate electrode.
  • the gap between the tip and the surrounding gate electrode should be as small as possible as this would reduce the threshold voltage for field emission considerably.
  • Fig. 8A and Fig. 8B show SEM pictures of a tip array and a tip with the finished structure including the gate metal.
  • the embodiment described above is extremely simple to manufacture and will mainly be used as large area cold electron source in a field emitter device in vacuum applications.
  • Fig. 2A to Fig. 2K show another preferred embodiment of the invention according to a sligthly modified method for fabricating the field emission devices. This embodiment is well suited for being used in display applications.
  • the substrate 7 which in this case preferably is a glass plate is coated with a conductive layer 13, preferably a metal layer.
  • Layer 13 is structured to form conductive stripes 13 which are the cathode electrodes in the final device.
  • a semiconductor layer 14 preferably a polysilicon layer, is deposited on the conductive stripes.
  • tip masks 8 By masking the semiconductor layer with tip masks 8, by underetching the tip masks in a dry or wet etching step and by subsequently removing the tip masks a multitude of tips is formed.
  • the tips 1 and the cathode electrodes 13 are coated by a first insulating layer 9 and by a second insulating layer 10 as shown in Figs. 2E and 2F.
  • the later step of etching back the second insulating layer 10 to obtain a planarized structure as shown in Figs. 2G and 2H is a chemical-mechanical polishing step.
  • the first insulating layer 9 acts as an etch stop layer.
  • a suitable material for this purpose is Si 3 N 4 .
  • the chemical-mechanical polishing step is controlled in a way that the nitride layer 9 covering the tips 1 forms an etch stop. This is very important to avoid damage of the tips caused by the etch back step.
  • Fig. 2I shows the device after the removal of those portions of first insulating layer 9 which were covering the tips. The tips now stick out against the surface of the second insulating layer 10.
  • the final device with a metal layer 4 forming the gate electrode and covering the upper portion of the tips is shown in Fig. 2K.
  • Figs. 1F and 2K clearly emphasize one major performance advantage of the proposed devices in that the tips 1 project above the surface of the surrounding electrode 4 forming the gate aperture 3.
  • Figs. 5A and 5B explain the dependencies between the tip/gate geometries and the current/voltage behaviour as a function of these geometries. Generally a low threshold voltage for the on-set of field emission is advantageous for each device irrespective of its specific application.
  • the range of the threshold voltages at which the individual tips emit is as small as possible. This allows for a better multiplexing behaviour.
  • the tip apex in Fig. 5A is below the surface level of the gate electrode, which corresponds to the left side of the zero line in Fig. 5B, and is moving towards zero, the voltage for a constant current is decreasing. The voltage decreases until the tip apex has reached a lowest level of a few hundred nanometers above the bottom surface of the gate electrode. If the tip apex increases to stick out of the gate elctrode surface level, the voltage stays constant.
  • FIGs. 3A to 3E and 4A to 4C offer processes for low cost large area field emitter devices. These devices are also suitable as cold electron emitters in vacuum microelectronic devices or as cathode devices in flat panel displays.
  • Fig. 3A the tip masks 8, preferable of SiO 2 , have been used to form truncated cones 1 on a silicon substrate by known photolithography and etching steps.
  • a further wet or dry etching step leads to the structure with overhanging tip masks in Fig. 3B.
  • thermal oxidation the truncated cones are shrinked to provide sharp tips and at the same time to build up the first insulating layer 9 covering the sharp tips and the surface of the substrate.
  • the overhanging tip masks have not been removed during or after the thermal oxidation step.
  • a metal layer 4 is deposited, preferably by evaporating a metal that closely sticks to the underlying insulating layer 9 and that allows to transport a small gate current.
  • the metal layer covers the insulating layer 9 as well as the overhanging tip masks as to be seen in Fig. 3D. Suitable is a chromium/gold deposition.
  • Fig. 3E the tip masks 8 with the metal coating thereon and those portions of the insulating layer 9 which directly cover the top part of the tips are removed. This may be done by etching with buffered HF.
  • Fig. 4A corresponds to the substrate 7 with sharpened tips 1 covered by the insulating layer 9 of Fig. 3C.
  • a second insulating layer 10 is deposited and etched back to a defined level.
  • a suitable material for this layer is photo resist or polyimide, materials which may be applied by spin coating. It is important that the overhanging tip masks are sticking out of the surface of the etched back insulating layer 10.
  • the gate electrode 4 is parallel to the surface of the substrate.
  • the dielectric portion formed by the first and second insulating layers 9, 10 is much thicker thus offering a much lower device capacity. This kind of device is therefore especially suitable for some high frequency circuits.
EP96101877A 1996-02-09 1996-02-09 Structure et procédé de fabrication d'un dispositif d'émission de champ Withdrawn EP0789382A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP96101877A EP0789382A1 (fr) 1996-02-09 1996-02-09 Structure et procédé de fabrication d'un dispositif d'émission de champ
JP3705897A JPH09223454A (ja) 1996-02-09 1997-02-05 電界放出装置の構造と製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP96101877A EP0789382A1 (fr) 1996-02-09 1996-02-09 Structure et procédé de fabrication d'un dispositif d'émission de champ

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2836279A1 (fr) * 2002-02-19 2003-08-22 Commissariat Energie Atomique Structure de cathode pour ecran emissif
US7239076B2 (en) * 2003-09-25 2007-07-03 General Electric Company Self-aligned gated rod field emission device and associated method of fabrication
US8076832B2 (en) 2007-05-25 2011-12-13 Sony Corporation Electron emitter structure and associated method of producing field emission displays

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102299325B1 (ko) * 2015-02-24 2021-09-06 에스티온 테크놀로지스 게엠베하 가스 이온화를 위한 x-선 소스

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2650119A1 (fr) * 1989-07-21 1991-01-25 Thomson Tubes Electroniques Dispositif de regulation de courant individuel de pointe dans un reseau plan de microcathodes a effet de champ, et procede de realisation
FR2700222A1 (fr) * 1993-01-06 1994-07-08 Samsung Display Devices Co Ltd Procédé de formation d'un dispositif à effet de champ en silicium.
US5394006A (en) * 1994-01-04 1995-02-28 Industrial Technology Research Institute Narrow gate opening manufacturing of gated fluid emitters
US5451830A (en) * 1994-01-24 1995-09-19 Industrial Technology Research Institute Single tip redundancy method with resistive base and resultant flat panel display
WO1996004674A2 (fr) * 1994-08-05 1996-02-15 Central Research Laboratories Limited Dispositif emetteur de champ a grille auto-alignee et ses procedes de fabrication

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2650119A1 (fr) * 1989-07-21 1991-01-25 Thomson Tubes Electroniques Dispositif de regulation de courant individuel de pointe dans un reseau plan de microcathodes a effet de champ, et procede de realisation
FR2700222A1 (fr) * 1993-01-06 1994-07-08 Samsung Display Devices Co Ltd Procédé de formation d'un dispositif à effet de champ en silicium.
US5394006A (en) * 1994-01-04 1995-02-28 Industrial Technology Research Institute Narrow gate opening manufacturing of gated fluid emitters
US5451830A (en) * 1994-01-24 1995-09-19 Industrial Technology Research Institute Single tip redundancy method with resistive base and resultant flat panel display
WO1996004674A2 (fr) * 1994-08-05 1996-02-15 Central Research Laboratories Limited Dispositif emetteur de champ a grille auto-alignee et ses procedes de fabrication

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
BUSTA H H: "VACUUM MICROELECTRONICS 1992", JOURNAL OF MICROMECHANICS & MICROENGINEERING, vol. 2, 1 January 1992 (1992-01-01), pages 43 - 74, XP000560006 *
GHIS A ET AL: "SEALED VACCUM DEVICES: FLUORESCENT MICROTIP DISPLAYS", IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 38, no. 10, 1 October 1991 (1991-10-01), pages 2320 - 2322, XP000225960 *
SPINDT C A ET AL: "PHYSICAL PROPERTIES OF THIN-FILM FIELD EMISSION CATHODES WITH MOLYBDENUM CONES", JOURNAL OF APPLIED PHYSICS, vol. 47, no. 12, 1 December 1976 (1976-12-01), pages 5248 - 5263, XP000560520 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2836279A1 (fr) * 2002-02-19 2003-08-22 Commissariat Energie Atomique Structure de cathode pour ecran emissif
WO2003071571A1 (fr) * 2002-02-19 2003-08-28 Commissariat A L'energie Atomique Structure de cathode pour ecran emissif
US7759851B2 (en) 2002-02-19 2010-07-20 Commissariat A L'energie Atomique Cathode structure for emissive screen
US7239076B2 (en) * 2003-09-25 2007-07-03 General Electric Company Self-aligned gated rod field emission device and associated method of fabrication
US8076832B2 (en) 2007-05-25 2011-12-13 Sony Corporation Electron emitter structure and associated method of producing field emission displays

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