EP0733961A1 - Reference current generator in CMOS technology - Google Patents

Abstract

In the current generator circuit a first current mirror (MP1,MP2) is formed with two circuit branches intended to be connected between two supply terminals (VDD,VSS). Ends of the branches comprise transistors (MP1,MN1;MP2,MN2) of opposite conductivity types connected in series. The second current mirror (MP1,MP3) generates an image (13) of the current (11) flowing in one of the branches. An active component (MN4) forming a variable conductance is mounted in series with the branch and is controlled in such a way that its value varies linearly with the current image (13). This conductance thus carries a current whose strength depends solely on the technological characteristics of the active component.

Description

The present invention relates to reference current generators produced in CMOS technology.

Figure 1 of the accompanying drawings shows an example of such a reference current generator produced according to the prior art. A description can be found in an article by E. Vittoz and J. Felrath, published in the journal IEEE, Journal of Solid State Circuits, Vol. SC-12, pp. 224-231, June 1977, and entitled "CMOS analog integrated circuits based on weak inversion operation" (CMOS analog integrated circuits based on weak inversion operation).

   où I_DO est un paramètre qui dépend de la tension grille - substrat, W et L sont respectivement la longueur et la largeur du canal et U_T est une tension proportionnelle à la température absolue, valant environ 26 mV à la température ambiante. Pour les transistors MNA et MNB de la figure 1, ayant même tension de grille et même longueur de canal, le rapport des courants est donné par:

This known generator comprises two P channel transistors, MPA and MPB forming a current mirror, two MNA and MNB transistors which are regulation transistors and a resistor R which forms the element on which the current reference is based. The whole of this assembly is connected between the supply voltages V _DD and V _SS , the reference current being able to be taken from the supply terminal V _DD , for example. The regulation transistors operate at low inversion, which means that their gate voltage Vg is less than their threshold voltage V _T and that the drain current I _D decreases exponentially with the source voltage V _S , according to the formula:

where I _DO is a parameter which depends on the grid-substrate voltage, W and L are respectively the length and the width of the channel and U _T is a voltage proportional to the absolute temperature, being worth approximately 26 mV at ambient temperature. For the MNA and MNB transistors of FIG. 1, having the same gate voltage and the same channel length, the current ratio is given by:

This ratio being fixed by the current mirror MPA-MPB, this relationship results in a well-defined value of the source voltage V _S1 of the transistor MNA:

The resistance R and the voltage V _S1 being fixed, the current i ₁ takes a well defined value: $${\mathit{\text{i}}}_{\text{1}}\text{=}\frac{{\mathit{\text{V}}}_{\mathit{\text{s}}\text{1}}}{\mathit{\text{R}}}$$

The objective of the designers of CMOS circuits being generally to create components having a size and a consumption as low as possible, the presence of a resistance in a circuit is often considered as an important disadvantage. Indeed, especially if the current to be supplied is low, a resistance of high value is required, which requires an excessive silicon surface, if the resistivity (resistance per square) of the layer serving as resistance is low.

In addition, the reproducibility of the resistance is often poor in standard CMOS technology, which is incompatible with the precision that is generally required of a reference current generator.

The object of the invention is to propose a reference current generator free of resistance.

The subject of the invention is therefore a reference current generator produced in CMOS technology comprising a first current mirror which forms two circuit branches intended to be connected between supply terminals of opposite polarities and each comprising a group of connected transistors in series and of opposite conductivity types, a first of said branches comprising, put in series with its transistors, stabilization means for impose on the transistor connected to it in this first branch a predetermined fixed source voltage, this reference current generator being characterized in that it also comprises a second current mirror for generating an image of the current flowing in said first branch, said stabilization means comprising an active component forming a variable conductance mounted in series in said first branch and controlled in such a way that its value varies non-linearly with said current image, this conductance thus being traversed by a current whose intensity depends solely on the technological characteristics of said active component.

Thanks to these characteristics and in particular to the stabilization means as defined above, the generator according to the invention is formed exclusively of active components which can be easily integrated with good reproducibility and which only take on the integrated circuit chip not a lot of place.

• la figure 1 est un schéma d'un générateur de courant de référence selon la technique antérieure;
• la figure 2 est un schéma de principe d'un générateur de courant de référence selon l'invention;
• la figure 3 représente un schéma d'un générateur de courant de référence permettant de fournir un courant de référence à plusieurs utilisateurs;
• la figure 4 montre un exemple d'un circuit de démarrage pour le générateur selon l'invention;
• la figure 5 représente un schéma d'une réalisation pratique du générateur selon l'invention;
• la figure 6 est un graphique illustrant le fonctionnement du générateur selon l'invention;
• les figures 7, 8 et 9 montrent des variantes de réalisation du générateur selon l'invention.

Other characteristics and advantages of the invention will appear during the description which follows, given solely by way of example and made with reference to the appended drawings in which:

• Figure 1 is a diagram of a reference current generator according to the prior art;
• Figure 2 is a block diagram of a reference current generator according to the invention;
• FIG. 3 represents a diagram of a reference current generator making it possible to supply a reference current to several users;
• FIG. 4 shows an example of a starting circuit for the generator according to the invention;
• FIG. 5 represents a diagram of a practical embodiment of the generator according to the invention;
• Figure 6 is a graph illustrating the operation of the generator according to the invention;
• Figures 7, 8 and 9 show alternative embodiments of the generator according to the invention.

We will first refer to Figure 2 which shows a block diagram of the preferred embodiment of the invention.

The sources of two channel P transistors, respectively MP1 and MP2 are connected to a supply line V _DD and their gates are connected to each other to form a node 1. The drains of these transistors are respectively connected to the drains of two N channel transistors, MN1 and MN2. The connection between the drain of transistor MP1 and the transistor MN1 is also connected to node 1.

The gates of the transistors MN1 and MN2 are also connected together and form a node 2 to which the drain of the transistor MN2 is also connected.

Two N channel transistors, MN3 and MN4 are connected by their sources to a supply line V _SS , their gates being connected to each other to form a node 3 to which the drain of transistor MN3 is also connected. As will appear later, the transistor MN4 is an active component operating as a controlled conductance.

The source of transistor MN1 is connected to the drain of transistor MN4 thus forming a node 4, and that of transistor MN2 is connected to the supply line V _SS .

The drain of transistor MN3 is connected to the drain of a channel P transistor, MP3, the source of which is connected to the supply line V _DD and the gate of which is connected to node 1.

The transistors MN1 and MN2 of this circuit operate at low inversion, which means that their gate voltage is lower than their threshold voltage V _T and that the drain current I _D is a decreasing exponential function of the source voltage V _S , according to formula (1). Furthermore, the transistors MN3 and MN4 work in strong inversion, in other words their gate voltage is higher than their threshold voltage V _T. Finally, the voltage V _DD is chosen to be high enough so that, except for the transistor MN4, all the transistors are in saturation.

It is assumed that the three branches of the circuit, formed by MP1-MN1-MN4, MP2-MN2 and MP3-MN3, are traversed respectively by the currents i ₁ , i ₂ and i ₃ .

If, on the other hand, a dimensional ratio S = W / L is defined for each transistor in FIG. 2, we will call S _n1 , S _n2 , S _n3 , S _n4 , S _p1 , S _p2 and S _p3 these ratios for the seven circuit transistors. As already indicated above, the P channel transistors are in saturation so that they define fixed current ratios as follows: $$\frac{{\mathit{\text{i}}}_{\text{2}}}{{\mathit{\text{i}}}_{\text{1}}}\text{=}\frac{{\mathit{\text{S}}}_{\mathit{\text{p}}\text{2}}}{{\mathit{\text{S}}}_{\mathit{\text{p}}\text{1}}}\text{and}\frac{{\mathit{\text{i}}}_{\text{3}}}{{\mathit{\text{i}}}_{\text{1}}}\text{=}\frac{{\mathit{\text{S}}}_{\mathit{\text{p}}\text{3}}}{{\mathit{\text{S}}}_{\mathit{\text{p}}\text{1}}}$$

   avec: $${\mathit{\text{K}}}_{\text{1}}\text{=}\frac{{\mathit{\text{S}}}_{\mathit{\text{p}}\text{2}}{\mathit{\text{S}}}_{\mathit{\text{n}}\text{1}}}{{\mathit{\text{S}}}_{\mathit{\text{p}}\text{1}}{\mathit{\text{S}}}_{\mathit{\text{n}}\text{2}}}$$

The source voltage Vs _n1 of the transistor MN1, which is also the drain voltage Vd _n4 of the transistor MN4, stabilizes at a well defined value if, as already indicated above, the transistors MN1 and MN2 are in weak inversion, this which involves, by application of the relation (3), as in the circuit of the prior art: $${\mathit{\text{VS}}}_{\mathit{\text{not}}}{}_{\text{1}}\text{=}{\mathit{\text{Vd}}}_{\mathit{\text{not}}}{}_{\text{4}}\text{=}{\mathit{\text{U}}}_{\mathit{\text{T}}}\text{* 1}\mathit{\text{not}}\text{((}\mathit{\text{K}}\text{1)}$$

with: $${\mathit{\text{K}}}_{\text{1}}\text{=}\frac{{\mathit{\text{S}}}_{\mathit{\text{p}}\text{2}}{\mathit{\text{S}}}_{\mathit{\text{not}}\text{1}}}{{\mathit{\text{S}}}_{\mathit{\text{p}}\text{1}}{\mathit{\text{S}}}_{\mathit{\text{not}}\text{2}}}$$

In addition, U _T = kT / q is the thermodynamic tension, proportional to the absolute temperature T, and is worth approximately 26 mV at room temperature.

To facilitate understanding of the operation of the generator shown in FIG. 2, it is assumed that a current i ₁ is sent to the source of transistor MN1. By the effect of the current mirror that constitute the transistors MP1 and MP2, an identical current i ₂ is sent into the transistor MN2 whose gate voltage Vg _n2 adjusts to pass this current. This gate voltage is also applied to the gate of transistor MN1. In order for this transistor MN1 to supply the current i ₁ , its source voltage Vs _n1 must take a positive value, since this transistor is wider than the transistor MN2. If, as already indicated, the transistors MN1 and MN2 are in weak inversion, therefore if i ₁ is small, this source voltage Vs _n1 is independent of the current i ₁ and takes the value given by equation (2).

By the effect of the current mirror formed by the transistors MP1 and MP3, a current i ₃ is sent to the transistor MN3 and this current takes the form: $${\mathit{\text{<figure-callout id="3" label="i" filenames="imgf0004.png" state="{{state}}">i</figure-callout>}}}_{\text{3}}\text{=}{\mathit{\text{i}}}_{\text{1}}\frac{{\mathit{\text{S}}}_{\mathit{\text{p}}\text{3}}}{{\mathit{\text{S}}}_{\mathit{\text{p}}\text{1}}}$$

In addition, the transistors MN3 and MN4 are in strong inversion and the transistor MN3 is in saturation from where: $${\mathit{\text{<figure-callout id="3" label="i" filenames="imgf0004.png" state="{{state}}">i</figure-callout>}}}_{\text{3}}\text{=}\frac{\text{1}}{\text{2}}{\text{β}}_{\mathit{\text{not}}\text{3}}\text{((}{\mathit{\text{Vg}}}_{\mathit{\text{not}}\text{3}}\text{-}{\mathit{\text{V}}}_{\mathit{\text{Tn}}}{\text{)}}^{\text{2}}$$

This current produces a voltage Vg _n3 on the gate of transistor MN3 of the form (β _n3 being the gain factor of the transistor): $${\mathit{\text{Vg}}}_{\mathit{\text{not}}\text{3}}\text{=}\sqrt{\frac{\text{2}{\mathit{\text{i}}}_{\text{3}}}{{\text{β}}_{\mathit{\text{not}}\text{3}}}}\text{+}{\mathit{\text{V}}}_{\mathit{\text{Tn}}}$$

The transistor MN4 has the same gate voltage, but its drain voltage Vd _n4 = Vs _n1 is less than its saturation voltage, therefore (β _n4 being the gain factor of this transistor):

By combining equations (8), (10) and (11), we find the current i ₁ 'which flows in the transistor MN4:

We obtain the same expression if we express the effect of transistor MN4 by its equivalent resistance:

The current i ₁ , expressed using this relation (13) and the relation (4) still depends on Vg _n3 . By eliminating Vg _n3 and i ₃ using equations (8) and (10), we find expression (12).

FIG. 6 shows the shape of this current i ' ₁ , the graph showing on the abscissa the current i ₁ imposed by the current mirror and on the ordinate the theoretical currents determined according to the above equations.

It is therefore seen that the current which is established corresponds to the equality (point of intersection of the curves) between the current i ₁ sent in the source of the transistor MN1 and the current i ₁ 'produced in the transistor MN4. Now, equation (12) shows that this current is a parabolic function of i ₁ , because the transistor MN3 is saturated, while the transistor MN4 operates in unsaturated regime due to its low drain voltage.

   avec: $${\mathit{\text{K}}}_{\text{2}}\text{=}\frac{{\mathit{\text{S}}}_{\mathit{\text{p}}\text{3}}{\mathit{\text{S}}}_{\mathit{\text{n}}\text{4}}}{{\mathit{\text{S}}}_{\mathit{\text{p}}\text{1}}{\mathit{\text{S}}}_{\mathit{\text{n}}\text{3}}}$$

In reality, there is only one condition which can be established in the circuit, it is when i ₁ '= i ₁ Consequently, we find for the real current i ₁ in the branch of the circuit comprising the transistors MN1 and MN4:

with: $${\mathit{\text{<figure-callout id="2" label="K" filenames="imgf0001.png,imgf0003.png" state="{{state}}">K</figure-callout>}}}_{\text{2}}\text{=}\frac{{\mathit{\text{S}}}_{\mathit{\text{p}}\text{3}}{\mathit{\text{S}}}_{\mathit{\text{not}}\text{4}}}{{\mathit{\text{S}}}_{\mathit{\text{p}}\text{1}}{\mathit{\text{S}}}_{\mathit{\text{not}}\text{3}}}$$

   dans laquelle:

By substituting Vs _n1 (equation 6) in equation (14), we find: $${\mathit{\text{i}}}_{\mathit{\text{R}}}\text{=}{\mathit{\text{K}}}_{\mathit{\text{eff}}}{\text{β}}_{\mathit{\text{not}}\text{4}}{\mathit{\text{<figure-callout id="2" label="U T" filenames="imgf0001.png,imgf0003.png" state="{{state}}">U </figure-callout>}}}_{\mathit{\text{T}}}^{}$$

in which:

• a) le courant i_R est proportionnel au produit du facteur de gain β₄ du transistor MN4 et du carré de la tension thermodynamique U_T;
• b) le facteur de proportionnalité K_eff dépend uniquement des rapports dimensionnels des transistors; et
• c) le courant i_R est indépendant des tensions de seuil V_T des transistors utilisés.

Equations (10 and (11) show that:

• a) the current i _R is proportional to the product of the gain factor β ₄ of the transistor MN4 and the square of the thermodynamic voltage U _T ;
• b) the proportionality factor K _eff depends only on the dimensional ratios of the transistors; and
• c) the current i _R is independent of the threshold voltages V _T of the transistors used.

It therefore follows that the current i _R is a stable parameter of the circuit so that it constitutes a current reference. It will be noted that this current is only determined by the dimensioning of the transistors, in other words by the topography of the circuit which can be reproduced with precision from one circuit to another.

   où β_n40 et U_T0 se rapportent à une température de référence T₀ (température ambiante), et m est un exposant voisin de 2. En combinant les équations (16) et (18), le courant i_R devient: $${\mathit{\text{i}}}_{\text{1}}\text{=}{\mathit{\text{K}}}_{\mathit{\text{eff}}}{\text{β}}_{\mathit{\text{n}}\text{40}}{\mathit{\text{U}}}_{\mathit{\text{T}}\text{0}}^{\text{2}}{\left(\frac{\mathit{\text{T}}}{{\mathit{\text{T}}}_{\text{0}}}\right)}^{\text{2-}\mathit{\text{m}}}$$

Furthermore, we know that the gain factor of a transistor depends on the absolute temperature in the same way as mobility, according to the law (applied to transistor MN4): $${\text{β}}_{\mathit{\text{not}}\text{4}}{\text{= β}}_{\mathit{\text{not}}\text{40}}{\left(\frac{{\mathit{\text{T}}}_{\text{0}}}{\mathit{\text{T}}}\right)}^{\mathit{\text{m}}}{\text{= β}}_{\mathit{\text{not}}\text{40}}{\left(\frac{{\mathit{\text{U}}}_{\mathit{\text{T}}\text{0}}}{{\mathit{\text{U}}}_{\mathit{\text{T}}}}\right)}^{\mathit{\text{m}}}$$

where β _n40 and U _T0 relate to a reference temperature T ₀ (room temperature), and m is an exponent close to 2. By combining equations (16) and (18), the current i _R becomes: $${\mathit{\text{i}}}_{\text{1}}\text{=}{\mathit{\text{K}}}_{\mathit{\text{eff}}}{\text{β}}_{\mathit{\text{not}}\text{40}}{\mathit{\text{<figure-callout id="0" label="U T" filenames="imgf0003.png" state="{{state}}">U </figure-callout>}}}_{\mathit{\text{T}}}^{\text{0}}{\left(\frac{\mathit{\text{<figure-callout id="0" label="T T" filenames="imgf0003.png" state="{{state}}">T </figure-callout>}}}{{\mathit{\text{T}}}_{}}\right)}^{\text{2-}\mathit{\text{m}}}$$

The first three terms of this equation being defined at a fixed temperature and if m is close to 2, it can be seen that the current varies little with temperature, which constitutes another advantage of the circuit of the invention.

The current reference can be taken from the supply terminal V _DD , the current serving as a reference then being formed by the sum of the currents i ₁ (i _R ), i ₂ and i ₃ .

We will now refer to FIG. 3 which shows how the reference current generator can produce several other reference currents.

The circuit of Figure 3 uses the diagram of Figure 2 so that there are the same transistors connected in the same way. It shows three other ways to generate a reference current.

The first consists in using an additional channel transistor P, MP4, the gate of which is connected to node 1. Its source is connected to the terminal VDD, while the reference current i ₄ can be taken from the drain of this transistor.

The second possibility consists in using an N channel transistor, MN5, the gate of which is connected to the drain of transistor MN3, the source of which is connected to terminal V _SS of the circuit and the drain of which will receive the reference current i ₅ .

The third possibility consists in also using an N channel transistor, MN6, the gate of which is connected to node 2 and which, moreover, is connected in the same way as the transistor MN5. It will be supplied with the reference current i ₆ .

For the transistors MP4, MN5 and MN6 to provide currents close to the desired reference currents, they must be in saturation, that is to say that their drain-source voltage must, in absolute value, be greater than a limit Vd _sat . This implies that the circuit supplied by the transistor MP4 is connected to a lower potential than the voltage V _DD , for example the voltage V _SS and that the circuits supplied by the transistors MN5 and MN6 are connected to a higher potential than the voltage V _SS , for example V _DD .

As the gates of these auxiliary transistors MP4, MN5 and MN6 do not charge the nodes to which they are connected, we can multiply the number and thus provide reference currents at many points of a larger circuit including the current generator can be part.

FIG. 4 shows more particularly an example of a starting circuit for the reference current generator according to the invention. Indeed, such a circuit is necessary to avoid that the generator remains initially blocked. In the example shown, the starting circuit comprises an N channel transistor, MN7, the source of which is connected to the terminal V _ss and the drain of which is connected to node 1. The circuit further comprises a second N channel transistor, MN8 of which the gate is connected to node 2, the source of which is connected to the terminal V _SS and the drain of which is connected both to the gate of the transistor MN7 and to a capacitor C which is also connected to the terminal V _DD .

The capacitor C is discharged at startup which causes the transistor MN7 to flow and an initial current to flow in the transistors MP1 to MP3. When the circuit is traversed by a sufficient current, the transistor MN8 charges the capacitor C, which blocks the transistor MN7. The generator then operates at its normal speed.

FIG. 5 schematically shows an advantageous way of producing the generator according to the invention. This diagram includes both the transistors to generate a reference current and those used to start the circuit.

To achieve the topography of the generator, it is advantageous to distribute the transistors according to the nature of their operating conditions. Thus, preferably belong to a first group MP all the P channel transistors with strong inversion, to a second group MNA the transistors N channel with low inversion, while a third group includes the N channel transistors with strong inversion.

To obtain a precise pairing, it is advantageous to define in each group a unitary transistor and to realize the various functionalities of the transistors by putting in series or in parallel the number of unitary transistors desired for a good dimensional ratio. For example, the transistor MN1 in FIG. 2 can actually be formed by six unitary transistors arranged in parallel

To obtain a strong inversion, it is desirable to respect the following relation: $$\frac{\mathit{\text{i}}}{\text{β}}{\text{> 5 · 10}}^{\text{-3}}{\mathit{\text{<figure-callout id="2" label="V" filenames="imgf0001.png,imgf0003.png" state="{{state}}">V</figure-callout>}}}^{\text{2}}$$

To achieve a small inversion the following relation will preferably be respected: $$\frac{\mathit{\text{i}}}{\text{β}}\text{<0.5}{\mathit{\text{<figure-callout id="2" label="U T" filenames="imgf0001.png,imgf0003.png" state="{{state}}">U </figure-callout>}}}_{\mathit{\text{T}}}^{}{\text{≅ 3 · 10}}^{\text{-4}}{\mathit{\text{<figure-callout id="2" label="V" filenames="imgf0001.png,imgf0003.png" state="{{state}}">V</figure-callout>}}}^{\text{2}}$$

If the reference currents are imposed, the relations (19) and (20) define the conditions to be satisfied on the gain factors β.

et $${\mathit{\text{K}}}_{\text{2}}\text{=}\frac{{\text{β}}_{\mathit{\text{p}}\text{3}}}{{\text{β}}_{\mathit{\text{p}}\text{1}}}\text{=}\frac{{\mathit{\text{W}}}_{\mathit{\text{p}}\text{3}}}{{\mathit{\text{W}}}_{\mathit{\text{p}}\text{1}}}$$

Referring to the example of FIG. 5, the following dimensional ratios can be used (without this being in any way limiting for the invention): $${\mathit{\text{K}}}_{\text{1}}\text{=}\frac{{\text{β}}_{\mathit{\text{not}}\text{1}}}{{\text{β}}_{\mathit{\text{not}}\text{2}}}\text{=}\frac{{\mathit{\text{W}}}_{\mathit{\text{not}}\text{1}}}{{\mathit{\text{W}}}_{\mathit{\text{not}}\text{2}}}$$

and $${\mathit{\text{<figure-callout id="2" label="K" filenames="imgf0001.png,imgf0003.png" state="{{state}}">K</figure-callout>}}}_{\text{2}}\text{=}\frac{{\text{β}}_{\mathit{\text{<figure-callout id="3" label="p" filenames="imgf0004.png" state="{{state}}">p</figure-callout>}}\text{3}}}{{\text{β}}_{\mathit{\text{p}}\text{1}}}\text{=}\frac{{\mathit{\text{W}}}_{\mathit{\text{p}}\text{3}}}{{\mathit{\text{W}}}_{\mathit{\text{p}}\text{1}}}$$

In the following example, we have chosen K ₁ = 6 and K ₂ = 3. This example gives some details on a practical design of the reference current generator according to the invention, produced using CMOS technology. current, whose main parameters have the following typical values: Transistor type channel N channel P V _T * 0.6 -0.6 β for W = L ** 65 24 * in Volts; ** in µA / V ²

The values of the currents can be chosen as follows: $${\text{i}}_{\text{1}}{\text{= 20nA, i}}_{\text{2}}{\text{= 20nA, i}}_{\text{3}}{\text{= 60nA, i}}_{\text{4}}{\text{= 40nA and <figure-callout id="5" label="i" filenames="imgf0003.png" state="{{state}}">i</figure-callout>}}_{\text{5}}\text{= 120nA.}$$

As already indicated, it is advantageous to design the generator using three groups of transistors. Under these conditions, all the transistors in each group can be identical and have for example the following dimensions: MP group MNA Group MNB Group W * 6 50 6 L * 50 6 207 i / β 6.6710 ^-3 3.710 ^-5 3.10 ^-2 β ** 2.88 542 1.88 * in µm; ** in µA / V ²

It can be seen from this example that the generator according to the invention is well suited to supply reference currents of less than 1 μA. Its size is reduced, while its own consumption can be of the order of 5i ₁ only.

Figures 7, 8 and 9 show three variants of the reference current generator according to the invention.

In the embodiment of the generator that has just been described (FIGS. 3, 4 and 5), the saturation transistors may, for a given gate voltage and especially if the length of their channel is small, present a slight variation. drain current depending on the drain voltage. Thus, the reference current can be subject to a certain dependence on the supply voltage (a few% per Volt). In the circuit shown, it is mainly the transistors MN1 and MN2 which are responsible for this effect.

If the accuracy of the reference current does not tolerate this dependence, it is then desirable to use the circuit shown in Figure 7.

In this circuit, two auxiliary transistors MNl1 and MN12 (called "cascode transistors") are respectively inserted in series with the transistors MN1 and MN2. The gates of these transistors are connected in common to the junction between the transistor MN12 and the transistor MP2. It follows that the drain voltages of the transistors MN1 and MN2 are substantially equal and independent of variations in the voltage V _DD .

FIG. 8 shows a variant offering the possibility of adjusting the reference current from outside the circuit. To obtain this result, the MP3 transistor is broken down into several unitary transistors MP3a, MP3b, MP3c .... which are respectively connected in series with as many switching transistors P channel Sa, Sb, Sc The gate of the first transistor Sa is directly connected to terminal V _SS . He is therefore a driver at all times. The gates of the other transistors Sb Sc .... are connected to a logic control circuit CL making it possible to make these transistors selectively conductive. Thus, the effective width of the MP3 transistor can be adjusted from the outside, that is to say its parameter K ₂ (equation 15). This results in a corresponding variation of the parameter K _eff (equation 16) and therefore of the current i ₁ (equation 20). This circuit is especially desirable if, during manufacture, the current dispersion from one batch of circuits to another is significant.

FIG. 9 shows a third variant of the generator according to the invention in which, all things also equal when considering FIG. 2, the source of transistor MN3 is connected to the drain of a transistor MN4 'and to the source of transistor MN1.

In this case, the transistor MN4 'is therefore traversed by the sum of the currents i ₁ and i ₃ . We then obtain roughly the same operation as that of the circuit of FIG. 2, by dimensioning the transistor MN4 'so that it has the same drain voltage as the transistor MN4, but for a current i ₁ + i ₃ instead of i ₁ , therefore K ₂ +1 times greater.

The invention is not limited to the embodiments which have just been described and which have been shown in the drawings. For example, embodiments comprising circuits having the same functionalities, but produced using transistors of opposite conductivity types also belong to the present invention.

Claims (14)

Reference current generator produced in CMOS technology comprising a first current mirror which forms two circuit branches intended to be connected between supply terminals (V _DD , V _SS ) of opposite polarities and each comprising a group of transistors (MP1 , MN1; MP2, MN2) connected in series and of opposite conductivity types, a first of said branches comprising, put in series with its transistors, stabilization means for imposing on the transistor (MN1) which is connected to it in this first branch predetermined fixed source voltage (Vs _n1 ), this reference current generator being characterized in that it also includes a second current mirror (MP1, MP3) for generating an image (i ₃ ) of the current (i ₁ ) flowing in said first branch, and in that said stabilization means comprise an active component (MN4, MN4 ') forming a variable conductance connected in series in said pr first branch and controlled in such a way that its value varies non-linearly with said current image (i ₃ ), this conductance thus being traversed by a current whose intensity depends solely on the technological characteristics of said active component. Reference current generator according to claim 1, characterized in that said active component is a transistor (MN4, MN4 ') operating in unsaturated conditions and in strong inversion. Reference current generator according to any one of claims 1 and 2, characterized in that said second current mirror constitutes a third circuit branch comprising, connected in series, two transistors (MP3, MN3), respectively of types of opposite conductivity and on the common node from which said control voltage is taken (Vg _n3 ). Reference current generator according to claim 3, characterized in that the gate of the transistor forming said active component (MN4, MN4 ') is connected to a node which connects said connected transistors (MP3, MN3) to each other in series, the transistor (MN3) among these transistors connected in series having the same type of conductivity as that of the transistor (MN4) forming the active component, having its gate connected to said node and its source connected to a source of fixed potential. Current generator according to claim 4, characterized in that said fixed potential source is a node of said first branch, connected to said transistor forming said active component (MN4 '). Current generator according to claim 4, characterized in that said fixed potential source is the terminal (V _SS ) among said supply terminals which is common to said transistor (MN4) forming said active component. Reference current generator according to any one of the preceding claims, characterized in that, with the exception of said active component (MN4, MN4 '), all of its transistors operate in saturated state. Reference current generator according to any one of Claims 3 to 7, characterized in that each of said branches comprises a P channel transistor (resp. MP1, MP2, MP3) and at least one N channel transistor (resp. MN1, MN2 , MN3) and in that said transistor operating in unsaturated conditions is an N channel transistor (MN4; MN4 '). Reference current generator according to claim 8, characterized in that said transistor operating in unsaturated conditions (MN4) is connected in series in said first branch. Reference current generator according to claim 8, characterized in that said transistor operating in unsaturated conditions (MN4 ') is connected in series in both said first branch and said third branch. Reference current generator according to any one of Claims 3 to 10, characterized in that it comprises at least one additional transistor (MP4, MN5, MN6) for drawing a reference current (i ₄ , i ₅ , i ₆ ), connected so as to be controlled by the voltage prevailing on the node (resp. 1, 2, 3) between the transistors of opposite conductivity types in a respective one of said branches. Reference current generator according to any one of the preceding claims, characterized in that said first and second branches comprise at least one additional transistor (MN11, MN12) in series. Reference current generator according to any one of Claims 3 to 12, characterized in that the transistors of the same type of conductivity and / or of the same type of inversion are mounted respectively in separate groups (MP, MNA, MNB) and in that at least one of the transistors in each group is formed by a predetermined number of unitary transistors having the same dimensional characteristics and together forming said transistor. Reference current generator according to claim 13, characterized in that the unitary transistors of at least one of said groups of transistors (MP) are connected in series with a switching transistor (Sa, Sb, Sc) making it possible to select said unit transistor, and in that it further comprises a logic circuit (CL) to allow the selective control of said switching transistors.

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