EP0730221A2 - Procédé et dispositif pour accélérer l'exécution d'instructions de retour - Google Patents

Procédé et dispositif pour accélérer l'exécution d'instructions de retour Download PDF

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Publication number
EP0730221A2
EP0730221A2 EP96103172A EP96103172A EP0730221A2 EP 0730221 A2 EP0730221 A2 EP 0730221A2 EP 96103172 A EP96103172 A EP 96103172A EP 96103172 A EP96103172 A EP 96103172A EP 0730221 A2 EP0730221 A2 EP 0730221A2
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EP
European Patent Office
Prior art keywords
return
value
program
program flow
prediction table
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP96103172A
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German (de)
English (en)
Other versions
EP0730221A3 (fr
EP0730221B1 (fr
Inventor
Akira Katsuno
Sunil W. Savkar
Michael C. Shebanow
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
HAL Computer Systems Inc
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Filing date
Publication date
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Publication of EP0730221A3 publication Critical patent/EP0730221A3/fr
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Publication of EP0730221B1 publication Critical patent/EP0730221B1/fr
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30054—Unconditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30058—Conditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30123—Organisation of register space, e.g. banked or distributed register file according to context, e.g. thread buffers
    • G06F9/30127—Register windows
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
    • G06F9/4482—Procedural
    • G06F9/4484—Executing subprograms
    • G06F9/4486—Formation of subprogram jump address

Definitions

  • the present invention relates to methods and apparatuses for controlling instruction flow in data processors and, in particular, for reducing the time for return from program flow changes such as the execution of subroutine calls and other similar instruction codes using return prediction.
  • branch direction taken or not-taken
  • branch address target address or address next to the branch instruction
  • An instruction set within a data processor usually contains a multitude of transfers of that instruction flow from a current pointer and a program counter located in the instruction flow to a new location.
  • the new location is the start of a sub-routine call or a piece of code that will be executed, there will be a need to return to the original instruction set from where the call was made.
  • the subroutine is a short sequence of code to which the instruction flow calls on to execute and then returns to the main location of the code sequence.
  • the instruction When the instruction leaves the main code sequence from a first location on the program counter, it jumps to a second location on the program counter where the start of the desired sub-routine is designated. Once the sub-routine call is complete, the instruction flow must jump back not to the first location, but to a third location which designates the next instruction in the main code sequence. Jumping back to the first location simply executes the same sub-routine call such as when a retry is needed for a default loop.
  • the procedure of making the call to transfer the instruction flow and then waiting for its return to the main code sequence is one of the limiting factors on the execution speed of the microprocessor.
  • the return is controlled through a register value which is read.
  • This value is stored to a dedicated register of some type depending on the microprocessor architecture. It may store a value equivalent to the program counter at the first location or to another location already advanced to the next instruction. This value functions as the return address stored in the register file which can be any file specifically stated to hold the location of the return from the program flow change.
  • the execution is stalled waiting for that register to be read, waiting for that return address to be put back into the program counter and waiting to continue the program execution.
  • the present invention provides a method of accelerating the return from program flow changes in the execution of a program containing a plurality of instructions.
  • the method includes the step of fetching a program flow change and determining if the program flow change contains a return instruction.
  • a value a value of a program counter is registered that identifies a location in the program for the return from the program flow change.
  • the program flow change is executed.
  • a predicted value is speculated from a return prediction table and the program flow change returns in accordance with the speculative value.
  • the present invention also contemplates an apparatus including a processor having an instruction flow control circuit for executing a program having a plurality of instructions.
  • the circuit includes a fetch program counter, program counter and register file.
  • the apparatus includes a return prediction table coupled to and accessable by the fetch program counter prior to any point the fetch program counter can access the register file.
  • the present invention contemplates the acceleration of control transfer instructions for the microprocessor in order to speed up the overall execution capability of the computer.
  • FIG. 1 is a block diagram of an embodiment of the present invention, including a fetch program counter 10, an instruction memory 12, a plurality of issue latches 14, and a decoder register file 16 of the issue unit.
  • Fetch program counter 10 receives an input fetch program count indication FPC_D, and produces an output fetch program count indication which it provides as an input to instruction memory 14, according to the present invention.
  • instruction memory 14 produces a count of instructions fetched, FETCH_CNT, as well as providing fetched instructions in accordance with the fetch program count to issue latches 14.
  • Issue latches 14 in turn provide an indication of the number of valid instructions, NV_Q, in the issue latches 14, and further provide issued instructions to decoder register file issue unit 16 which is couple in turn to an execution unit 36 and a register file 38.
  • PC_Q means the current program counter (PC) value in the issue cycle
  • FPC_Q means the fetch program counter value (FPC) in the current cycle
  • NV_D is the number of instructions which will be valid in the next cycle.
  • a program counter 18 clocks once per cycle, responding to an input program count signal from multiplexer 34, PC_D, with an output program count signal, PC_Q.
  • the program count provides an indication of the architectural device operating in the current cycle.
  • PC_D is the value of the next program count (PC); and
  • FPC_D is the value of the next fetch program count (FPC).
  • a specific embodiment is illustrated with a current window pointer 20 indexing into a return prediction table 22.
  • the current window pointer 20 identifies one or more register windows. Register windows are used when executing a control transfer such as subroutine. During a subroutine call, a save at the top of a subroutine call is performed and changes to a new register window. As a result, several free register windows are used without changing or modifying the state of the previous routine that called that subroutine.
  • the SPARC V9 architecture uses the call register windows which at the beginning of a sub-routine call does a change of windows.
  • the original set of registers that were being used for the original program from whence the call came are reserved. They are not available for use. They are stored off and instead it swap to a new window of values which are available to read and write.
  • the hardware supports a large number of registers even though only a small number of registers are addressed at any one time. In the SPARC V9 architecture for example, registers are defined with five bits allowing access to thirty-two logically addressable registers at any one time.
  • the current window pointer explicitly functions by pointing into a window of address values which are stored off.
  • the inventive embodiment receives a call instruction or a JUMP call instruction and decodes during fetch time. One of these instructions issues into the microprocessor and simultaneously writes the instruction to the register value of the current window. For the SPARC V9 architecture, this is register 15.
  • the value based on the current window pointer is written into the file that is indexed by the current window pointer.
  • the current window pointer is 2-bits in size and accordingly indexes explicitly to 4 distinct locations.
  • a return such as but not limited to JUMP return, a restore, or a retry
  • the current window pointer restores that program counter in that location that has been written into the return prediction table which is addressable.
  • the present invention can readily be used in other microprocessor systems.
  • the current window pointer can have more than 2-bits. Accordingly, with 8 register windows there would be 3 bits and more with a larger number of register windows.
  • Performing a save or restore moves back to another register window.
  • DEC decrements
  • the current window pointer usually does not jump from 00 to 11, except in performing back-ups or the like. For a SPARC V9 architecture which speculatively executes instructions, if instructions were speculated incorrectly at some prior time at location X minus delta, the execution backs up to this prior location. If the current pointer gets backed up, the program jumps value.
  • the index and the return prediction table are separate from the register file itself.
  • the return prediction table is used to speculatively execute the return. In situations that the return value is incorrect, it is pushed onto the stack.
  • the FPC fetch program counter is a speculative PC. That value back is feed back into the FPC for use in fetching instructions into the issue latches.
  • a value is popped off to speculate with, it will be stored in a watch point register 24.
  • the watch point register is pointed at once the actual return is finished execution.
  • the watchpoint register and method is preferred for use with the present invention, but conventional techniques are also suitable.
  • the watchpoint register can watch a plurality of predicted branch or jump-and-link instructions simultaneously. Second, it can grab a plurality of condition-code data or calculated jump-and-link addresses for which predicted branch or jump-and-link instructions are waiting by simultaneously monitoring or watching data forward buses from a plurality of execution units. Third, it can generate a plurality of misprediction signals of branch or jump-and-link instructions simultaneously. Fourth, it can store alternate branch address or predicted jump-and-link address in a single shared storage area. Fifth, it sends the correct branch address or jump-and-link address for instruction fetch when misprediction is detected by watchpoint.
  • the watchpoint registers are multipurpose. They check branch predictions, JMPL predictions, and supply a correct branch/JMPL address for refetching instructions after a backup when the original prediction was incorrect. They are called “watchpoint” registers because they sit on data forward distribution buses and monitor results from the several execution units. There are usually watchpoint registers corresponding to each checkpoint.
  • the function of the return prediction table is to provide speculative values of what the return address will be prior to the finish of execution of the instruction.
  • a comparison is made through a comparator 26 to assure that the predicted value was actually correct.
  • the comparator 26 leads into a control logic 28 which is one of the feeds into a multiplexer 30. If the comparison is incorrect, the program flow will back up and the correct return value is routed eventually to the FPC and to the PC.
  • a single window register 32 is used when there is no need to increment or decrement the values. Usually this embodiment is used for the last PC that is called. Since the calls come in pairs with a return, this embodiment is useful with that final call.
  • the present invention uses an indexed return prediction table for accelerating the fetch of instructions for the return from any type of program flow change or control transfer. As a result, the execution of the system or apparatus hardware is accelerated.
  • the present invention fetches a program flow change and determines if it contains a return function. As a result, the present invention stores the PC value for the return address from a program flow change in the return prediction table indexed by the current window pointer.
  • the current window pointer may be defined by the hardware itself.
  • the fetch program counter 10 and the PC 18 are updated in the case of a return from program flow change by indexing with the current window pointer into the return prediction table.
  • instructions such as a subroutine call which indicate a program flow change are fetched and executed by the system. It is after fetching of the instruction that the PC value is written. Usually, although not necessarily, this occurs while issuing the instruction to the remainder of the system. In the preferred embodiment, the storing of the PC during the call will occur during the issue of the call.
  • a comparison is performed to determine whether a correct or incorrect value was predicted. If an incorrect value was predicted, a new value is updated and the program flow is backed-up to the location prior to the execution of the incorrect program change.
  • the FPC is updated when the instructions are fetched and when the instructions move to the issue latches.
  • the PC is updated after the FPC and usually during issue or when the instructions are executed.
  • the present invention fetches instructions ahead the location where the instructions will actually be executed in the code sequence. In order to speed up the execution, the present invention fetches from a predicted location instead of waiting for the return. Otherwise, the return instruction would have to be executed before you read the contents of that register which previously was written with the result of the return. In order to read that register, you actually have to execute the instruction normally.
  • the value is known once the register file is read. While staying ahead of the program execution, the issue and the whole register file reprocess, store that same value that's written into the register file and restore that value onto a stock. When a program change is issued, the value is taken and run through the register file and pushed onto a stock that's accessible by the fetch program counter logic.
  • the fetch program logic will see a return instruction and perform the return in particular. Now, when it sees this specific instruction, it realizes that this instruction is going to get us results from the register files sometime X plus delta or a third location in the main code sequence. That same value is stored onto the stack and the return is synchronized. For example, if there are three returns in succession and none have been performed, the first return will always be with respect to the last jump issued. Therefore, the top of the stack always matched to the first jump return performed. In the event of performing a jump return, the stack is popped and the value is taken off the PC and shoved into the FPC at the appropriate moment. This continues along well in advance of the completion of the return instruction itself.
  • the present invention is useable with many processor applications and instruction set descriptions other than what is illustrated herein.
  • the use of the term counter window pointer can include using any pointer with the present invention.
  • the term return prediction table can include stacks as well as single registers.
  • the present invention is useable in any application wherein there is a return from a program flow change or from a controlled transfer including, but not limited to, the retry of a default condition.
  • the present invention contemplates the return to either the original location in the main code sequence or a location predetermined by a hardware or software change.

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Multi Processors (AREA)
  • Devices For Executing Special Programs (AREA)
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EP96103172A 1995-03-03 1996-03-01 Processeur superscalaire comprenant des fenêtres de registres multiples et génération d'adresses de réponse spéculatives Expired - Lifetime EP0730221B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US39828495A 1995-03-03 1995-03-03
US398284 1995-03-03

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EP0730221A2 true EP0730221A2 (fr) 1996-09-04
EP0730221A3 EP0730221A3 (fr) 1997-05-14
EP0730221B1 EP0730221B1 (fr) 2002-10-09

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US (1) US5896528A (fr)
EP (1) EP0730221B1 (fr)
AT (1) ATE225958T1 (fr)
DE (1) DE69624158T2 (fr)

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US9619230B2 (en) 2013-06-28 2017-04-11 International Business Machines Corporation Predictive fetching and decoding for selected instructions
US11150908B2 (en) 2017-08-18 2021-10-19 International Business Machines Corporation Dynamic fusion of derived value creation and prediction of derived values in a subroutine branch sequence
US10884747B2 (en) 2017-08-18 2021-01-05 International Business Machines Corporation Prediction of an affiliated register
US10908911B2 (en) 2017-08-18 2021-02-02 International Business Machines Corporation Predicting and storing a predicted target address in a plurality of selected locations
US10719328B2 (en) 2017-08-18 2020-07-21 International Business Machines Corporation Determining and predicting derived values used in register-indirect branching
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US10705973B2 (en) 2017-09-19 2020-07-07 International Business Machines Corporation Initializing a data structure for use in predicting table of contents pointer values
US10725918B2 (en) 2017-09-19 2020-07-28 International Business Machines Corporation Table of contents cache entry having a pointer for a range of addresses
US10884929B2 (en) 2017-09-19 2021-01-05 International Business Machines Corporation Set table of contents (TOC) register instruction
US10713050B2 (en) 2017-09-19 2020-07-14 International Business Machines Corporation Replacing Table of Contents (TOC)-setting instructions in code with TOC predicting instructions
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EP0730221A3 (fr) 1997-05-14
DE69624158T2 (de) 2003-06-05
ATE225958T1 (de) 2002-10-15
EP0730221B1 (fr) 2002-10-09
DE69624158D1 (de) 2002-11-14
US5896528A (en) 1999-04-20

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