EP0730220A2 - Verfahren und Vorrichtung zur schnellen Ausführung von Verzweigungsbefehlen - Google Patents

Verfahren und Vorrichtung zur schnellen Ausführung von Verzweigungsbefehlen Download PDF

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Publication number
EP0730220A2
EP0730220A2 EP96103171A EP96103171A EP0730220A2 EP 0730220 A2 EP0730220 A2 EP 0730220A2 EP 96103171 A EP96103171 A EP 96103171A EP 96103171 A EP96103171 A EP 96103171A EP 0730220 A2 EP0730220 A2 EP 0730220A2
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EP
European Patent Office
Prior art keywords
bits
inputs
control transfer
state
transfer instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP96103171A
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English (en)
French (fr)
Other versions
EP0730220A3 (de
Inventor
Sunil W. Savkar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
HAL Computer Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HAL Computer Systems Inc filed Critical HAL Computer Systems Inc
Publication of EP0730220A2 publication Critical patent/EP0730220A2/de
Publication of EP0730220A3 publication Critical patent/EP0730220A3/de
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/324—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address using program counter relative addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address

Definitions

  • This invention relates to processor design and more specifically, to the design of a processor implementation which executes relative control transfer instructions.
  • processors execute instructions from a program containing a sequence of instructions.
  • Many conventional processors utilize control transfer instructions, such as branches, to allow the processor to vary the processing order of the instructions from the serial program sequence.
  • Some control transfer instructions may be unconditional, causing a branch in all circumstances.
  • Other control transfer instructions may be conditional, transferring the program flow upon a met condition, such as a result of an operation being equal to zero.
  • the present invention operates with both unconditional as well as conditional control transfer instructions.
  • Control transfer instructions indicate a memory address from which the next logical instruction is to be read and executed. This address is known as the target address or the target. In the case of a conditional control transfer instruction, this next logical instruction at the target address is only processed if a condition indicated by the instruction is met, otherwise the next physical instruction is used as the next logical instruction.
  • the control transfer instruction may indicate the target address in a variety of ways. In some conventional processors, the instruction contains the complete target address. Such control transfer instructions are referred to as "absolute.” Such control transfer instructions execute rapidly because the entire address is available within the instruction, although the instruction length can be large.
  • control transfer instructions indicate the target address using an instruction displacement field relating to the memory address of the control transfer instruction itself.
  • the memory address of the control transfer instruction may be the address of the first word of the instruction, although any memory address related in some fashion to the instruction may be used.
  • the displacement which may be positive or negative, is added to the memory address of the control transfer instruction to produce the target address.
  • Such control transfer instructions are referred to as "relative.” Because many target addresses are near the address of the control transfer instruction, the use of relative control transfer instructions can result in substantial instruction length savings. However, the use of relative control transfer instructions can slow the execution of the instructions because the processor must first add the displacement to the address of the control transfer instruction to produce the target address.
  • Another conventional technique has been to precompute the target address in advance of the execution of the control transfer instruction. While this technique optimizes the speed of execution, it can dramatically increase the size of storage required to store the control transfer instruction and can increase the size of the data paths required to deliver relative control transfer instructions to the unit which will execute the instruction.
  • Another conventional technique has been to predict the target address by storing the most recent set of target addresses from other executed control transfer instructions, under the theory that target addresses from several control transfer instructions are often the same. Such a technique requires additional storage to store previous target addresses, and can incur additional processor time if the predicted target is incorrect.
  • the low order bits of the target address are precomputed by adding the relative displacement to a portion of the address of the control transfer instruction, to produce a set of low order bits of the target address, and two flag bits.
  • the remaining high order bits of the target address will either be equal to the same number of high order bits of the address of the control transfer instruction, or one more or one less.
  • the flag bits indicate whether equality, increment or decrement is applied to the high order bits of the control transfer instruction address to determine the high order bits of the target address, and such high order bits of the target address are then appended to the precomputed low order bits to produce the target. This requires only a fast increment or decrement operation to be used at execution time to compute the target address instead of a full addition or subtraction, while requiring the storage of only one extra bit per control transfer instruction.
  • Figure 1 is a flowchart illustrating a method according to the present invention of computing a compact absolute control transfer instruction.
  • Figure 2 is a flowchart illustrating a method according to the present invention of generating a target address from a compact absolute control transfer instruction.
  • FIG. 3 is a block schematic diagram of a processor instruction transfer apparatus according to the present invention.
  • Figure 4 is a block schematic diagram of an apparatus which computes the low order bits of a target address and two flag bits according to the present invention
  • Figure 5 is a schematic diagram of a decoder used to determine if an instruction is a relative control transfer instruction according to the present invention.
  • Figure 6 is a block schematic diagram of the apparatus of Figure 3 , with additional circuitry capable of passing non-relative control transfer instructions unchanged.
  • One embodiment of the present invention can convert a relative control transfer instruction into a compact absolute control transfer instruction which contains a set of least significant bits of the target address and two flag bits in a space only one bit larger than that required by the displacement of the relative control transfer instruction.
  • the use of the flag bits, the set of least significant bits, and a set of the most significant bits of the relative control transfer instruction address allows for rapid determination of the target address with a minimum of computation time.
  • the D relative displacement bits are sign extended 110 into D+1 bits, and added 112 to the absolute value of the D-1 least significant bits of the relative control transfer instruction address to produce a D+2 bit result, bits D+1 down to bit 0.
  • the D-1 least significant bits of the relative control transfer instruction are always treated as a positive number.
  • Some of the D+2 result bits may be stored 114 in place of the original displacement bits, or in another location, and some of the remaining bits may also be stored. As described below, bit D+1, the most significant bit, need not be stored. Thus, storage of the D+1 remaining bits requires only one additional bit storage position beyond the original D bit displacement.
  • the address of the relative control transfer instruction is the address of the first word of the control transfer instruction, although any address related to the control transfer instruction will allow operation of the present invention.
  • the second most significant bit of the result bits, bit D is referred to as the operation flag, which will indicate the type of operation described below which may be required to adjust the set of most significant control transfer instruction address bits.
  • the third most significant bit in the result, bit D-1 is referred to as the enable operation flag, which will indicate as described below whether any operation on the set of most significant control transfer address bits is required.
  • the D-1 least significant bits in the result are used as the least significant bits in the target address as described below.
  • the remaining W-D+1 most significant bits in the target address are determined by first reading 210 and testing 212 the enable operation flag bit. Where the enable operation flag bit has a value equal to zero, the D-1 least significant result bits are appended 214 to the W-D+1 most significant bits in the address of the relative transfer control instruction, each bit in the same order of significance as it appeared in the relative control transfer address or result.
  • the operation flag is read 215 and tested 216 to determine the W-D+1 most significant bits in the address of the target.
  • the operation flag need not be read 215 after the enable operation flag is tested 212 , but may be read 215 earlier in the method of the present invention.
  • the W-D+1 most significant bits in the relative transfer control instruction address are first incremented 222 by one to produce the W-D+1 most significant bits in the target address prior to appending 224 them to the D-1 least significant result bits as in step 214 .
  • the W-D+1 most significant bits in the relative transfer control instruction address are first decremented 218 by one prior to appending 220 them as in step 214 to produce the W-D+1 most significant bits in the target address.
  • the most significant control transfer instruction address bits are not actually incremented or decremented, but a copy of them is incremented 222 or decremented 218 .
  • Compact absolute control transfer instruction generator 342 accepts as input 322 relative control transfer instruction address stored in storage module 310 , and as input 320 the displacement stored in storage module 314 from the instruction stored in storage module 308 which also contains the relative transfer instruction opcode stored in storage module 312 .
  • the address, opcode and displacement are not stored in storage modules 310, 312, 314 , but are merely provided at inputs 322, 318 and 320 .
  • displacement input 410 is sign extended at least one bit by sign extender 411 .
  • Figure 4 shows a four-bit displacement, although any size greater than one may be used.
  • all inputs 410 are connected to their corresponding outputs 413 , and the most significant output 418 is coupled to the most significant input 415 .
  • a buffer may be coupled to the most significant input 415 if the fanout due to the addition of the most significant output 418 would be too great.
  • the outputs 413, 418 of the sign extender 411 are coupled to one of the sets of inputs 417 of a D+1 bit adder 420 , and the other set of adder inputs 419 are coupled to receive the D-1 least significant bits of the control transfer instruction address 412 . If the number of inputs in the first set 417 must be equal to the number of inputs in the second set 419 , then the most significant two bits 414 in the second set may be coupled to ground 416 in order to always treat input 419 as a positive number.
  • the second most significant adder output 332 may be stored in storage module 348 as the operation flag
  • third most significant bit 334 may be stored in storage module 350 as the operation enable flag
  • the remaining D-1 least significant bits 336 of the output of the adder 420 may be stored as the least significant target address bits in storage module 354 .
  • the control transfer instruction opcode bits from storage module 312 may be stored into storage module 346 to generate a compact relative absolute instruction stored in storage module 306 having a a number of bits only one greater than the number of bits in the relative control transfer instruction stored in storage module 308 when the most significant bit 428 of the output of adder 420 is unconnected to the storage module 306 .
  • a different opcode is stored at module 346 .
  • no opcode is stored, and module 346 is not used, as the outputs 332, 334, 336, 318 are coupled directly to the next stage described below. Module 346 is not required for the present invention to operate.
  • Incrementer / decrementer 344 is coupled to receive the most significant W-D+1 bits of the address of the relative control transfer instruction at input 330 , and the operation flag bit and enable operation flag bit at inputs 366 and 352 respectively. Incrementer / decrementer 344 passes the W-D+1 address bits from input 330 unchanged to output 360 if enable operation flag bit at the input 352 is zero.
  • Incrementer / decrementer 344 increments the W-D+1 address bits from input 330 and passes the incremented result to output 360 if enable operation flag bit at the input 352 is equal to one and operation flag bit at the input 366 is equal to zero. Incrementer / decrementer 344 decrements the W-D+1 address bits from input 330 and passes the decremented result to output 360 if enable operation flag bit at the input 352 is equal to one and operation flag bit at the input 366 is equal to one.
  • the output 360 from incrementer / decrementer 344 may be stored as the high order bits in storage module 362 and low order bits stored in storage module 354 and available on line 358 may be stored in storage module 364 to complete the generation of the target address in storage module 370 .
  • the target address is not separately stored, but available at outputs 360 , 358 .
  • the operation of the apparati 304 or 368 may be enabled only for instructions stored in module 308 which are relative control transfer instructions by using a decoder to decode the opcode bits stored in storage module 312 or 346 as described below.
  • the present invention will operate with any processor instruction set which contains relative control transfer instructions.
  • the present invention operates with the SPARC instruction set.
  • a decoder 510 is shown which decodes SPARC relative control transfer instruction opcodes as described in SPARC International, SPARC Architecture Manual , pp74-77 and 136-139 (9th ed. Prentice Hall, 1994), D.L. Weaver and T. Germond, editors.
  • Inputs 531, 530, 524, 523 and 522 correspond to instruction bits 31, 30, 24, 23 and 22 respectively in the opcode of the instruction.
  • Output 540 is asserted high if a relative control transfer instruction, bpr, bpcc, bcc or call, is contained in the opcode presented at the inputs 531, 530, 524, 523 and 522 .
  • FIG. 6 the apparatus of Figure 3 is shown with the decoder 510 of Figure 5 and multiplexors 610 to select which bits are placed into storage module 370 .
  • decoder 510 asserts output 540 instructing multiplexors 610 to pass inputs from buses 360, 358 to storage module 370 as described above in Figure 3 .
  • decoder 510 does not assert output 540 instructing multiplexors 610 to pass the full instruction on buses 318, 612 unchanged to storage module 370 .

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
EP96103171A 1995-03-03 1996-03-01 Verfahren und Vorrichtung zur schnellen Ausführung von Verzweigungsbefehlen Ceased EP0730220A3 (de)

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US398151 1982-07-14
US39815195A 1995-03-03 1995-03-03

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EP0730220A3 EP0730220A3 (de) 1997-01-08

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Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6446224B1 (en) 1995-03-03 2002-09-03 Fujitsu Limited Method and apparatus for prioritizing and handling errors in a computer system
DE69836056T2 (de) * 1997-08-29 2007-04-12 Matsushita Electric Industrial Co., Ltd., Kadoma Prozessor mit verringerter Zahl von bedingten Befehlen
US6167506A (en) 1997-11-17 2000-12-26 Advanced Micro Devices, Inc. Replacing displacement in control transfer instruction with encoding indicative of target address, including offset and target cache line location
US7904789B1 (en) * 2006-03-31 2011-03-08 Guillermo Rozas Techniques for detecting and correcting errors in a memory device
US20090182992A1 (en) * 2008-01-11 2009-07-16 International Business Machines Corporation Load Relative and Store Relative Facility and Instructions Therefore
US7734900B2 (en) * 2008-01-11 2010-06-08 International Business Machines Corporation Computer configuration virtual topology discovery and instruction therefore
US7739434B2 (en) 2008-01-11 2010-06-15 International Business Machines Corporation Performing a configuration virtual topology change and instruction therefore
US20090182984A1 (en) * 2008-01-11 2009-07-16 International Business Machines Corporation Execute Relative Long Facility and Instructions Therefore
US9280480B2 (en) 2008-01-11 2016-03-08 International Business Machines Corporation Extract target cache attribute facility and instruction therefor
US7895419B2 (en) 2008-01-11 2011-02-22 International Business Machines Corporation Rotate then operate on selected bits facility and instructions therefore
US20090182988A1 (en) * 2008-01-11 2009-07-16 International Business Machines Corporation Compare Relative Long Facility and Instructions Therefore
US7870339B2 (en) * 2008-01-11 2011-01-11 International Business Machines Corporation Extract cache attribute facility and instruction therefore
US20090182985A1 (en) * 2008-01-11 2009-07-16 International Business Machines Corporation Move Facility and Instructions Therefore

Citations (4)

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US4203157A (en) * 1978-09-05 1980-05-13 Motorola, Inc. Carry anticipator circuit and method
EP0265948A2 (de) * 1986-10-29 1988-05-04 Nec Corporation Datenprozessor mit der Fähigkeit, die Verzweigungsadresse sofort zu berechnen in einer Relativadressenverzweigung
EP0286260A2 (de) * 1987-03-27 1988-10-12 Tandem Computers Incorporated Gruppenbezogenes Adressierungssystem
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JP2761688B2 (ja) * 1992-02-07 1998-06-04 三菱電機株式会社 データ処理装置
KR950004225B1 (ko) * 1993-04-16 1995-04-27 현대전자산업주식회사 고속 캐리 증가 가산기
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Publication number Priority date Publication date Assignee Title
US4203157A (en) * 1978-09-05 1980-05-13 Motorola, Inc. Carry anticipator circuit and method
EP0265948A2 (de) * 1986-10-29 1988-05-04 Nec Corporation Datenprozessor mit der Fähigkeit, die Verzweigungsadresse sofort zu berechnen in einer Relativadressenverzweigung
EP0286260A2 (de) * 1987-03-27 1988-10-12 Tandem Computers Incorporated Gruppenbezogenes Adressierungssystem
US5276825A (en) * 1991-03-12 1994-01-04 Chips & Technologies, Inc. Apparatus for quickly determining actual jump addresses by assuming each instruction of a plurality of fetched instructions is a jump instruction

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EP0730220A3 (de) 1997-01-08
US5860152A (en) 1999-01-12

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