EP0715261A1 - Organisation d'un arbitre pour des transferts sériaux de bus - Google Patents

Organisation d'un arbitre pour des transferts sériaux de bus Download PDF

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Publication number
EP0715261A1
EP0715261A1 EP95308326A EP95308326A EP0715261A1 EP 0715261 A1 EP0715261 A1 EP 0715261A1 EP 95308326 A EP95308326 A EP 95308326A EP 95308326 A EP95308326 A EP 95308326A EP 0715261 A1 EP0715261 A1 EP 0715261A1
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European Patent Office
Prior art keywords
free time
data transfer
periodic
transfers
time
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EP95308326A
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German (de)
English (en)
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David R. Wooten
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Compaq Computer Corp
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Compaq Computer Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control

Definitions

  • the invention relates to serial bus transfers capable of handling several types of serial bus devices, and more particularly to an arbiter for managing operation and timing of device operations on the serial bus.
  • serial bus organization to connect all of these various lower bandwidth devices.
  • the serial bus is organized with a host controller having a series of ports, which can then be connected either directly to devices or functions or to further hubs which have below them further devices or functions.
  • a hub or the host controller may in addition incorporate functions if desired. In this manner a tree structure can be developed to allow a reasonable number of functions or devices to be attached to the serial bus system.
  • the host controller connects to a bus in the computer system, for example the PCI bus, through the host controller. By having the host controller act as a concentrator, only a single connection to the PCI bus is necessary. The connection is better able to utilize the performance of that PCI bus without requiring numerous connections.
  • the host controller, each hub, and each function or port contain particular control registers for doing set up and initialization operations.
  • three basic types of data transfer are defined in the serial bus system.
  • the first type is isochronous, which is effectively a continuous real time transfer, such as telephony information or audio information.
  • the second type is asynchronous block transfers, such as printer operations and conventional serial port operations, while the third type is asynchronous interactive device transfers, such as keyboard, mouse, pointing device, pen interfaces, and the configuration and status information, generally referred to as the control information, of the various devices.
  • the packet types include data packets, token packets for use from host to device, a handshake packet and a special control packet.
  • Data packets are the isochronous, asynchronous block, and asynchronous control types.
  • Token packets allow transfer of data packets.
  • Handshake packets are used to perform a ready handshake after transfer of a data or control packet to acknowledge successful receipt or indicate unsuccessful receipt.
  • Special control packets are used for logical reset and status request transfers. Each function or device has a logical address.
  • An isochronous device needs a virtual channel having a given minimum bandwidth, so isochronous transfers must be requested or scheduled to have this minimum bandwidth.
  • the bandwidth can be obtained by long block sizes and infrequent transfers, smaller block sizes and more frequent transfers, or a combination.
  • An asynchronous block device need not have a guaranteed bandwidth, as they conventionally can have some flexibility in data transfer rates, but preferably the transfers must be robust so that when errors are detected, the transfer can be retried.
  • Asynchronous devices come in essentially two types, high and low bandwidth.
  • Higher bandwidth devices include printers and modems, while lower bandwidth devices are keyboards, mice and the like.
  • the control functions are relatively low bandwidth.
  • the control functions have essentially a one-time nature, being used mostly during system initialization and to prepare a device for a block transfer.
  • the isochronous and asynchronous block devices have a tendency to be very regular and thus operate differently from the control and interactive devices.
  • Each device and port on a hub or the host controller includes the capabilities to handle the low level bus transfer protocol between the particular node of the appropriate hub and the device itself.
  • a relatively simple transfer protocol with a limited number of packet types is defined.
  • the serial bus has a bandwidth of 5 to 20 Mb/sec, which must be split between the various devices. It is important that an isochronous device receive its guaranteed portion of that bandwidth, but it is also important that asynchronous block transfers and control transfers are not starved or overly delayed, if at all possible. Therefore, an arbiter or scheduler must be developed to properly coordinate the various transfers occurring in the serial bus system.
  • the arbiter maximize utilization of the serial bus system at all times to allow the best performance of the devices in the serial bus system. It is further desired that significant portions of the arbiter be handled in hardware because of the greater speeds conventionally obtainable by hardware, in deference to the customarily slower operation of software based functions.
  • a serial bus host controller utilizes an arbiter which organizes data transfer events into three categories, periodic data transfers, which are usually isochronous transfers; aperiodic transfers, which usually are asynchronous transfers and never are isochronous transfers; and control transfers.
  • the arbiter fundamentally operates on a periodic basis. At the beginning of each period, the arbiter preferably alternates between periodic transfers and control transfers. When all of the periodic transfers have been completed, the arbiter then provides access to the various asynchronous transfers which are scheduled to occur, alternating with any remaining control transfers.
  • the arbiter gives preference to the periodic events, and if any time within the period is available, which is referred to as the free time, control events are interleaved with periodic events until no free time remains or all are completed. Any remaining time in the period is used cycling through the aperiodic transfers.
  • the arbiter of the preferred embodiment keeps a running total of free time during each period to determine if additional control or aperiodic transfers can occur.
  • the computer system C includes a processor 100 such as a Pentium® or 486 processor by Intel or their equivalents. It is understood that other processors could of course be utilized.
  • the processor 100 is connected to a second level or L2 cache 102 and to a memory and L2 cache controller and PCI bridge 104 and address and data buffer 106.
  • the main memory 108 of the computer system C is connected between the memory and L2 cache controller 104 and the address and data buffer 106. It is understood that the processor 100, cache 102, memory and cache controller 104, address and data buffer 106 and main memory 108 form the processor system and processor to PCI bus bridge according to a PCI system. It is understood of course that alternate processor systems and high speed bus architectures could be utilized if desired. Further, the address buffering could be included in the PCI bridge 104.
  • the PCI bridge 104 and address and data buffer 106 are connected to a PCI bus 110 which performs the high speed high performance back bone of the computer system C.
  • a PCI to ISA (Industry Standard Architecture) bridge 110 is connected between the PCI bridge 110 and an ISA bus 114.
  • a floppy disk controller 116 is connected to the ISA bus 114, as is the system ROM (read only memory) 118. Additionally, there may be a plurality of ISA slots connected to the ISA bus 114 for receiving interchangeable cards.
  • PCI bus 110 The majority of the devices are connected to the PCI bus 110.
  • a SCSI or IDE (Intelligent Drive Electronics) controller 122 is connected to the PCI bus 110 and to the associated disk drives and other devices (not shown).
  • a network interface card (NIC) 124 is also connected to the PCI bus 110 to allow high performance network connections.
  • NIC network interface card
  • video graphics system 126 is connected to the PCI bus 110 and to an associated monitor 128.
  • a fax/modem DSP (digital signal processor) 138 can also be connected to the PCI bus 110 for fax and modem data processing.
  • this is an exemplary computer system architecture and is provided for explanation, variations being readily apparent to one skilled in the art.
  • a serial bus host controller 130 is also connected to the PCI bus 110.
  • the serial bus host controller 130 of the illustrated embodiment acts as both a host controller and a hub, with various hubs and functions connected to the host bus controller 130.
  • a printer 132 is connected to one port of the serial bus host controller 130, while an expansion hub 134 providing for further expansion capabilities is connected to a second port.
  • a telephony interface 136 containing the necessary CODEC and DAA components is connected to a third port and also receives a telephone line.
  • the telephone line can be any of the available types such as an analog line, an ISDN line, a PBX connection and so on.
  • the monitor 128 further acts as a hub and as a node.
  • the monitor 128 is thus connected to one port of the serial bus host controller 130.
  • the node or device function of the monitor 128 allows configuration of the monitor 128 independent from the high speed data utilized in the video system 126.
  • the monitor 128 preferably acts as a hub because of the conventional physical arrangement of a modern computer system.
  • the system unit which contains the other devices is located under the desk or in a relatively remote location, with only the monitor 128, a keyboard 140, a pointing device such as a mouse 142 or pen 144, a telephone handset 146, and microphone and speakers relatively accessible to the user.
  • the monitor 128 effectively forms the central core of this unit, it is logically a proper location for a hub.
  • the telephone handset 146 could be connected to one port of the monitor hub to receive digitised analog information either directly from the telephony interface 136 or as otherwise available, such as from an answering machine or voice mail function.
  • the microphone is part of audio input circuitry 148 which is connected to a second port of the monitor hub, while audio output circuitry 150 contains the speakers used for audio output.
  • the keyboard 140 further acts as a hub itself and a node, in that it is connected to the monitor hub but further contains ports to connect to the mouse 142 and a pen or stylus pointing device interface 144. This further physical connection is appropriate as those are the primary input devices and they are in most cases generally relatively near the keyboard 140 to ease use or operation.
  • the relatively lower data rate operations are connected to the serial bus host controller 130 according to the serial bus system.
  • the printer 132 is set up and used with higher bandwidth asynchronous block transfers, while the telephony interface 136, the phone handset 146 and, in most cases, the audio input circuitry 148 and the audio output circuitry 150 are isochronous devices.
  • the keyboard 140, mouse 142 and pen interface 144 can be treated as low bandwidth asynchronous block devices.
  • each one of the particular devices connected over the serial bus system includes control ports and configuration registers which need to be accessed by the processor 100 via the serial bus host controller 130 to allow control and setup of the individual devices.
  • serial bus services 206 return data to both the device driver software 204 and the configuring software 202, and on occasion directly to the operating system 200.
  • Serial bus services 206 provide four basic functions.
  • the first is client services 208, which is utilized when the device driver software 204 and the configuring software 202 register with the serial bus services 206 and which provides event notifications back to the device driver software 204 and the configuring software 202.
  • Serial bus services 206 also includes configuration management software 210, which tracks and keeps track of the organization of the various functions or devices in the serial bus system and also maintains the configuration state of each device.
  • a bus management module 212 provides high level management of the operations of the serial bus system, such as bandwidth and power management for the devices, both isochronous and asynchronous, as required. Further, the bus management module 212 performs diagnostics.
  • the fourth module is the data transfer module 214, which handles the actual data transfer between the configuring software 202 and the device software 204 and the host controller system 216.
  • the host controller system 216 is actually comprised of two portions, host controller services software 218 and the serial bus host controller 130.
  • the host controller services software 218 includes three modules, the first of which is schedule management 220, which is responsible for actually organizing the polling of the particular transfers or channels to allow efficient or smooth operation. Effectively, the schedule management module 220 can be considered, in large part, the arbiter of the serial bus system.
  • Queue management module 222 controls access to the various data queues.
  • Controller management module 224 deals with the actual operation and configuration of the serial bus host controller 130 and provides certain functions and status information back to the serial bus services 206.
  • the host controller services 218 thus interact directly with the serial bus host controller 130.
  • the serial bus host controller 130 interacts with the various functions or devices according to the lower level serial bus protocol.
  • FIG. 3 a block diagram illustrating the logical operation and organization of the host controller system 216 is illustrated.
  • a PCI bus 110 and software interface 300 is physically connected to the PCI bus 110 and logically connected to the serial bus services 206.
  • Queue management module 222 of the host controller services 216 effectively handles four queues, the first and second queues being the block data transmit queue 302 and the block data receive queue 304. These are effectively the isochronous and asynchronous block transfer data queues.
  • the transmit queues 302 and 306 are connected to transmit logic 310, while the receive queues 304 and 308 are connected to receive logic 312.
  • the transmit and receive logic 310 and 312 are connected to hub functions 314, which in turn are connected to the actual ports of the host controller 130.
  • a polling scheduler 316 which is effectively the function of the schedule management module 220, is connected to the various queues 302, 304, 306, and 308 and to the transmit and receive logic 310 and 312 so that packets are properly shuttled according to the operation of the polling scheduler 316.
  • a controller status block 318 was connected to the hub functions 314 and to the interface 300 to act as the controller management module 224.
  • the arbiter inside the polling scheduler 316 can be organized a number of different ways. In all of these organizations, the polling scheduler 316 includes a periodic timer or tick counter to reset or reorganize and provide predetermined period time slices, so that isochronous transfers can be scheduled in a regular order.
  • the periodic timer is preferably programmable and its operations is well known to those skilled in the art.
  • the arbitration of the various events scheduled to occur are kept in a single queue 320 as shown in Figure 4.
  • the various events as indicated are effectively the data transfer operations which are scheduled to occur. For example, an isochronous virtual channel is connected between the telephony interface 136 and the telephone handset 146 to allow a telephone call to be received. Then a series of isochronous data transfer packet requests would be placed into the queue 320 so that sufficient bandwidth is present, given the packet sizes and data transfer rates on the serial bus, to allow the telephone conversation to occur without interruption.
  • the isochronous transfer requests are placed at the head of the queue 320 so that when the arbiter begins traversing the queue at the start of each periodic interval, the isochronous transfers are completed first.
  • One portion of the configuration management software 210 was to allocate overall bandwidths of the serial bus system given the various transfers of isochronous and asynchronous nature to guarantee that the isochronous transfers occur as desired. To this end, the configuration management software 210 performs calculations so that only sufficient isochronous transfers are present and the bandwidth is not completely utilized by those transfers.
  • asynchronous transfers are placed in the queue 320 following the isochronous transfers. For instance, this could include printer transfers. These are placed after the isochronous requests because by definition they are asynchronous and therefore more flexible. Thus they will be performed only after the isochronous transfers occur.
  • the control transfers as assigned locations in the queue 320. Preferably, the control transfers are placed within the queue 320 so that they will execute within a reasonable period of time and not be starved.
  • the schedule management module 220 of the host controller services 218 becomes quite difficult, especially as the number of isochronous transfers increases because after traversing the isochronous and asynchronous transfers there may be minimal time left for the control transfers, so that the schedule management module 220 must frequently be rearranging events in the queue 320 to assure that asynchronous and control transfers occur at least periodically at some minimum cycle rate. This is a relatively complex task and therefore for this reason it is undesirable to use the single queue arrangement. While the single queue 320 does simplify the hardware operations of the serial bus host controller 130 as only a single queue must be traversed, great emphasis is then placed in the schedule management software 220 to provide most of the actual scheduling and starvation control. As this increases software complexity and software conventionally runs slower than hardware, overall performance of the serial bus system is not maximized.
  • Figures 5A and 5B show a more preferable organization of the queues used by the arbiter in the scheduler 316.
  • an isochronous queue 340 and an asynchronous queue 342 are utilized.
  • isochronous queue 340 contains only isochronous transfers and is preferably traversed once during each periodic interval, with this queue 340 being traversed first.
  • the queue 342 contains asynchronous events such as the block transfers and the control transfers.
  • the queue 342 is preferably treated in a circular manner with the control transfers being removed after execution. The control transfers are detected by identifying them as such using the packet header information.
  • FIG. 5B shows an alternative queue arrangement having a block transfer queue 346 and a control transfer queue 348.
  • Block transfer queue 346 contains both the isochronous transfers and the asynchronous block transfers, preferably in the order of isochronous followed by asynchronous.
  • Queue 346 preferably is traversed once each periodic interval, while the control queue 348 is traversed as time and events are available. Each control event is then removed after execution.
  • This organization further simplifies the operation of the schedule management software 220 in that regular events simply are placed in the block queue 346, while the random or pseudo-random control requests are simply placed in a separate queue 348.
  • This organization has the drawback that the control events follow the block events and so may starve if the various block events take the entire period and more. Therefore, the schedule management software 220 still must be aware of this possibility to appropriately handle the queues 346 and 348. Further, the schedule management software 220 may still need to rearrange the asynchronous transfers to prevent starvation.
  • FIG. 6 the queue structure according to the preferred embodiment is illustrated.
  • a periodic transfer queue 360 there are three queues utilized by the arbiter, a periodic transfer queue 360, an aperiodic transfer queue 362 and a control transfer queue 364. All isochronous requests are placed in the periodic queue 360, while all asynchronous block transfers are generally placed in the aperiodic queue 362, though asynchronous block transfers can be placed in the periodic queue 360 if guaranteed bandwidth is desired.
  • the various control events are placed in the control queue 364. Operation of the arbiter is further illustrated in the flowcharts of Figures 7A and 7B.
  • a cycle of operation for a given period commences at step 400 upon receipt of the periodic timer pulse or event.
  • the arbiter moves the pointer of the periodic queue 360 to the top and then control proceeds to step 402 to determine if the free time available in the period is greater than zero.
  • the configuration management software 210 and the schedule management software 220 will determine the calculated total amount of time utilized by the transfers in the periodic queue 360, usually just isochronous transfers, and the difference between this total calculated time and the total time defined by the periodic timer is the free time.
  • the free time is always greater than zero to guarantee that the aperiodic events and the control events actually do occur and are not fully starved. That guarantee of free time is a higher level function of the configuration management software 210 which coordinates bandwidth requests with the various device drivers 204 denying a request if the free time goes below zero and a reallocation cannot be performed.
  • control proceeds to step 404 to determine if there are any items in the control queue 364. If so, control proceeds to step 406 to determine if a read is pending from a prior read request provided in the control queue 364. To partially simplify operation of the serial bus host controller 130, preferably no further control operations proceed once a control operation has issued a read request to a device and the response has not been received. In an alternative embodiment, the read delay could occur on a device by device basis, but this would increase the complexity of the host controller 130 and is not the preferred embodiment. It is desirable to simply wait for the read return to avoid complexities in the host controller 130. If a read is pending, control proceeds to step 408 to determine if the read operation has timed out.
  • control proceeds to step 410 where a read token packet is passed to the particular device which has the read pending to determine if the device is now ready to respond. Control proceeds from the repeat read token step 410 to step 412.
  • step 413 determines if the remaining free time is sufficient to perform the next control item. If not, control proceeds to step 420. If so, control proceeds to step 414 where the next control item is executed and removed from the queue 364. Of course, if this was a read operation a read pending flag would be sent. Control proceeds from step 414 to step 412. In step 412, a determination is made whether the particular transfer requested by the control event has been completed. If so, control proceeds to step 416. If not, control proceeds to step 418 to determine if the particular response or acknowledgement from the function or device has timed out. If not, control returns to step 412 to wait for completion or time out. If the operation has completed or timed out, control proceeds from steps 412 and 418 to step 416. In step 416, the time actually required to do the transfer is subtracted from the free time value to determine the amount of free time remaining in this period.
  • the queue entries are only entry points or indices into related tables.
  • the table entries include control block information on each packet, such as address or addresses; packet type; packet size, both transmit and receive; location of the packet in main memory 108, which the host controller 130 can access using bus mastering capabilities; timeout period for the particular transfer; calculated time for the transfer, which generally should be at least the timeout period; and other related information.
  • the table memory can be located in the host controller 130 for speed and to minimize PCI bus 110 traffic; can be located in a separate local memory or can be in the main memory 108. This calculated time can then be compared with the actual time required for the transfer to appropriately adjust the free time.
  • the transfer was completed in less than the calculated time, the difference can be added to the free time, whereas if the transfer took longer than desired, then the free time is reduced. It is understood that the actual time should usually be less than the calculated or requested time, but under certain conditions it may be possible for the actual time to exceed the requested time. Control then returns to step 402 to proceed in this loop.
  • step 429 determines if there is sufficient free time to perform the next aperiodic item. If not, control returns to step 402. If so, control proceeds to step 430 where the next aperiodic item in the aperiodic queue 362 is performed.
  • the aperiodic queue 362 is treated as a circular queue and just traversed without removal of any items.
  • the periodic queue 360 is traversed once, top to bottom, while the control queue 364 is treated as a FIFO.
  • the schedule management and configuration management software 220 and 210 are responsible for entering events in the aperiodic queue 362. The aperiodic transfer is executed and control proceeds to step 432 to see if it has been completed.
  • control proceeds to step 434 to determine if it has timed out. If not, control returns to step 432. If it has timed out in step 434 or has completed in step 432, control proceeds to step 436 where the amount of time required to do the aperiodic transfer is subtracted from the remaining free time to determine the total free time in this period. Control then returns to step 402.
  • the aperiodic queue 362 contains all asynchronous items, both high and low bandwidth, the primary differences between high bandwidth devices and low bandwidth devices being the size of the data and to some extent the polling rate. Given this preferred embodiment, they are readily placed in the aperiodic queue 362, reserving the control queue 364 for only single event type transfers, not periodic polling operations.
  • the aperiodic events are executed quite frequently. This generally will cause no problem in the device as the port handshaking will primarily be a dedicated hardware function. Further, this alleviates the problem of reordering the queue 362 when free time is small to avoid starvation. Further, the potential rapid polling is considered preferable to either dead bus time or defining a second period during which the asynchronous events must occur. However, the asynchronous items can be placed in the periodic queue 360 along with the isochronous items if this potential rapid polling is not desired.
  • control transfers which are frequently very short, are given very high priority but will occur only if the periodic transfers provide any free time. After all of the periodic transfers have occurred, then aperiodic transfers will occur in a circular fashion, interleaved with any remaining control items.
  • the use of the three queues 360, 362, and 364 in the arbitration flow as seen in Figures 7A and 7B provides the greatest simplicity to the schedule management module 220.
  • the schedule management software 220 need only place the transfer request into the particular queue, with the arbiter then handling events from there.
  • the software 220 is not required to periodically rearrange the queues as in the previous examples of Figures 4, 5A and 5B. This greatly simplifies the operation and because significant portions are being done with relatively simplistic hardware, an increase in performance of the overall operation of the serial bus system is developed.
  • the host controller 130 contains a register 500 into which the schedule management software 220 stores the calculated total free time.
  • This register 500 contains the value of the free time, that is, the result of total calculated isochronous and asynchronous transfer time for all events in the periodic queue 360 subtracted from the periodic time.
  • This register 500 is connected to the one input of a multiplexor 502, which has its select input connected to the periodic timer pulse.
  • the output of the multiplexor 502 is connected to the parallel load input of a free time register 504, which register 504 keeps track of the actual free time remaining.
  • the free time register 504 is loaded by either a periodic timer event or the completion or time out of a particular transfer, be it isochronous, asynchronous, or control.
  • the data outputs of the free time register 504 are provided to the positive input of an adder 506.
  • a negative or subtracting input to the adder 506 is provided by the output of an adder 508.
  • the positive or plus input of the adder 508 receives the actual time for a particular transfer. This is preferably kept by a simple timer that is initiated when the transfer is started and stopped when the transfer is completed.
  • a negative or subtraction input of the adder 508 is provided by the output of a two input multiplexor 510. The selection of the multiplexor 510 is based on the presence of a periodic event.
  • the zero input, which is connected to a zero value, of the multiplexor 510 is selected so that in this case the free time register value simply has subtracted from it the actual time required for the aperiodic or control event.
  • the calculated time for that particular event is provided to the one input of the multiplexor 510, so that in this case the free time value plus the calculated time value less the actual time value is provided at the output of the adder 506.
  • the output of the adder 506 is connected to the zero input of the multiplexor 502, so that the free time register is then properly changed to maintain a free time value for utilization by the arbiter.
  • the free time register 504 also contains a greater than zero output which is utilized by the arbiter in the decision step 402.
  • the calculated total free time register 500 can be replaced by a register 520 which receives the total calculated periodic event transfer time from the schedule management software 220 and the periodic timer reload register 522, which would in any case be present in the serial bus host controller 130 to maintain the periodic timer.
  • the periodic timer time in the register 522 is provided to the positive or plus input of an adder 524 and the total calculated periodic event time is provided to the negative or subtracting input of the adder 524.
  • the output of the adder 524 is then connected to the one input of the multiplexor 504 so that in this manner the software 220 does not have to calculate the total free time but rather it can simply provide the total calculated periodic event transfer time.
EP95308326A 1994-11-29 1995-11-21 Organisation d'un arbitre pour des transferts sériaux de bus Withdrawn EP0715261A1 (fr)

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US08/346,097 US5621898A (en) 1994-11-29 1994-11-29 Arbiter organization for serial bus transfers
US346097 1999-07-01

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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998012646A1 (fr) * 1996-09-23 1998-03-26 Silicon Graphics, Inc. Procede d'attribution garantie de largeur de bande dans un systeme informatique pour transferts de donnees entree/sortie
WO2001044955A2 (fr) * 1999-12-16 2001-06-21 Intel Corporation Appareil destine a l'arbitrage de ressource de memoire en fonction de l'attribution de l'intervalle de temps dediee
EP1178632A2 (fr) * 2000-08-04 2002-02-06 Siemens Aktiengesellschaft Procédé de transmission cyclique par bus
US6412049B1 (en) 1999-12-16 2002-06-25 Intel Corporation Method for minimizing CPU memory latency while transferring streaming data
US6415367B1 (en) 1999-12-16 2002-07-02 Intel Corporation Apparatus for reducing asynchronous service latency in a time slot-based memory arbitration scheme
WO2003048950A1 (fr) * 2001-12-03 2003-06-12 Koninklijke Philips Electronics N.V. Systeme de bus de communication
US6757765B1 (en) 1997-03-21 2004-06-29 Hitachi, Ltd. Electronic device, method for using electronic device, and electronic device system for reserving bus usage time on a bus to conduct communications between electronic devices
WO2006035344A1 (fr) 2004-09-28 2006-04-06 Koninklijke Philips Electronics N.V. Systeme et procede de traitement de donnees pour arbitrage memoire
WO2006117746A1 (fr) * 2005-05-04 2006-11-09 Nxp B.V. Controleur de memoire et procede pour controler l'acces a une memoire, ainsi que systeme comprenant un controleur de memoire
WO2008035352A2 (fr) * 2006-09-18 2008-03-27 Sandisk Il Ltd. Procédé et dispositif de stockage permettant d'évaluer une durée pour une opération de stockage
EP1178395A3 (fr) * 2000-07-31 2009-05-20 Texas Instruments Incorporated Appareil et méthode de communication d'un message numérique multimot avec un processeur de signal isochrone

Families Citing this family (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5832492A (en) * 1995-09-05 1998-11-03 Compaq Computer Corporation Method of scheduling interrupts to the linked lists of transfer descriptors scheduled at intervals on a serial bus
US5948094A (en) * 1995-09-29 1999-09-07 Intel Corporation Method and apparatus for executing multiple transactions within a single arbitration cycle
US5671365A (en) * 1995-10-20 1997-09-23 Symbios Logic Inc. I/O system for reducing main processor overhead in initiating I/O requests and servicing I/O completion events
SG74010A1 (en) 1996-06-14 2000-07-18 Compaq Computer Corp Serial bus hub
US5799196A (en) * 1996-07-02 1998-08-25 Gateway 2000, Inc. Method and apparatus of providing power management using a self-powered universal serial bus (USB) device
JPH10154373A (ja) * 1996-09-27 1998-06-09 Sony Corp データデコードシステムおよびデータデコード方法、伝送装置および方法、並びに、受信装置および方法
US6119190A (en) * 1996-11-06 2000-09-12 Intel Corporation Method to reduce system bus load due to USB bandwidth reclamation
US5890015A (en) * 1996-12-20 1999-03-30 Intel Corporation Method and apparatus for implementing a wireless universal serial bus host controller by interfacing a universal serial bus hub as a universal serial bus device
DE69837356T2 (de) * 1997-02-14 2007-11-29 Canon K.K. Vorrichtung, System und Verfahren zur Datenübertragung und Vorrichtung zur Bildverarbeitung
US6012117A (en) * 1997-03-14 2000-01-04 Intel Corporation Methods and apparatus for arbitrating and controlling arbitration for access to a serial bus
US6199127B1 (en) * 1997-12-24 2001-03-06 Intel Corporation Method and apparatus for throttling high priority memory accesses
US6085265A (en) * 1998-01-09 2000-07-04 Toshiba America Information Systems, Inc. System for handling an asynchronous interrupt a universal serial bus device
US6138200A (en) * 1998-06-09 2000-10-24 International Business Machines Corporation System for allocating bus bandwidth by assigning priority for each bus duration time slot to application using bus frame and bus duration
US6151651A (en) * 1998-06-17 2000-11-21 Advanced Micro Devices, Inc. Communication link with isochronous and asynchronous priority modes coupling bridge circuits in a computer system
US6148357A (en) * 1998-06-17 2000-11-14 Advanced Micro Devices, Inc. Integrated CPU and memory controller utilizing a communication link having isochronous and asynchronous priority modes
US6199132B1 (en) 1998-06-17 2001-03-06 Advanced Micro Devices, Inc. Communication link with isochronous and asynchronous priority modes
US6202116B1 (en) 1998-06-17 2001-03-13 Advanced Micro Devices, Inc. Write only bus with whole and half bus mode operation
US6532019B1 (en) 1998-06-17 2003-03-11 Advanced Micro Devices, Inc. Input/output integrated circuit hub incorporating a RAMDAC
US6891797B1 (en) * 1998-07-06 2005-05-10 Canon Kabushiki Kaisha Method and device for communicating information
US6119243A (en) * 1998-07-06 2000-09-12 Intel Corp. Architecture for the isochronous transfer of information within a computer system
US6101613A (en) * 1998-07-06 2000-08-08 Intel Corporation Architecture providing isochronous access to memory in a system
US6336179B1 (en) 1998-08-21 2002-01-01 Advanced Micro Devices, Inc. Dynamic scheduling mechanism for an asynchronous/isochronous integrated circuit interconnect bus
US6381647B1 (en) * 1998-09-28 2002-04-30 Raytheon Company Method and system for scheduling network communication
US6243778B1 (en) * 1998-10-13 2001-06-05 Stmicroelectronics, Inc. Transaction interface for a data communication system
JP3543649B2 (ja) * 1998-10-27 2004-07-14 セイコーエプソン株式会社 データ転送制御装置及び電子機器
US6272563B1 (en) 1998-11-03 2001-08-07 Intel Corporation Method and apparatus for communicating routing and attribute information for a transaction between hubs in a computer system
KR100359092B1 (ko) * 1998-11-18 2003-02-19 삼성전자 주식회사 가변 등시성 데이터 전송방법 및 그 장치
US6618782B1 (en) 1998-11-23 2003-09-09 Advanced Micro Devices, Inc. Computer interconnection bus link layer
US6499079B1 (en) 1998-11-23 2002-12-24 Advanced Micro Devices, Inc. Subordinate bridge structure for a point-to-point computer interconnection bus
US6457084B1 (en) 1998-11-23 2002-09-24 Advanced Micro Devices, Inc. Target side distributor mechanism for connecting multiple functions to a single logical pipe of a computer interconnection bus
US6690676B1 (en) 1998-11-23 2004-02-10 Advanced Micro Devices, Inc. Non-addressed packet structure connecting dedicated end points on a multi-pipe computer interconnect bus
US6457081B1 (en) 1998-11-23 2002-09-24 Advanced Micro Devices, Inc. Packet protocol for reading an indeterminate number of data bytes across a computer interconnection bus
US6470410B1 (en) 1998-11-23 2002-10-22 Advanced Micro Devices, Inc. Target side concentrator mechanism for connecting multiple logical pipes to a single function utilizing a computer interconnection bus
US6421751B1 (en) 1998-11-23 2002-07-16 Advanced Micro Devices, Inc. Detecting a no-tags-free condition in a computer system having multiple outstanding transactions
US6611891B1 (en) 1998-11-23 2003-08-26 Advanced Micro Devices, Inc. Computer resource configuration mechanism across a multi-pipe communication link
US6256698B1 (en) 1999-01-11 2001-07-03 Sony Corporation Method of and apparatus for providing self-sustained even arbitration within an IEEE 1394 serial bus network of devices
US6425032B1 (en) 1999-04-15 2002-07-23 Lucent Technologies Inc. Bus controller handling a dynamically changing mix of multiple nonpre-emptable periodic and aperiodic devices
US6351783B1 (en) * 1999-05-20 2002-02-26 Intel Corporation Method and apparatus for isochronous data transport over an asynchronous bus
US6600756B1 (en) * 1999-06-14 2003-07-29 Hewlett-Packard Development Company, Lp. Method of improving the performance of a bus which is asynchronous-traffic intensive
US6611926B1 (en) * 1999-11-29 2003-08-26 Hewlett-Packard Development Company, L.P. Mechanisms to sample shared-dirty-line addresses
US7406554B1 (en) * 2000-07-20 2008-07-29 Silicon Graphics, Inc. Queue circuit and method for memory arbitration employing same
US6859852B2 (en) * 2000-09-08 2005-02-22 Texas Instruments Incorporated Immediate grant bus arbiter for bus system
US6901451B1 (en) * 2000-10-31 2005-05-31 Fujitsu Limited PCI bridge over network
DE10219359B4 (de) * 2002-04-30 2007-05-03 Advanced Micro Devices, Inc., Sunnyvale Vorrichtung und Verfahren mit einem Queuemechanismus
US7206866B2 (en) * 2003-08-20 2007-04-17 Microsoft Corporation Continuous media priority aware storage scheduler
US7433984B2 (en) * 2004-10-13 2008-10-07 Texas Instruments Incorporated Time-based weighted round robin arbiter
JP4282591B2 (ja) * 2004-11-30 2009-06-24 株式会社東芝 スケジュール管理装置、スケジュール管理方法及びプログラム
KR100970595B1 (ko) 2008-10-20 2010-07-16 한국항공우주연구원 주기/비주기 통신 테이블의 데이터 구조를 이용한 통신 시스템 및 방법
JP2010165175A (ja) * 2009-01-15 2010-07-29 Internatl Business Mach Corp <Ibm> バスの使用権を制御する装置および方法
JP2015166972A (ja) * 2014-03-04 2015-09-24 セイコーエプソン株式会社 転送システムおよび印刷装置
US9794979B2 (en) 2015-04-13 2017-10-17 Qualcomm Incorporated Method for arbitration and adaptive power-cycling in a multi-channel network
CN110603523B (zh) 2017-05-05 2023-09-08 微芯片技术股份有限公司 用于对串行通信链路上的事件的传输进行优先级排序的设备和方法
WO2018204399A1 (fr) 2017-05-05 2018-11-08 Microchip Technology Incorporated Dispositifs et procédés de transmission d'événements avec une latence uniforme sur des liaisons de communication en série
CN113268183B (zh) * 2021-05-21 2023-04-07 北京自如信息科技有限公司 一种列表页面倒计时显示方法及装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0346141A2 (fr) * 1988-06-10 1989-12-13 Westinghouse Electric Corporation Réseau haute performance à mémoire représentative pour système de commande de processus en temps réel
JPH04266236A (ja) * 1991-02-20 1992-09-22 Mitsubishi Electric Corp 通信方式
EP0523874A2 (fr) * 1991-07-01 1993-01-20 AT&T Corp. Méthode d'opération d'un bus de paquets asynchrones pour transmettre des informations isochrone et asynchrone

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4593282A (en) * 1983-04-14 1986-06-03 At&T Information Systems Inc. Network protocol for integrating synchronous and asynchronous traffic on a common serial data bus
DE3480962D1 (de) * 1984-10-31 1990-02-08 Ibm Deutschland Verfahren und einrichtung zur steuerung einer sammelleitung.
US4667191A (en) * 1984-12-21 1987-05-19 Motorola, Inc. Serial link communications protocol
US4736366A (en) * 1986-02-13 1988-04-05 International Business Machines Corporation Bus acquisition system
US4980886A (en) * 1988-11-03 1990-12-25 Sprint International Communications Corporation Communication system utilizing dynamically slotted information
US4969120A (en) * 1989-02-13 1990-11-06 International Business Machines Corporation Data processing system for time shared access to a time slotted bus
FR2648647B1 (fr) * 1989-06-19 1991-08-23 Alcatel Business Systems Procede et dispositif d'arbitrage pour acces en emission au support de transmission d'un reseau de commutation reparti
US4961188A (en) * 1989-09-07 1990-10-02 Bell Communications Research, Inc. Synchronous frequency encoding technique for clock timing recovery in a broadband network
CA2051029C (fr) * 1990-11-30 1996-11-05 Pradeep S. Sindhu Arbitrage de bus de transmission de paquets commutes, y compris les bus de multiprocesseurs a memoire commune
US5339425A (en) * 1990-12-11 1994-08-16 Fisher Controls International, Inc. Operating system for a process controller
FR2677473B1 (fr) * 1991-06-05 1995-04-07 Telemecanique Procede et bus d'arbitrage pour transmission de donnees serie.
US5402416A (en) * 1994-01-05 1995-03-28 International Business Machines Corporation Method and system for buffer occupancy reduction in packet switch network
US5392280A (en) * 1994-04-07 1995-02-21 Mitsubishi Electric Research Laboratories, Inc. Data transmission system and scheduling protocol for connection-oriented packet or cell switching networks
US5463624A (en) * 1994-04-15 1995-10-31 Dsc Communications Corporation Bus arbitration method for telecommunications switching

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0346141A2 (fr) * 1988-06-10 1989-12-13 Westinghouse Electric Corporation Réseau haute performance à mémoire représentative pour système de commande de processus en temps réel
JPH04266236A (ja) * 1991-02-20 1992-09-22 Mitsubishi Electric Corp 通信方式
EP0523874A2 (fr) * 1991-07-01 1993-01-20 AT&T Corp. Méthode d'opération d'un bus de paquets asynchrones pour transmettre des informations isochrone et asynchrone

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
"Access to high-speed LAN via wireless media", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 36, no. 4, NEW YORK, US, pages 59 - 62 *
PATENT ABSTRACTS OF JAPAN vol. 17, no. 57 (E - 1315) 4 February 1993 (1993-02-04) *

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998012646A1 (fr) * 1996-09-23 1998-03-26 Silicon Graphics, Inc. Procede d'attribution garantie de largeur de bande dans un systeme informatique pour transferts de donnees entree/sortie
US5784569A (en) * 1996-09-23 1998-07-21 Silicon Graphics, Inc. Guaranteed bandwidth allocation method in a computer system for input/output data transfers
US7003606B2 (en) 1997-03-21 2006-02-21 Hitachi, Ltd. Electronic device, method for using electronic device, and electronic device system for reserving bus usage time on a bus to conduct communications between electronic devices
US6757765B1 (en) 1997-03-21 2004-06-29 Hitachi, Ltd. Electronic device, method for using electronic device, and electronic device system for reserving bus usage time on a bus to conduct communications between electronic devices
US6363461B1 (en) 1999-12-16 2002-03-26 Intel Corportion Apparatus for memory resource arbitration based on dedicated time slot allocation
EP1752881A1 (fr) * 1999-12-16 2007-02-14 Intel Corporation Appareil destine a l'arbitrage de ressource de mémoire en fonction de l'attribution de l'intervalle de temps dédiée
US6412049B1 (en) 1999-12-16 2002-06-25 Intel Corporation Method for minimizing CPU memory latency while transferring streaming data
US6415367B1 (en) 1999-12-16 2002-07-02 Intel Corporation Apparatus for reducing asynchronous service latency in a time slot-based memory arbitration scheme
EP1762941A1 (fr) * 1999-12-16 2007-03-14 Intel Corporation Appareil d'arbitrage de ressources de mémoire basé sur l'allocation d'intervalles de temps dédiés
WO2001044955A3 (fr) * 1999-12-16 2002-03-07 Intel Corp Appareil destine a l'arbitrage de ressource de memoire en fonction de l'attribution de l'intervalle de temps dediee
WO2001044955A2 (fr) * 1999-12-16 2001-06-21 Intel Corporation Appareil destine a l'arbitrage de ressource de memoire en fonction de l'attribution de l'intervalle de temps dediee
EP1178395A3 (fr) * 2000-07-31 2009-05-20 Texas Instruments Incorporated Appareil et méthode de communication d'un message numérique multimot avec un processeur de signal isochrone
EP1178632A2 (fr) * 2000-08-04 2002-02-06 Siemens Aktiengesellschaft Procédé de transmission cyclique par bus
EP1178632A3 (fr) * 2000-08-04 2003-07-30 Siemens Aktiengesellschaft Procédé de transmission cyclique par bus
WO2003048950A1 (fr) * 2001-12-03 2003-06-12 Koninklijke Philips Electronics N.V. Systeme de bus de communication
WO2006035344A1 (fr) 2004-09-28 2006-04-06 Koninklijke Philips Electronics N.V. Systeme et procede de traitement de donnees pour arbitrage memoire
US7913014B2 (en) 2004-09-28 2011-03-22 Nxp B.V. Data processing system and method for memory arbitration
WO2006117746A1 (fr) * 2005-05-04 2006-11-09 Nxp B.V. Controleur de memoire et procede pour controler l'acces a une memoire, ainsi que systeme comprenant un controleur de memoire
WO2008035352A2 (fr) * 2006-09-18 2008-03-27 Sandisk Il Ltd. Procédé et dispositif de stockage permettant d'évaluer une durée pour une opération de stockage
WO2008035352A3 (fr) * 2006-09-18 2008-06-26 Sandisk Il Ltd Procédé et dispositif de stockage permettant d'évaluer une durée pour une opération de stockage

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US5621898A (en) 1997-04-15
JP3729546B2 (ja) 2005-12-21

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