EP0694846B1 - Programmed circuit for numerical scrambling - Google Patents

Description

The invention relates to a scrambling method digital and its application to a programmable circuit, basically to protect from inspection the contents of an executable program. The invention particularly applies to secure management circuits financial transactions.

The instruction data of a contained program in a program memory are usually protected by mixing physical addresses in memory of this instruction data. So this data doesn't are more stored in memory according to their address logical, but scattered. In operational mode of programmable circuit, a specific decoding circuit allows to find the real physical address in memory of instruction data according to its address logic.

This process provides protection against visual inspection of program memory. However, the instruction data flows in clear on the data bus, to be executed by the circuit microprocessor. However, it is technically possible to place a spy on the data bus, to read the data in transit. The program can then be replenished. Protection in practice contribution is therefore limited.

In addition, the complexity of the decoding circuit address to find the addresses real physics leads to using the same keys of coding and hence the same decoding circuit for a product family to reduce costs Manufacturing.

However, if a fraudster succeeds in reconstructing the program for one of the products it gets a correspondence between physical addresses and logical addresses, which will allow it to find the keys and the algorithm used to mix the addresses. He will thus have the solution for the whole family.

A device which scrambles the data is known from US-4,633,388.

An object of the invention is to improve the data protection in a circuit programmed in using a permutation scrambling process data bits.

Another object of the invention is a method of protection of this data easy to implement, allowing individual protection for each product.

We know that an executable program contains data, some of which constitute instructions for This program.

It is provided according to the invention that either these instruction data or other data is scrambled in program memory. Which means the bit swapping of one of these groups of data is performed at code generation executable. In this way, we have program memory scrambled data among other data that does not are not.

We recall that according to the current meaning, we by program memory is meant all the addresses physical data stored in executable code. These addresses can be in different memory circuits, for example in memories ROM and RAM.

As defined in the claims, the invention therefore relates to a method of digital scrambling of data.

The invention relates to a programmed circuit. comprising at least one bit permutation circuit data, for n-bit data.

According to the invention, the permutation circuit includes n permutation stages with n inputs and one outlet, each floor comprising n cells of permutation.

Advantageously, a permutation cell is made using the same technology as the cells of program memory.

• la figure 1 représente le principe du brouillage selon l'invention,
• la figure 2 est un schéma-bloc d'un circuit programmable protégé selon l'invention,
• la figure 3 est un schéma de principe d'un circuit de permutation selon l'invention,
• la figure 4 est un dessin topologique de deux étages d'un circuit de permutation selon l'invention et
• la figure 5 est une vue en coupe AA du dessin topologique de la figure 4.

Other characteristics and advantages of the invention are presented in the following description, given by way of non-limiting example, and with reference to the appended drawings in which:

• FIG. 1 represents the principle of interference according to the invention,
• FIG. 2 is a block diagram of a protected programmable circuit according to the invention,
• FIG. 3 is a block diagram of a permutation circuit according to the invention,
• FIG. 4 is a topological drawing of two stages of a permutation circuit according to the invention and
• FIG. 5 is a sectional view AA of the topological drawing of FIG. 4.

According to the invention, an executable code generator discriminates instruction data from other data of a program, to apply interference by permutation of the bits or else to this data instructions, or other data. It's that which is represented in figure 1. We obtain a code executable that contains scrambled data among others who are not.

This executable code is stored in memory program of a programmable circuit: programming by mask in read only memory and / or download in memory rewritable (RAM, EEPROM or others).

A programmable circuit according to the invention is shown in Figure 2. It includes a unit of UC control which is a microprocessor type organ, with an instruction entry on a register RI instruction and data entry on a data register and which includes a unit programmed UP. This programmed unit receives instruction data to execute from the registry RI instruction and controls the RD data register and for example arithmetic circuits and logic, or counters, grouped in a circuit of calculation referenced 1 in the figure. In the example shown, computation circuit 1 receives data of the RD data register on which it performs calculations according to unit instructions programmed.

The different data are transferred to the data or instruction registers by a bus DBUS data connected to different memory circuits.

In the example shown in Figure 2, the circuit programmable includes ROM read only memory and rewritable memories, in the example a memory RAM and programmable and erasable memory electrically EEPROM.

In this example, we expect that executable code is stored in ROM and RAM memories.

According to the invention, it is expected that the data of the program memory pass either in clear or scrambled on the data bus depending on whether they are instruction data or not.

Preferably, we choose that it is the data of instructions that pass through scrambled. And a circuit of permutation DBr1 is placed at the input of instructions of the control unit, to unscramble the data instructions in program memory and transferred by the DBUS data bus. The data instructions are therefore scrambled on the bus data.

If it was the other data that was scrambled by the code generator a permutation inverse is applied at the output of program memory, so that the instruction data is scrambled on the bus. Or the scrambled data passes scrambled on the bus and a swap circuit is provided for data input from the control unit.

The method according to the invention therefore makes it possible to many combinations.

In the example shown in Figure 2, which is intended more particularly for cases where the data of instructions pass through scrambled on the bus among the other data in clear, we planned two other permutation circuits DBr2 and DBr3. The first is placed between the RAM memory and the data bus, and the second is placed between the EEPROM memory and the bus data. In this way, the data stored in these two rewritable memories are scrambled respectively according to a second and third permutation, but transit unscrambled on the bus data.

More specifically, in the example shown, the instruction data stored in RAM have underwent two permutations: the first which is their specific, performed on code generation and second applied as memory input. And 1a second permutation is unscrambled before the data transmission on the bus. The second permutation is preferably different from the first applied to instruction data.

We could also have another memory without associated permutation circuit.

Thus, the method according to the invention allows apply different interference to data of program memory instructions as the one applied to other data: stored shapes, shapes transmitted different, and also to apply interference different to each of the rewritable memories: permutation or not, selection of the permutation of bits different from one rewritable memory to another.

According to the invention, the difficulties are thus increased spying on data and understanding the protection device.

The structure chosen will mainly depend on the intended application. Finally, we will see that we can easily use different permutations of a programmable circuit to another.

An example of realization of a circuit of permutation used in the invention is detailed on the block diagram of Figure 3.

The DBUS data bus having a width of n bits, the permutation circuit comprises n stages of permutation, that is Ep0 to Ep7 in the example (n = 8).

Each permutation stage receives as input n bits of the data bus, i.e. D0-D7 in the example and delivers an unscrambled output bit: the stage of permutation Ep0 delivers the output bit Di0, ..... the permutation stage Ep7 delivers the output bit Di7. It is these output bits Di0-Di7 which are applied as input to the RI instruction register.

Each permutation stage includes n cells of permutation c0-c7 in the example whose function is that of a fuse, only one of n allowing the transmission of the associated input data bit on the floor output data bit.

Each permutation stage corresponds to a rank of different pass cell.

In the example shown, the floor cell
Ep0 is c7
Ep1 c3
Ep2 c6
.
.
.
Ep7 c0.

n possibilités pour le premier étage Ep0;

n-1 possibilités pour le deuxième étage Ep1;

et ainsi de suite.

The permutation circuit DBr1 is thus characterized by a permutation selection for each stage. For a bus with n data bits, we have:

n possibilities for the first stage Ep0;

n-1 possibilities for the second stage Ep1;

And so on.

The scrambling method according to the invention allows so n! different scrambling possibilities for a data bus of width n bits.

If the memories have a different width of the bus of n given bits and in particular a greater width, each slice of n bits is swapped according to the invention. And if the program memory is larger, the executable code generator must perform the scrambling of executable program data after have cut them into n-bit slices.

An example of realization of a circuit of permutation according to the invention is shown in figures 4 and 5.

Figure 4 shows a topological drawing of two permutation stages Ep0 and Ep1 at n = 8 bits input (D0-D7) and one output bit, respectively Di0 and Di1, and FIG. 5 represents a section AA of this drawing.

For each permutation stage Ep0, Ep1 we have a middle interconnection layer DM0, DM1, connected to the output bit line of the floor.

And, for each cell c0-c7 of a stage of permutation, we have a local interconnection layer connected to the input bit line associated with this cell. For example, we have an interconnection layer local D10 for cell c0, connected to the line of input data bit D0.

Programming a permutation stage consists of then in an extension of the interconnection layer median at the local interconnection layer of a cell among the n cells of this stage of permutation. In the example shown, we thus have for stage Ep0 an extension of the interconnection layer median DM0 at the local interconnection layer D17 of cell c7 and for stage Ep1, we have an extension from the middle interconnection layer DM1 to the layer of local interconnection D13 of cell c3.

In the example shown, the bit lines of input data D0-D7 are metal, and parallel between them and the output data bit line, for example Di0, is in polysilicon, in a plane between the plane of the data bit lines input and the substrate. The layer contact interconnection point to the data bit line outlet is done by a metal line made in the same plane as the input data bit lines and parallel to them. This metal line is noted lm0 for the stage Ep0 and lm1 for the stage Ep1.

The middle or local interconnection layers can be made in diffusion, metal or others, based on programmable circuit technology.

For example and as more particularly shown in Figures 4 and 5, they are made in diffusion, by ion implantation (called process implant). Or the middle interconnection layer is it made of metal.

In section AA represented in FIG. 5, we distinguishes for example for the stage Ep0 the line of Di0 polysilicon data output, connected to the metal line lm0 above, and the contacts of this metal line on the middle interconnection layer DM0 of the permutation stage Ep0.

The local interconnection layers D13 and D14 cells c3 and c4 of stages Ep0 and Ep1 are also visible in this figure 5. And, we see the extension of the middle interconnection layer DM1 to the layer local interconnection D13 of cell c3 of the floor Ep1.

The specialization of a permutation stage is therefore by extension of the interconnection layer median to the local interconnect layer which contact the input data bit line selected (mask drawing).

Programming the permutation circuit according to the invention then consists according to this method of manufacturing to select layer extension interconnection layer at the interconnection layer locale which defines permutation, extension which goes allow the input bit line to be connected to the line output bit.

This programmable specialization is particularly easy to implement, allowing flexibility in adapting the manufacturing process to each programmable circuit: use of circuits of permutation on the other memories or not, with jamming identity or not, etc ... and allowing a different interference for each programmable circuit: We no longer have a protective identity within the same family. This results in protection considerably improved programmable circuits.

• d'une part, on réalise les cellules de permutation et les cellules de mémoire morte dans les mêmes étapes de fabrication, avec les mêmes masques, au moyen des mêmes types de couches d'interconnexion; la programmation ou particularisation du circuit pour le programme et le brouillage spécifiés par le client se fait au même niveau de fabrication, d'où une grande simplification de la fabrication;
• d'autre part, on augmente la difficulté d'inspection visuelle du circuit par utilisation de technologies similaires.

Advantageously, for a program memory of the read only memory type, the same manufacturing method is used as for the permutation circuit:

• on the one hand, the permutation cells and the read-only memory cells are produced in the same manufacturing steps, with the same masks, by means of the same types of interconnection layers; the programming or specificization of the circuit for the program and the interference specified by the customer is done at the same level of manufacturing, hence a great simplification of manufacturing;
• on the other hand, the difficulty of visual inspection of the circuit is increased by the use of similar technologies.

According to the process described in relation to Figures 4 and 5, data programming executables scrambled in read-only memory is performed, using a middle interconnect layer to the same bit line and an interconnection layer local for each cell extended or not to the layer interconnection point according to the programmed state desired 0 or 1 of the cell.

Claims (9)

1. Programmed circuit comprising a program memory (ROM, RAM) connected by at least one data bus (DBUS) to a control unit (UC), the program memory containing data of an executable code scrambled by applying a permutation of bits to data of the said code, the said permutation being applied either to the instruction data or to other data of the said code and the programmed circuit comprising at least a first permutation circuit (DBr1) between the said data bus and an instruction input or a data input of the said control unit, characterised in that the said permutation circuit comprises n input bit lines (D0-D7) and supplies as an output n output bit lines (Di0-Di7), and n programmed permutation stages (Ep0-Ep7) per mask, each permutation stage (Ep0) receiving the said n input bit lines (D0-D7) and supplying a single output bit line (Di0), and comprising one permutation cell (c0-c7) per input bit line (D0-D7), the programming of each stage consisting of making, in only one cell (c7) amongst the n cells of each stage, an electrical interconnection between the input bit line (D7) electrically connected to the said cell and the output bit line of the stage (Di0), the electrical connections to the input data bit lines and to the output bit lines and the interconnections corresponding to levels of manufacture and interconnection of the circuit.
2. Programmed circuit according to Claim 1, characterised in that the scrambled data of the executable code stored in program memory are the data other than the instruction data and in that another permutation circuit is provided, placed between the program memory and the data bus, in order to apply a corresponding scrambling to these data, and to apply a corresponding scrambling to the instruction data before they are transmitted over the data bus, the first permutation circuit (DBr1) being provided at the instruction input of the control unit (UC).
3. Programmed circuit according to Claim 1 or 2, in which the instruction data of the program memory pass scrambled over the data bus and in which the first permutation circuit (DBr1) is applied as an instruction input of the control unit (UC), and comprising one or more writeable or rewriteable memories (RAM, EEPROM) belonging or not to the program memory, characterised in that it comprises at least one other permutation circuit (DBr2), placed between the data bus (DBUS) and a writeable or rewriteable memory (RAM), in order to apply a corresponding jamming to the data coming from the data bus and to be written in the said memory and to apply a corresponding unscrambling to the data of the said memory to be transmitted over the bus.
4. Programmed circuit according to Claim 3, characterised in that the permutation circuits (DBr2, DBr3) associated with different writeable or rewriteable memories effect different permutations.
5. Programmed circuit according to Claim 3 or 4, characterised in that the first permutation circuit (DBr1) at the instruction input of the control unit and a permutation circuit (DBr2) associated with a writeable or rewriteable memory (RAM) are such that they effect different permutations.
6. Programmed circuit according to any one of the preceding claims, characterised in that each permutation cell (c0) associated with an input data bit line (D0) of a permutation stage comprises a local interconnection line (D10) connected to the said input bit line (D0), and in that each permutation stage (Ep0) comprises a middle interconnection line (DM0) connected to the output data bit line (Di0), the programmed interconnection in each stage consisting of an extension of the said middle interconnection line (DM0) to the said local interconnection line (D10) of one cell amongst the n cells of the said permutation stage.
7. Programmed circuit according to Claim 6, characterised in that the middle interconnection line (DM0) and the local interconnection lines (D10-D17) are interconnection lines produced by ion implantation.
8. Programmed circuit according to Claim 7, characterised in that the middle interconnection line (DM0) of each permutation stage is produced from metal and the local interconnection line (D10-D17) in diffusion, by ion implantation.
9. Programmed circuit according to any one of Claims 1 to 5, comprising a read only memory (ROM), characterised in that the permutation cells (c0-c7) are produced like the cells of the said read only memory.

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