WO2000026791A2 - Secure memory management unit which uses multiple cryptographic algorithms - Google Patents
Secure memory management unit which uses multiple cryptographic algorithms Download PDFInfo
- Publication number
- WO2000026791A2 WO2000026791A2 PCT/US1999/026171 US9926171W WO0026791A2 WO 2000026791 A2 WO2000026791 A2 WO 2000026791A2 US 9926171 W US9926171 W US 9926171W WO 0026791 A2 WO0026791 A2 WO 0026791A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- algorithm
- encrypted data
- integrated circuit
- external memory
- memory
- Prior art date
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
- G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
Definitions
- the present invention concerns memory management in a computer system designs and pertains particularly to a secure memory management unit which uses multiple cryptographic algorithms.
- secure information within a computing system can be encrypted before being, stored in the memory for the computing system.
- secure integrated circuit uses the secure information
- the secure information is transferred to the integrated circuit and decrypted before being used.
- Secure information returned to the memory for the computing system is encrypted before being stored.
- SMMU secure memory management unit
- SRAM static random access memory
- the SMMU performs the swap out of the "dirty" page of information before the new page is placed in the cache.
- a "dirty" page of information is a page of information which has been written to while in the cache where the changes made have not been written out to the system memory. If the "dirty" page of information contains secure information, the SMMU first encrypts the page before swapping the page out to system memory. While performing page swapping the SMMU holds off the processor while pages are being swapped to and from the processor cache.
- the SMMU handles all secure information for a computing system.
- the secure information can include both executable code (typically stored in a read-only memory (ROM)) and data (typically stored in random access memory (RAM)).
- executable code typically stored in a read-only memory (ROM)
- RAM random access memory
- an integrated circuit accesses first encrypted data stored in an external random access memory and accesses second encrypted data stored in an external read-only memory.
- the external random access memory and the external read-only memory are external to the integrated circuit.
- a first algorithm is used to decrypt the first portion of the first encrypted data.
- a second algorithm is used to decrypt the first portion of the second encrypted data. The second algorithm is different than the first algorithm.
- the first portion of the second encrypted data includes instructions for execution by a processor and the first portion of the first encrypted data includes data used during execution by the processor.
- the first algorithm is used to encrypt the first portion of the first encrypted data.
- a new decryption key for the first algorithm is generated upon start-up and upon reset of the integrated circuit.
- the present invention allows for an increase in security.
- the use of different algorithms allows a highly secure algorithm to be used for information which is only to be decrypted and a less secure algorithm for data which will be encrypted and decrypted.
- One reason the less secure algorithm does not need to be as strong as the highly secure algorithm is because the data encrypted by the less secure algorithm does not remain encrypted for as long a period of time as data encrypted by the highly secure algorithm. In this way security may be provided while at the same time providing greater flexibility in designing parts which conform to various export laws which forbid export of parts with certain encryption capability.
- Figure 1 is a simplified block diagram illustrating different cryptographic algorithms being used on information dependent upon whether the information is an instruction stored in ROM or data stored in RAM in accordance with the preferred embodiment of the present invention.
- Figure 2 is a simplified block diagram of an integrated circuit which includes a secure memory management unit in accordance with the preferred embodiment of the present invention.
- FIG 3 is a simplified block diagram of the secure memory management unit shown in Figure 2 in accordance with the preferred embodiment of the present invention.
- FIG 4 is a simplified block diagram which shows data flow of secure information from an external system memory into cache memory within the integrated circuit shown in Figure 2 in accordance with the preferred embodiment of the present invention.
- Figure 5 illustrates usage of registers within the secure memory management unit shown in Figure 3 in accordance with the preferred embodiment of the present invention.
- Figure 6 is a simplified block diagram which illustrates data flow for a data miss within the integrated circuit shown in Figure 2 in accordance with the preferred embodiment of the present invention.
- FIG. 1 is a simplified block diagram illustrating different cryptographic algorithms, within a single secure memory management unit (SMMU) 13, being used on information dependent upon whether the information is an instruction stored in an external read-only memory
- SMMU secure memory management unit
- SMMU single-dimensional memory
- RAM random access memory
- Any type of SMMU system implemented in either hardware or software can be used to implement SMMU 13.
- a decryption algorithm 94 is used for decryption before placing the information in a section of memory reserved as ROM secure information 92.
- an encryption/decryption algorithm 93 is used for decryption before placing the information in a section of memory reserved as ROM secure information 92, and is used for encryption before returning the information back into external RAM 45.
- Encryption/decryption algorithm 93 can be made more secure by randomly generating, after each reset of SMMU 13, a unique reset key used in encryption/decryption algorithm 93. This separate reset key is then used to encrypt/decrypt RAM secure information 91 passing through SMMU 13.
- Encryption algorithm 93 is a different key than the key used for decryption algorithm 94.
- encryption/decryption algorithm 93 and decryption algorithm 94 operate in accordance with the Data Encryption Standard (DES).
- DES Data Encryption Standard
- Decryption algorithm 94 is, for example, a 56-bit 3 DES algorithm which uses a 56-bit secure key.
- Encryption/decryption algorithm 93 is, for example, a 40-bit 1 DES algorithm which uses a 40-bit secure key. Because encryption is only performed using the 40-bit 1 DES algorithm, maximum performance is obtained while still providing significant protection for ROM secure information 92 and RAM secure information 91.
- the two algorithm system may be variously integrated into processor systems which utilize a secure memory management unit (SMMU).
- SMMU secure memory management unit
- Figure 2 is a simplified block diagram of an integrated circuit which includes a system processor 12, a soft secure memory management unit (SMMU) 13, and main memory 14 connected to a processor bus 11.
- processor 11 is an ARM7TDMI processor or another processor that may be included on an integrated circuit.
- Main memory 14 is, for example, implemented as a static random access memory (SRAM).
- a hardware encryption core 16 may be included.
- encryption/decryption may be performed by system processor 12.
- encryption and decryption is performed in accordance with the Data Encryption Standard (DES).
- Soft SMMU 13 takes advantage of system processor 12 to handle page allocation and data movement for page updates.
- DES Data Encryption Standard
- Soft SMMU 13 Functionality of soft SMMU 13 is reduced to maintaining page information and triggering an abort of the memory cycle on a page miss.
- System processor 12 can interrupt the abort as a page miss and update the page registers in the soft SMMU 13. The new page can then be loaded and decrypted by system processor 12. This allows great flexibility in the determination of multiple pages, write back capability, or locking pages that are used often.
- hardware encryption core 16 is not required for low end applications or for simple encryption methods. For these case an encryption/decryption algorithm can be resident on system processor 12.
- the hardware within soft SMMU 13 is page modular. The timing requirements are greatly reduced since soft SMMU 13 only compares an address received on an external bus to the page boundaries in the page registers within soft SMMU 13. Soft SMMU 13 can abort the cycle at the end of the memory transaction, therefore soft SMMU 13 does not have to make a comparison at the beginning of the cycle. Since data is moved by system processor 12, there are no special DMA ports or DMA busses that are necessary. System processor 13 can move the data on the memory bus 11.
- the data pages that are cached by system processor 12 can be stored as pages 15 in main memory 14, which serves as scratch memory space for processor 12. Instructions that are cached by system processor 12 can be stored as pages 115 in main memory 14. Alternatively, the instructions can be stored in a separate instruction cache.
- Soft SMMU 13 is a simple peripheral attached to processor bus 11.
- Soft SMMU 13 monitors address requested by system processor 12 for an instruction or data operation that is within the page limits of secure information stored in an external system memory (either external RAM 45 or external ROM 145).
- the external system memory is external to the integrated circuit.
- Limit registers within soft SMMU 13 indicate the page limits of secure information stored in the external system memory. If the data requested by system processor 12 is within the page limits of secure information stored in the external system memory but is not located on a page that is currently held in main memory 14, soft SMMU 13 will abort the operation using an abort line 17.
- Figure 3 is a simplified block diagram of soft SMMU 13.
- Limit registers 22 store page limits for secure information within an external system memory external to the integrated circuit.
- a comparison circuit 23 compares the page limits in limit registers 22 with an address on address lines 21 of processor bus 11. When the address on address lines 21 is within the page limits in limit registers 22, a WITHIN flag on a line 33 is asserted true.
- Registers 24 contain information (e.g., start address and page size) of a "page 0" of data stored in pages 15 of main memory 14.
- a comparison circuit 25 compares the information in registers 24 with the address on address lines 21 of processor bus 11 to determine whether the address on address lines 21 addresses data stored in "page 0" of data stored in pages 15 of main memory 14. When the address on address lines 21 addresses data stored in "page 0" of data stored in pages 15, an "EQ0" flag on a line 30 is asserted true
- Registers 26 contain information (e.g., start address and page size) of a "page 1" of data stored in pages 15 of main memory 14.
- a comparison circuit 27 compares the information in registers 26 with the address on address lines 21 of processor bus 11 to determine whether the address on address lines 21 addresses data stored in "page 1" of data stored in pages 15 of main memory 14. When the address on address lines 21 addresses data stored in "page 1" of data stored in pages 15, an "EQ1" flag on a line 31 is asserted true.
- soft SMMU 13 contains similar circuitry.
- registers 28 contain information (e.g., start address and page size) of a "page N" of data stored in pages 15 of main memory 14.
- a comparison circuit 29 compares the information in registers 28 with the address on address lines 21 of processor bus 11 to determine whether the address on address lines 21 addresses data stored in "page N" of data stored in pages 15 of main memory 14. When the address on address lines 21 addresses data stored in "page N" of data stored in pages 15, an "EQN" flag on a line 32 is asserted true.
- Limit registers 22 and registers 24, 26 and 28 can be accessed by processor 12. This allows for great flexibility in configuring the external memory, main memory 14 and the page size of individual pages.
- soft SMMU 13 determines there is a HIT when the address on address lines 21 results in, for a page X, the EQ flag being asserted (EQX) and the page being enabled (ENABLEX). Thus there is a HIT on page 0 for EQO AND ENABLEO. There is a HIT on page 1 for EQ1 AND ENABLE 1. There is a HIT on page N for EQN AND ENABLEN.
- the address on address lines 21 is used to access a value within pages 15 or pages 115 of main memory 14, when there is a fetch command and the address on address lines 21 results in a HIT and the WITHIN flag on a line 33 is asserted true.
- Soft SMMU 13 detects a miss when there is a fetch command and the address on address lines 21 does not result in a HIT and the WITHIN flag on a line 33 is asserted true. In this case, the desired page needs to be swapped in from the external system memory and decrypted. If necessary (and only for pages 15 from external RAM 45) a page is swapped out of main memory 14 to make room for the new page.
- System processor 12 is the engine which performs necessary SMMU operations to allow encrypted data external to the integrated circuit to be utilized by system processor 12.
- processor performs encryption and decryption using two encryption engines to implement two separate decryption algorithms (an encryption/decryption algorithm for data from external RAM 45 and a decryption algorithm for information from external ROM 145).
- system processor 12 can perform encryption and decryption using two separate software algorithms (a software encryption/decryption algorithm for data from external RAM 45 and a software decryption algorithm for information from external ROM 145).
- FIG. 4 is a simplified block diagram which shows data flow of secure information from external system memory 45 into a data cache memory (pages 15 of main memory 14) for system processor 12 and shows data flow of secure information from external ROM 46 into an instruction cache memory (pages 115 of main memory 14) for system processor 12.
- a page of information from secure information 46 of external system memory 45 is received by an SMMU function 47 of the integrated circuit.
- the page of information contains secure data to be used by system processor 12.
- SMMU function 47 is implemented by soft SMMU hardware 13 and SMMU processes running on system processor 12.
- SMMU function 47 uses encryption engine 40 (or algorithms run by system processor 12) to decrypt the page of secure information, and places the decrypted information within pages 15 of main memory 14. Processor 12 can then access the decrypted information.
- a page of information from secure information 146 of external ROM 145 is received by an SMMU function 147 of the integrated circuit.
- the page of information contains secure instructions to be executed by system processor 12.
- SMMU function 147 is implemented by soft SMMU hardware 13 and SMMU processes running on system processor 12.
- SMMU function 147 uses encryption engine 140 (or algorithms run by system processor 12) to decrypt the page of secure information, and places the decrypted information within pages 115 of main memory 14. Processor 12 can then access the decrypted information.
- Figure 5 shows usage of registers within soft SMMU 13 for data from external system memory 45.
- Limit registers 22 store page limits for secure information within secure information 46 of external system memory 45 system.
- limit registers 22 include a register which contains a lower limit to a section A and an upper limit to section A of secure information 46, as shown in Figure 5.
- Limits for additional segments also may be stored in limit registers 22, as illustrated by the register which contains a lower limit to a section B and the register which contains an upper limit to section B.
- Current page information registers 51 identify addresses of pages currently in pages 15 of main memory 14. These pages, as needed, are moved back and forth from secure information 46 of external system memory 45 system, as described above. Use of current page information registers 51 is described more fully above in the discussion of registers 24, 26 and 28 shown in Figure 3.
- Figure 6 illustrates what happens when a page miss occurs for pages 15.
- a page miss is initiated when a program counter 82 for system processor 12 encounters an address which is not currently in main memory (SRAM) 14.
- Soft SMMU hardware 13 detects this as described above. Upon detection, soft SMMU 13 signals processor 12 on abort line 17. The SMMU process then takes control. If the requested address is within either the A or B limits (as set out in limit registers 22), the SMMU process claims the address and begins the process of fetching the page. Otherwise, the SMMU process will not claim the address and instead will allow a memory controller 85 to fetch the data.
- Last hit page is the page which was most recently hit.
- the algorithm is cyclic in that it simply picks the next page in sequence.
- the external page from secure pages 46 in external system memory 45 is loaded into the input registers of encryption engine 40 and decryption begins.
- the output registers of encryption engine 40 are then moved into the appropriate page within pages 15 of main memory 14.
- the SMMU process will also update the missed page register which indicates which page was most recently swapped. Once the page has been loaded into pages 15, the SMMU process re-enables normal processing of processor 12.
- a write back of data from pages 15 occurs if two conditions are met: the external memory limit range is write back enabled and the page being swapped out has changed. Only external system memory 45 is write back enabled, not pages 15 of main memory 14.
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- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Computer Hardware Design (AREA)
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- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Storage Device Security (AREA)
Abstract
Description
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Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000580099A JP2002529815A (en) | 1998-11-05 | 1999-11-04 | Secure memory management unit using multiple encryption algorithms |
EP99961596A EP1125206A2 (en) | 1998-11-05 | 1999-11-04 | Secure memory management unit which uses multiple cryptographic algorithms |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/186,546 US6910094B1 (en) | 1997-10-08 | 1998-11-05 | Secure memory management unit which uses multiple cryptographic algorithms |
US09/186,546 | 1998-11-05 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2000026791A2 true WO2000026791A2 (en) | 2000-05-11 |
WO2000026791A3 WO2000026791A3 (en) | 2000-07-27 |
Family
ID=22685369
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1999/026171 WO2000026791A2 (en) | 1998-11-05 | 1999-11-04 | Secure memory management unit which uses multiple cryptographic algorithms |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP1125206A2 (en) |
JP (1) | JP2002529815A (en) |
WO (1) | WO2000026791A2 (en) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1202150A2 (en) * | 2000-10-31 | 2002-05-02 | Kabushiki Kaisha Toshiba | Microprocessor with program and data protection function under multi-task environment |
GB2384336A (en) * | 2001-09-28 | 2003-07-23 | Lexar Media Inc | Non-volatile memory with encrypted data, which is scrambled and encoded. |
WO2004027586A2 (en) * | 2002-08-21 | 2004-04-01 | Audi Ag | Method for protecting against manipulation of a controller for at least one motor vehicle component and controller |
EP1482392A2 (en) * | 2003-02-18 | 2004-12-01 | Micronas GmbH | Processor with external memory |
EP1637960A2 (en) * | 2004-08-27 | 2006-03-22 | Microsoft Corporation | System and method for using address bits to signal security attributes of data in the address space |
US7162735B2 (en) | 2000-07-18 | 2007-01-09 | Simplex Major Sdn.Bhd | Digital data protection arrangement |
DE102005051577A1 (en) * | 2005-10-21 | 2007-05-03 | Engel Technologieberatung, Entwicklung/Verkauf Von Soft- Und Hardware Kg | Method for encrypting or decrypting data packets of a data stream and signal sequence and data processing system for carrying out the method |
US7653802B2 (en) | 2004-08-27 | 2010-01-26 | Microsoft Corporation | System and method for using address lines to control memory usage |
US7734926B2 (en) | 2004-08-27 | 2010-06-08 | Microsoft Corporation | System and method for applying security to memory reads and writes |
US7822993B2 (en) | 2004-08-27 | 2010-10-26 | Microsoft Corporation | System and method for using address bits to affect encryption |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7325115B2 (en) * | 2003-11-25 | 2008-01-29 | Microsoft Corporation | Encryption of system paging file |
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US5224166A (en) * | 1992-08-11 | 1993-06-29 | International Business Machines Corporation | System for seamless processing of encrypted and non-encrypted data and instructions |
EP0694846A1 (en) * | 1994-07-29 | 1996-01-31 | STMicroelectronics S.A. | Numerial scrambling method and its application to a programmable circuit |
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1999
- 1999-11-04 EP EP99961596A patent/EP1125206A2/en not_active Ceased
- 1999-11-04 JP JP2000580099A patent/JP2002529815A/en not_active Withdrawn
- 1999-11-04 WO PCT/US1999/026171 patent/WO2000026791A2/en not_active Application Discontinuation
Patent Citations (4)
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US4847902A (en) * | 1984-02-10 | 1989-07-11 | Prime Computer, Inc. | Digital computer system for executing encrypted programs |
US5224166A (en) * | 1992-08-11 | 1993-06-29 | International Business Machines Corporation | System for seamless processing of encrypted and non-encrypted data and instructions |
EP0694846A1 (en) * | 1994-07-29 | 1996-01-31 | STMicroelectronics S.A. | Numerial scrambling method and its application to a programmable circuit |
US5757919A (en) * | 1996-12-12 | 1998-05-26 | Intel Corporation | Cryptographically protected paging subsystem |
Cited By (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7162735B2 (en) | 2000-07-18 | 2007-01-09 | Simplex Major Sdn.Bhd | Digital data protection arrangement |
EP1202150B1 (en) * | 2000-10-31 | 2006-11-29 | Kabushiki Kaisha Toshiba | Microprocessor with program and data protection function under multi-task environment |
EP1202150A2 (en) * | 2000-10-31 | 2002-05-02 | Kabushiki Kaisha Toshiba | Microprocessor with program and data protection function under multi-task environment |
US7673152B2 (en) | 2000-10-31 | 2010-03-02 | Kabushiki Kaisha Toshiba | Microprocessor with program and data protection function under multi-task environment |
US7065215B2 (en) | 2000-10-31 | 2006-06-20 | Kabushiki Kaisha Toshiba | Microprocessor with program and data protection function under multi-task environment |
GB2384336A (en) * | 2001-09-28 | 2003-07-23 | Lexar Media Inc | Non-volatile memory with encrypted data, which is scrambled and encoded. |
GB2384336B (en) * | 2001-09-28 | 2005-08-10 | Lexar Media Inc | Improved data processing |
WO2004027586A2 (en) * | 2002-08-21 | 2004-04-01 | Audi Ag | Method for protecting against manipulation of a controller for at least one motor vehicle component and controller |
WO2004027586A3 (en) * | 2002-08-21 | 2004-04-29 | Audi Ag | Method for protecting against manipulation of a controller for at least one motor vehicle component and controller |
EP1482392A2 (en) * | 2003-02-18 | 2004-12-01 | Micronas GmbH | Processor with external memory |
EP1482392A3 (en) * | 2003-02-18 | 2005-08-03 | Micronas GmbH | Processor with external memory |
EP1637960A3 (en) * | 2004-08-27 | 2006-11-29 | Microsoft Corporation | System and method for using address bits to signal security attributes of data in the address space |
EP1637960A2 (en) * | 2004-08-27 | 2006-03-22 | Microsoft Corporation | System and method for using address bits to signal security attributes of data in the address space |
US7444523B2 (en) | 2004-08-27 | 2008-10-28 | Microsoft Corporation | System and method for using address bits to signal security attributes of data in the address space |
US7653802B2 (en) | 2004-08-27 | 2010-01-26 | Microsoft Corporation | System and method for using address lines to control memory usage |
US7734926B2 (en) | 2004-08-27 | 2010-06-08 | Microsoft Corporation | System and method for applying security to memory reads and writes |
US7822993B2 (en) | 2004-08-27 | 2010-10-26 | Microsoft Corporation | System and method for using address bits to affect encryption |
DE102005051577A1 (en) * | 2005-10-21 | 2007-05-03 | Engel Technologieberatung, Entwicklung/Verkauf Von Soft- Und Hardware Kg | Method for encrypting or decrypting data packets of a data stream and signal sequence and data processing system for carrying out the method |
DE102005051577B4 (en) * | 2005-10-21 | 2008-04-30 | Engel Solutions Ag | Method for encrypting or decrypting data packets of a data stream and signal sequence and data processing system for carrying out the method |
Also Published As
Publication number | Publication date |
---|---|
JP2002529815A (en) | 2002-09-10 |
WO2000026791A3 (en) | 2000-07-27 |
EP1125206A2 (en) | 2001-08-22 |
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