EP0689721A1 - Direct multilevel thin-film transistor production method - Google Patents

Direct multilevel thin-film transistor production method

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Publication number
EP0689721A1
EP0689721A1 EP94909965A EP94909965A EP0689721A1 EP 0689721 A1 EP0689721 A1 EP 0689721A1 EP 94909965 A EP94909965 A EP 94909965A EP 94909965 A EP94909965 A EP 94909965A EP 0689721 A1 EP0689721 A1 EP 0689721A1
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EP
European Patent Office
Prior art keywords
level
etching
semiconductor
insulating
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP94909965A
Other languages
German (de)
French (fr)
Inventor
Eric Sanson
Nicolas Szydlo
Bernard Hepp
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thomson-LCD
Original Assignee
Thomson-LCD
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Filing date
Publication date
Application filed by Thomson-LCD filed Critical Thomson-LCD
Publication of EP0689721A1 publication Critical patent/EP0689721A1/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate

Definitions

  • the present invention relates to a method for manufacturing thin film transistors (TFT), with a direct stepped structure and a low number of mask levels, making it possible to make contact between the gate of a transistor and the source or the drain of the same. or another transistor, and which can be used for the manufacture of flat liquid crystal screens, in particular on screens with integrated control electronics.
  • TFT thin film transistors
  • a liquid crystal display is made up of a number of liquid crystal cells arranged in a matrix and connected by lines and columns for connection to the control electronics.
  • a first support plate consists of a substrate containing a first set of electrodes, the control components of these electrodes, as well as the addressing lines and columns (active matrix).
  • the liquid crystal is contained between this plate and a second support plate constituting the counter-electrode.
  • Each pixel thus formed functions as an optical valve.
  • the local modification of the transmission or the reflection of the light is obtained by applying from the control electronics a voltage between an access contact of the plate and a contact of the counter plate. This voltage gives rise to an electric field between the facing electrodes and activates the volume of liquid crystal located between the two electrodes which more or less changes the characteristics of the light passing through it.
  • an active element with two (diode) or three terminations (transistor) is associated with each pixel and with each row - column intersection.
  • the manufacture of such screens can call upon methods of manufacturing active matrices made up of thin-film transistors.
  • These transistors can have a direct staged structure, that is to say that, with respect to the substrate, the grid is above the source and drain, or reverse staged, that is to say that the grid is located below the source and drain.
  • a direct stepped structure is described in European patent application 82 783 "process for manufacturing transistors in thin silicon layers on insulating substrate "(F. Morin et al), as well as in an article by JAPAN DISPLAY '86" A 6 "Diagonal Active Matrix Addressed LCD for MINITEL Application” by the same authors.
  • the technology described in these documents is very economical since it makes it possible to produce thin film transistors with only two levels of masks, by manufacturing the data columns at the same time as the electrodes.
  • an article by Y. Ugai et al "A 7.23-in. -Diagonal Color LCD Addresssed by a-Si TFTs" (SID 84 DIGEST, page 308) proposes the manufacture of a direct stage transistor made with three mask levels.
  • this invention overcomes these drawbacks through an economical manufacturing process with three or four levels of masks.
  • this invention relates to methods of manufacturing thin-film transistors direct stages with four levels of masks that can be used in a liquid crystal screen, it is characterized in that it comprises the following steps:. deposition and etching of a first conductive level on an insulating substrate so as to form a source and a drain,
  • deposition and etching of a second insulating level deposition and etching of a second conductive level producing the gate of the transistor.
  • the present invention also relates to a method of manufacturing thin-film transistors direct stages with three levels of masks which can be used in a liquid crystal screen, the steps of which are as follows:
  • This latter process can be followed by a step of etching the bilayer semiconductor level - insulating level using the etched conductive level as mask level, and a step of oxidation, nitriding or passivation of the etched sides of the level. semiconductor.
  • the present invention also relates to a method for manufacturing a liquid crystal screen, the active matrix transistors of which are manufactured by such methods.
  • Another object of the present invention is an electronic circuit produced on an insulating substrate by one of the mode of implementation of the method according to the invention.
  • the method according to the invention makes it possible to passivate the transistors during the process, to make them insensitive to light coming from above, the bottom being able to be protected by an opaque mask ("black matrix "in English) as described in French patent application No. 91 12586 filed by the applicant.
  • the method according to the invention allows the fabrication of integrated circuits on the same substrate as the active matrix thanks to the possibility that it offers of being able to connect the gates of the transistors to sources or drains of the same or other transistors, and thus be used in an "integrated drivers" technology. It is also possible to manufacture by this process different types of transistors and capacitances without adding additional levels of masks.
  • FIGS. 1 a to 1 c represent a first embodiment of the method according to the invention
  • FIG. 1 d represents a planar view of part of an active matrix screen produced according to the method of FIGS. 1 a to 1 c,
  • FIG. 1e represents the electrical diagram of the principle of an inverter
  • FIG. 1 f represents the reverser of the figure produced by the method of FIGS. 1 a to 1 c,
  • FIGS. 2a to 2d show a second embodiment of the method according to the invention
  • FIG. 2e represents a planar view of part of an active matrix screen produced according to the method of FIGS. 2a to 2c,
  • FIG. 2f represents a planar view of part of an active matrix screen produced according to the method of FIGS. 2a, 2b and 2d,
  • FIG. 2g shows the inverter of Figure 1 e manufactured by the method of Figures 2a to 2c
  • FIG. 2h represents the inverter of FIG. 1 e manufactured by the method of FIGS. 2a, 2b and 2d,
  • FIGS. 3a to 3c represent a third embodiment of the method according to the invention.
  • FIG. 3d represents a planar view of part of an active matrix screen produced according to the method of FIGS. 3a to 3c,
  • Figure 3e shows the inverter of Figure 1 e manufactured by the method of Figures 3a to 3c.
  • the same elements and the same materials were kept the same ref erence.
  • Figure 1a shows an insulating substrate 10 and can be transparent, on which a layer 1 1 of a transparent conductive material or a transparent conductive bilayer - doped semiconductor is deposited and etched during a first step performing, for example , source 1 (data column), drain 2 (electrode) and any interconnection 3.
  • this first level can be doped superficially if it is not already doped to allow ohmic contact source 1 - drain 2.
  • This doping can be carried out, for example, by a process of the "flash phosphine" type consisting in depositing on the transparent conductor 1 1 of phosphorus in an environment of phosphorus and hydrogen plasma, the diffusion of phosphorus in the conductor 1 1 as well as in the semiconductor material 13 making the ohmic contact source 1 - drain 2 (FIG. 1 b).
  • This process is described in the publication JAPAN DISPLAY'89, page 506.
  • the third step illustrated in FIG. 1 consists in depositing and etching a semiconductor material 13 or a semiconductor multilayer so as to completely cover the first level 1 1, overflowing preferably on either side of the mesas formed by these layers.
  • the fourth step of this first example of implementation of the method according to the present invention consists in depositing and then etching a layer 14 of a dielectric material so that a contact 5 can be established during the fifth step of the process.
  • FIG. 1 d represents a part of an active matrix screen comprising at least part of the direct stage transistors produced according to the method described above. The description of this figure is made from a pixel but can obviously be extended to all of these pixels arranged in a matrix.
  • the layer of transparent conductive material 11 is deposited on the insulating substrate 10, this transparent conductive material possibly being surface doped before or after its etching so as to form the data columns 25 corresponding to the source 1 of transistor 20, and electrodes 26 of pixels.
  • these electrodes 26 have an approximately square shape and are provided with a tab 2 corresponding to the drain 2 of the transistor 20.
  • the semiconductor 13 is deposited then etched and constitutes a mesa joining the source 1 (column 25 ) at drain 2 (pixel electrode 26).
  • the dielectric 14 is then deposited over the entire surface in order to produce the gate insulator and is etched in order to establish the contacts 3 (not shown in the figure).
  • the conductive material 15 is deposited and then etched making the lines 28 and its contacts 3.
  • FIG. 1e represents the electrical diagram in principle of an inverter 40.
  • This comprises two transistors 41 and 42 connected in series between two polarity + V (47) and -V (46).
  • a high signal IN arrives at 44 on the gate of transistor 42, that is turned on.
  • the gate of transistor 41 being connected (43) to the polarity line + V, the latter is on and a low signal OUT comes out at 45.
  • transistor 42 is returned not passing and it is a high signal which leaves at 45 from the inverter 40.
  • FIG. 1 f This inverter 40 produced according to the first embodiment of the method according to the invention is shown in FIG. 1 f.
  • the conductive material 1 1, preferably transparent and surface-treated, is deposited and etched so as to form the sources and drains of the transistors 41 and 42, as well as the connection line 45.
  • the semiconductor 13 is deposited and etched so as to form mesas 29 joining sources and drains.
  • the insulator 14 is then deposited and etched so as to create an opening 5 at the level of the external source and drain of the transistors 41 and 42 respectively.
  • the conductor 15 is deposited and etched making the contacts of gates 44 and 43, as well as the contacts source - line 47 (+ V) and drain - line 46 (-V).
  • This first embodiment of the method according to the invention reveals a constraint which is that the deposits of the layer 13 of the fine semiconductor material 13 and of the dielectric material 14 are not produced during the same vacuum cycle. This can generate a bad interface between these two levels during the etching of the layer 13 of the semiconductor, which can have the consequence of degrading the electrical properties of the transistor. This drawback is avoided in the following embodiments of the method.
  • FIGS. 2a to 2d A second embodiment of the method according to the invention is illustrated by FIGS. 2a to 2d.
  • the first two steps are identical to those of the previous mode and correspond to a first level of mask.
  • the layer 13 of the semiconductor material and a layer 16 of a dielectric material are deposited and etched simultaneously, as shown in FIG. 2b.
  • the fact that the dielectric 16 and the semiconductor 13 are deposited and etched during the same vacuum cycle makes it possible to achieve a good interface between the two layers.
  • the fourth step consists in depositing a second dielectric layer 14 over the entire surface and in etching it so that contact can be established between the conductive layer 15 (deposited during the fifth and last step) corresponding to the grid 22 and the connection 3 and / or in such a way that an opening 6 in the dielectric layer 14 brings the conductive level 15 and the insulating level 16 into contact, on the island consisting of the sources and drains, of the semiconductor 13 and of the insulator 16, the dielectric layer 14 covering only the edges of the etched block formed by the layers 11, 13 and 16. In this case, four masking levels are used.
  • this latter mode allows, without adding additional steps, to solve the problem of bad interface mentioned above, to produce different types of transistors and capacitors whose characteristics can be selected by an appropriate choice of dielectrics 14 and 16 and which correspond to Figures 2c and 2d.
  • a first type of transistor 23 is illustrated in FIG. 2c and uses the two dielectrics 14 and 16 as the gate dielectric. This makes such a transistor not very sensitive to "gate stress": parasitic phenomenon due to amorphous silicon, when the gate is controlled with high voltages, the electrical characteristics of the transistor deteriorate over time.
  • the second type of transistor 24 is illustrated in FIG. 2d and uses only the dielectric 16 as the gate dielectric. This makes it possible to adapt the characteristics of the transistor to lower voltages, this type of transistor being able to be used on the peripheral control electronics. Indeed, the gate insulator being thinner, the current flowing through the transistor is higher.
  • the transistors of the active matrix can be of the first type.
  • the control electronics can use both types of transistors, which makes it possible to adapt it to low-voltage external signals compatible with current technology.
  • the choice of the two insulators 16 and 14 makes it possible to use either only transistors of the first type, or only transistors of the second type, or transistors of the two types mixed.
  • FIG. 2e represents a part of an active matrix screen comprising at least partly transistors 23 and produced according to the second embodiment of the method according to the invention of FIGS. 2a, 2b and 2c.
  • the description of this figure is made from a pixel, but it is obvious that it extends to all the other pixels arranged in a matrix fashion.
  • the layer of transparent conductive material 1 1 is deposited on the insulating substrate 10, this transparent conductive material being able to be doped surface before or after its etching so as to form the columns of data
  • connection 3 can be for example the source or the drain of a transistor of the integrated control electronics, and completely covers the mesa 27 constituted by the semiconductor 13 and the first insulator 16.
  • Such a transistor includes the two insulators 14 and 16 of FIG. 2c as a gate dielectric.
  • FIG. 2f represents in the same way a part of an active matrix produced according to the second embodiment of the method of FIGS. 2a, 2b and 2d, active matrix of which all or part of the transistors comprises the first level of insulator 16 as a gate dielectric (transistor 24 in FIG. 2d).
  • Transistor 24 in FIG. 2d we find the data columns 25 and the electrodes 26 of any shape but having a tab which constitutes the drain 2 of the transistor 24.
  • FIG. 2g represents the inverter 40 of FIG. 1e produced by the second embodiment of the method according to the invention comprising two transistors 41 and 42 of the first type. The explanation given during the description of FIG.
  • the Figure 2h shows the inverter 40 of Figures 1 e and 2g manufactured by the second embodiment of the method according to the invention comprising two transistors 41 and 42 of the second type.
  • the difference compared to the previous figure is the opening 6 etched through the second level of insulation 14.
  • the dielectric 14 is used as passivation of the transistors, of the pixel electrode, as a gate insulator, and as an interconnection dielectric (insulation of two superposed conductive layers).
  • a third embodiment of the method according to the invention comprises the same first and second steps of the preceding modes as shown in FIG. 3a.
  • the third step of this embodiment of the method according to the invention consists in depositing simultaneously a layer 13 of a semiconductor material and a layer 16 of a dielectric material. These first two steps correspond to two levels of masks.
  • the third step consists in passivating the zones 131 and 132 not protected by the dielectric on the sides of the semiconductor.
  • This passivation can be carried out by an oxidation (plasma O, O2.03, N2O), or a nitriding (plasma N, NH3), or a passivation (deposition of planarizing dielectric followed by an aanisotropic etching of this same dielectric).
  • plasma O, O2.03, N2O oxidation
  • a nitriding plasma N, NH3
  • a passivation deposition of planarizing dielectric followed by an aanisotropic etching of this same dielectric.
  • a layer 15 of a conductive material is deposited and then etched, constituting a third level of mask (FIG. 3c).
  • the gate contact 22 - connection 3 is this time provided by the direct contact between the conductor level 15 and the connection 3.
  • This third mode can be completed by a fifth step consisting in etching the layers of dielectric 16 and of the semiconductor material 13 using the conductor 15 as the mask level. Indeed, zones of the semiconductor mesa 13 - insulator 16 can extend on either side of the conductive layer 15 etched (grid) in the plane perpendicular to the plane of the figure, and must be removed according to the desired technology .
  • a sixth step can then consist of passivating by oxidation or nitriding or by depositing a dielectric on the sides of the semiconductor not protected by the dielectric 16.
  • a semiconductor mesa 13 - insulator 16 can be left on the connection 3 in order to isolate it from the conductive level 15.
  • FIG. 3d represents a part of an active matrix produced according to this third embodiment of the method according to the invention described from FIGS. 3a to 3c.
  • An electrode 26 of any shape has a tab 2 forming the drain of the transistor 30.
  • a column 25 provided with a tongue opposite the drain 2 and which forms the source 1 of the transistor 30 .
  • the semiconductor 13 and the dielectric 16 are deposited and etched so as to form the mesas 31 and 32, the mesa 31 forming the semiconductor level of the transistor 30 and the mesa 32 an isolation level. between column 25 and grid 28 deposited and etched during the fourth step of the process.
  • FIG. 3e represents the inverter 40 of FIG. 1 e manufactured according to the third embodiment of the method according to the invention.
  • the transistors 41 and 42 the first conductive level constituting the sources and drains of these transistors as well as the connection 45, the mesas 29 whose flanks were passive consisting of a first semiconductor level 13 and a first level insulator 16, and finally, the metal level 15 forming the gates 43 and 44 of the transistors 41 and 42 as well as the connections 46 and 47.
  • the dielectric 16 deposited in the same vacuum cycle as the semiconductor level 13 allows a good interface between these two levels.
  • the method according to the invention can be implemented on a glass substrate or on an already preprocessed substrate (ground plane, black matrix and insulating level) which allows, for example, to add a storage capacity and to protect the transistor against the light from the back of the screen.
  • a particularly advantageous improvement of the invention consists in depositing and etching a first opaque level directly on the substrate at the start of the process, so that the latter masks the semiconductor channel between the source and the drain of each transistor. direct floor.
  • This first opaque level can be deposited and etched so as to mask in the light the places where the sources, drains and semiconductors constituting the transistors controlling the pixel electrodes are going to be deposited, or leave exposed only the areas comprising the electrodes , thereby improving the contrast of the screen while blocking the photoconductivity of the semiconductor materials used.
  • This level can be made of reflective metal and, if it is conductive, this first etching must be followed by the deposition over the entire surface of the substrate of an insulating level.
  • Such a first opaque level is called "black matrix” and is described in detail in French patent application No. 91 12586 filed by the applicant.
  • Another improvement of the present invention can be to add directly to the substrate at the start of the process, a capacity storage on which the active matrix will be produced.
  • a capacity storage on which the active matrix will be produced is described in detail in French patent application No. 91 12585 filed by the applicant.
  • This storage capacity can be achieved by a transparent conductive layer deposited directly on the entire substrate and covered by a transparent insulating layer. Thus, no new mask level has been added. It can also be opaque and etched so as to only mask the semiconductor areas or to let light pass only over the areas comprising the electrodes, thus playing the role of "black matrix".
  • the substrate 10 is a glass plate
  • the transparent and conductive material 11 can be indium tin oxide (ITO) or tin oxide (SnO2)
  • the material semiconductor 13 a multilayer or monolayer of hydrogenated amorphous silicon (a- Si: H), of polycrystalline or microcrystalline silicon.
  • the dielectric materials 14 and 16 can be silicon dioxide (SiO2), silicon nitride (SiN) or oxynitride.
  • the insulating layer in contact with the semiconductor is a layer of silicon nitride (SiN) and that which is in contact with the conductor, a layer of silicon dioxide (SiO2).
  • the conductive materials 15 can be aluminum, titanium, chromium, molybdenum, tungsten, tantalum, TITO, alloys or multilayers.
  • the present invention applies to the manufacture of thin film transistors with a direct, self-passivating and self-screening stepped structure which can be used for the production of any electronic circuit (signal processing electronics) integrated on a preprocessed or non-preprocessed substrate, or on an amorphous silicon-based glass plate such as those used for photocopying or driving a photodiode array, and more particularly for making flat liquid crystal screens controlled by external or integrated electronics (drivers).
  • signal processing electronics signal processing electronics

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  • Microelectronics & Electronic Packaging (AREA)
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  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

A method for producing direct multilevel thin-film transistors (TFTs) with a small number of mask levels, for forming a contact between a transistor gate and the source or drain of the same or another transistor, and for use in producing flat LCD screens, particularly on screens having integral electronic control circuitry. Said method for producing direct multilevel thin-film transistors (20; 23; 24) having four mask levels comprises the steps of depositing and etching a first conductive level (11) on an insulating substrate (10) to form a source (1) and a drain (2), depositing and etching a semiconductor level (13) alone or followed by a first insulating level (16) joining the source (1) and the drain (2), depositing and etching a second insulating level (14), and depositing and etching a second conductive level (15) constituting the gate (22) of the transistor (20, 23). A further method of producing direct multilevel thin-film transistors (30) with three mask levels comprises the steps of depositing and etching a first conductive level (11) on an insulating substrate (10) to form a source and a drain (1, 2), depositing and a drain (1, 2), depositing a second semiconductor level (13) followed by an insulation level (16) and etching the assembly to join source (1) and drain (2), oxidation, nitriding or passivation of the sides (131, 132) of the semiconductor levels (13), and depositing and etching a conductive level (15).

Description

PROCEDE DE FABRICATION DE TRANSISTORS A COUCHES MINCES ETAGES DIRECTS METHOD FOR MANUFACTURING DIRECT STAGE THIN FILM TRANSISTORS
La présente invention concerne un procédé de fabrication de transistors à couche mince (TFT), à structure étagée directe et à faible nombre de niveaux de masque, permettant de réaliser un contact entre la grille d'un transistor et la source ou le drain du même ou d'un autre transistor, et pouvant être utilisés pour la fabrication d'écrans plats à cristaux liquides, en particulier sur les écrans avec électronique de commande intégrée.The present invention relates to a method for manufacturing thin film transistors (TFT), with a direct stepped structure and a low number of mask levels, making it possible to make contact between the gate of a transistor and the source or the drain of the same. or another transistor, and which can be used for the manufacture of flat liquid crystal screens, in particular on screens with integrated control electronics.
Un écran à cristaux liquides est constitué d'un certains nombre de cellules à cristal liquide disposées de manière matricielle et reliées par des lignes et des colonnes de connexion à l'électronique de commande. Une première plaque support est constituée d'un substrat contenant un premier jeu d'électrodes, les composants de commande de ces électrodes, ainsi que les lignes et les colonnes d'adressage (matrice active). Le cristal liquide est contenu entre cette plaque et une seconde plaque support constituant la contre-électrode. Chaque pixel (pour picture élément en langue Anglaise) ainsi formée fonctionne en valve optique. La modification locale de la transmission ou de la réflexion de la lumière est obtenue en appliquant à partir de l'électronique de commande une tension entre un contact d'accès de la plaque et un contact de la contre plaque. Cette tension fait naître un champ électrique entre les électrodes en regard et active le volume de cristal liquide situé entre les deux électrodes qui modifie plus ou moins les caractéristiques de la lumière qui le traverse.A liquid crystal display is made up of a number of liquid crystal cells arranged in a matrix and connected by lines and columns for connection to the control electronics. A first support plate consists of a substrate containing a first set of electrodes, the control components of these electrodes, as well as the addressing lines and columns (active matrix). The liquid crystal is contained between this plate and a second support plate constituting the counter-electrode. Each pixel (for picture element in English language) thus formed functions as an optical valve. The local modification of the transmission or the reflection of the light is obtained by applying from the control electronics a voltage between an access contact of the plate and a contact of the counter plate. This voltage gives rise to an electric field between the facing electrodes and activates the volume of liquid crystal located between the two electrodes which more or less changes the characteristics of the light passing through it.
Dans le cas d'écrans à matrice active, un élément actif à deux (diode) ou trois terminaisons (transistor) est associé à chaque pixel et à chaque intersection ligne - colonne. La fabrication de tels écrans peut faire appel à des procédés de fabrication de matrices actives constituées de transistors en couche mince. Ces transistors peuvent avoir une structure étagée directe, c'est à dire que, par rapport au substrat, la grille est au dessus des source et drain, ou étagée inverse, c'est à dire que la grille est située au dessous des source et drain.In the case of active matrix screens, an active element with two (diode) or three terminations (transistor) is associated with each pixel and with each row - column intersection. The manufacture of such screens can call upon methods of manufacturing active matrices made up of thin-film transistors. These transistors can have a direct staged structure, that is to say that, with respect to the substrate, the grid is above the source and drain, or reverse staged, that is to say that the grid is located below the source and drain.
Une structure étagée directe est décrite dans la demande de brevet Européen 82 783 "procédé de fabrication de transistors en couches minces en Silicium sur substrat isolant" (F.Morin et al), ainsi que dans un article de JAPAN DISPLAY '86 "A 6" Diagonal Active Matrix Addressed LCD for MINITEL Application" des mêmes auteurs. La technologie décrite dans ces documents est très économique puisqu'elle permet de réaliser des transistors à couches minces avec seulement deux niveaux de masques, en fabricant les colonnes de données en même temps que les électrodes. D'autre part, un article de Y.Ugai et al "A 7.23-in. -Diagonal Color LCD Addresssed by a-Si TFTs" (SID 84 DIGEST, page 308) propose la fabrication d'un transistor étage direct réalisé avec trois niveaux de masques.A direct stepped structure is described in European patent application 82 783 "process for manufacturing transistors in thin silicon layers on insulating substrate "(F. Morin et al), as well as in an article by JAPAN DISPLAY '86" A 6 "Diagonal Active Matrix Addressed LCD for MINITEL Application" by the same authors. The technology described in these documents is very economical since it makes it possible to produce thin film transistors with only two levels of masks, by manufacturing the data columns at the same time as the electrodes. On the other hand, an article by Y. Ugai et al "A 7.23-in. -Diagonal Color LCD Addresssed by a-Si TFTs" (SID 84 DIGEST, page 308) proposes the manufacture of a direct stage transistor made with three mask levels.
Cependant, ces technologies comportent un certain nombre d'inconvénients dont le principal provient de la photoconductivité du silicium. En effet, ces transistors sont sensibles à la lumière par le dessus, c'est à dire par leurs bords, et la technologie "dar mask" (grille recouvrant totalement le matériau semiconducteur) est impossible. Ces transistors sont aussi sensibles à la lumière par le dessous, c'est à dire par le canal du transistor en contact direct avec le substrat lorsque celui- ci est transparent. D'autre part, il est nécessaire d'introduire dans le procédé de fabrication de ces transistors, une étape supplémentaire de passivation afin d'éviter l'affleurement du matériau semiconducteur en fin de procédé. Enfin, une limitation de taille est qu'il n'y a pas de contact possible grille - source.However, these technologies have a number of drawbacks, the main one of which comes from the photoconductivity of silicon. Indeed, these transistors are sensitive to light from above, ie by their edges, and the "dar mask" technology (grid completely covering the semiconductor material) is impossible. These transistors are also sensitive to light from below, that is to say through the transistor channel in direct contact with the substrate when the latter is transparent. On the other hand, it is necessary to introduce into the manufacturing process of these transistors, an additional passivation step in order to avoid the outcrop of the semiconductor material at the end of the process. Finally, a size limitation is that there is no possible grid-source contact.
Des solutions ont été proposées afin de remédier au problème de la photoconductivité par le bas comme celles décrites dans les brevets HOSIDEN EP 186036 et EP 179915, ainsi que dans un article de T.Wada et al "1280x800 Color Pixel 15 inche Full Color Active Matrix LCD" (EURODISPLAY'90 The Tenth International Display Research Conférence", page 370). Ces solutions nécessitent au moins quatre niveaux de masques et ne permettent pas de contact grille - source ou drain. D'autre part, ces solutions ne proposent, pour remédier au problème de la photoconductivité par le haut, que de déposer et graver un masque opaque sur la contre électrode.Solutions have been proposed in order to remedy the problem of photoconductivity from below, such as those described in the HOSIDEN patents EP 186036 and EP 179915, as well as in an article by T. Wada et al "1280x800 Color Pixel 15 inche Full Color Active Matrix LCD "(EURODISPLAY'90 The Tenth International Display Research Conference", page 370). These solutions require at least four levels of masks and do not allow grid-source or drain contact. On the other hand, these solutions do not offer, for remedy the problem of photoconductivity from above, than depositing and etching an opaque mask on the counter electrode.
La présente invention permet de s'affranchir de ces inconvénients grâce à un procédé de fabrication économique à trois ou quatre niveaux de masques. En effet, cette invention concerne des procédés de fabrication de transistors à couches minces étages directs à quatre niveaux de masques pouvant être utilisés dans un écran à cristaux liquide, il est caractérisé en ce qu'il comporte les étapes suivantes: . dépôt et gravure d'un premier niveau conducteur sur un substrat isolant de manière à former une source et un drain,The present invention overcomes these drawbacks through an economical manufacturing process with three or four levels of masks. Indeed, this invention relates to methods of manufacturing thin-film transistors direct stages with four levels of masks that can be used in a liquid crystal screen, it is characterized in that it comprises the following steps:. deposition and etching of a first conductive level on an insulating substrate so as to form a source and a drain,
. dépôt et gravure d'un niveau semiconducteur seul ou avec un premier niveau isolant joignant les source et drain,. deposition and etching of a semiconductor level alone or with a first insulating level joining the source and drain,
. dépôt et gravure d'un second niveau isolant . dépôt et gravure d'un second niveau conducteur réalisant la grille du transistor.. deposition and etching of a second insulating level. deposition and etching of a second conductive level producing the gate of the transistor.
La présente invention concerne aussi un procédé de fabrication de transistors à couches minces étages directs à trois niveaux de masques pouvant être utilisés dans un écran à cristaux liquides dont les étapes sont les suivantes:The present invention also relates to a method of manufacturing thin-film transistors direct stages with three levels of masks which can be used in a liquid crystal screen, the steps of which are as follows:
. dépôt et gravure d'un premier niveau conducteur sur un substrat isolant de manière à former une source et un drain,. deposition and etching of a first conductive level on an insulating substrate so as to form a source and a drain,
. dépôt d'un niveau semiconducteur et d'un niveau isolant et gravure de l'ensemble joignant les source et drain, . oxydation, nitruration ou passivation des flancs du niveau semiconducteur,. deposition of a semiconductor level and an insulating level and etching of the assembly joining the source and drain,. oxidation, nitriding or passivation of the flanks of the semiconductor level,
. dépôt et gravure d'un niveau conducteur réalisant la grille du transistor.. deposition and etching of a conductive level producing the gate of the transistor.
Ce dernier procédé pouvant être suivi d'une étape de gravure de la bicouche niveau semiconducteur - niveau isolant en utilisant le niveau gravé conducteur comme niveau de masque, et d'une étape d'oxydation, de nitruration ou de passivation des flancs gravés du niveau semiconducteur.This latter process can be followed by a step of etching the bilayer semiconductor level - insulating level using the etched conductive level as mask level, and a step of oxidation, nitriding or passivation of the etched sides of the level. semiconductor.
La présente invention concerne aussi un procédé de fabrication d'un écran à cristaux liquides dont les transistors de la matrice active sont fabriqués par de tels procédés.The present invention also relates to a method for manufacturing a liquid crystal screen, the active matrix transistors of which are manufactured by such methods.
Un autre objet de la présente invention est un circuit électronique réalisé sur un substrat isolant par un des mode de mise en oeuvre du procédé selon l'invention. Le procédé selon l'invention permet de passiver les transistors au cours du procédé, de les rendre insensibles à la lumière venant du dessus, le dessous pouvant être protégé par un masque opaque ("black matrix" en langue anglaise) comme cela est décrit dans la demande de brevet Français n °91 12586 déposée par la demanderesse.Another object of the present invention is an electronic circuit produced on an insulating substrate by one of the mode of implementation of the method according to the invention. The method according to the invention makes it possible to passivate the transistors during the process, to make them insensitive to light coming from above, the bottom being able to be protected by an opaque mask ("black matrix "in English) as described in French patent application No. 91 12586 filed by the applicant.
Le procédé selon l'invention permet la fabrication de circuits intégrés sur le même substrat que la matrice active grâce à la possibilité qu'il offre de pouvoir connecter les grilles des transistors à des sources ou drains du même ou d'autres transistors, et ainsi être utilisé dans une technologie "drivers intégrés". Il est d'autre part possible de fabriquer par ce procédé différents types de transistors et capacités sans pour cela ajouter de niveaux de masques supplémentaires.The method according to the invention allows the fabrication of integrated circuits on the same substrate as the active matrix thanks to the possibility that it offers of being able to connect the gates of the transistors to sources or drains of the same or other transistors, and thus be used in an "integrated drivers" technology. It is also possible to manufacture by this process different types of transistors and capacitances without adding additional levels of masks.
La présente invention sera mieux comprise et des avantages supplémentaires apparaîtront à la lecture de la description qui va suivre illustrée par les figures suivantes:The present invention will be better understood and additional advantages will appear on reading the description which follows, illustrated by the following figures:
. les figures 1 a à 1 c représentent un premier mode de mise en oeuvre du procédé selon l'invention,. FIGS. 1 a to 1 c represent a first embodiment of the method according to the invention,
. la figure 1 d représente une vue planaire d'une partie d'un écran à matrice active réalisé selon le procédé des figures 1 a à 1 c,. FIG. 1 d represents a planar view of part of an active matrix screen produced according to the method of FIGS. 1 a to 1 c,
. la figure 1e représente le schéma électrique de principe d'un inverseur, . la figure 1 f représente l'inverseur de la figurele fabriqué par le procédé des figures 1 a à 1 c,. FIG. 1e represents the electrical diagram of the principle of an inverter,. FIG. 1 f represents the reverser of the figure produced by the method of FIGS. 1 a to 1 c,
. les figures 2a à 2d représentent un second mode de mise en oeuvre du procédé selon l'invention,. FIGS. 2a to 2d show a second embodiment of the method according to the invention,
. la figure 2e représente une vue planaire d'une partie d'un écran à matrice active réalisé selon le procédé des figures 2a à 2c,. FIG. 2e represents a planar view of part of an active matrix screen produced according to the method of FIGS. 2a to 2c,
. la figure 2f représente une vue planaire d'une partie d'un écran à matrice active réalisé selon le procédé des figures 2a, 2b et 2d,. FIG. 2f represents a planar view of part of an active matrix screen produced according to the method of FIGS. 2a, 2b and 2d,
. la figure 2g représente l'inverseur de la figure 1 e fabriqué par le procédé des figures 2a à 2c, . la figure 2h représente l'inverseur de la figure 1 e fabriqué par le procédé des figures 2a, 2b et 2d,. Figure 2g shows the inverter of Figure 1 e manufactured by the method of Figures 2a to 2c,. FIG. 2h represents the inverter of FIG. 1 e manufactured by the method of FIGS. 2a, 2b and 2d,
. les figures 3a à 3c représente un troisième mode de mise en oeuvre du procédé selon l'invention,. FIGS. 3a to 3c represent a third embodiment of the method according to the invention,
. la figure 3d représente une vue planaire d'une partie d'un écran à matrice active réalisé selon le procédé des figures 3a à 3c,. FIG. 3d represents a planar view of part of an active matrix screen produced according to the method of FIGS. 3a to 3c,
. et la figure 3e représente l'inverseur de la figure 1 e fabriqué par le procédé des figures 3a à 3c. Dans les différentes figures décrites ci-dessous, les mêmes éléments et les mêmes matériaux ont gardé la même référence.. and Figure 3e shows the inverter of Figure 1 e manufactured by the method of Figures 3a to 3c. In the different figures described below, the same elements and the same materials were kept the same ref erence.
La figure 1 a représente un substrat 10 isolant et pouvant être transparent, sur lequel une couche 1 1 d'un matériau conducteur transparent ou d'une bicouche conducteur transparent - semiconducteur dopé est déposée et gravée lors d'une première étape réalisant, par exemple, les source 1 (colonne de données), drain 2 (électrode) et une interconnexion quelconque 3. Au cours d'une seconde étape, ce premier niveau peut être dopé superficiellement s'il ne l'est pas déjà pour permettre un contact ohmique source 1 - drain 2. Ce dopage peut être réalisé, par exemple, par un procédé du type "flash phosphine" consistant à déposer sur le conducteur transparent 1 1 du phosphore dans un environnement de plasma phosphore et hydrogène, la diffusion du phosphore dans le conducteur 1 1 ainsi que dans le matériau semiconducteur 13 réalisant le contact ohmique source 1 - drain 2 (figure 1 b). Ce procédé est décrit dans la publication JAPAN DISPLAY'89, page 506. La troisième étape illustrée par la figure 1 consiste à déposer et à graver un matériau semiconducteur 13 ou une multicouche semiconductrice de manière à recouvrir totalement le premier niveau 1 1 , en débordant de préférence de part et d'autre des mesas constituées par ces couches. La quatrième étape de ce premier exemple de mise en oeuvre du procédé selon la présente invention consiste à déposer puis à graver une couche 14 d'un matériau diélectrique de manière à ce qu'un contact 5 puisse être établi au cours de la cinquième étape du procédé.Figure 1a shows an insulating substrate 10 and can be transparent, on which a layer 1 1 of a transparent conductive material or a transparent conductive bilayer - doped semiconductor is deposited and etched during a first step performing, for example , source 1 (data column), drain 2 (electrode) and any interconnection 3. During a second step, this first level can be doped superficially if it is not already doped to allow ohmic contact source 1 - drain 2. This doping can be carried out, for example, by a process of the "flash phosphine" type consisting in depositing on the transparent conductor 1 1 of phosphorus in an environment of phosphorus and hydrogen plasma, the diffusion of phosphorus in the conductor 1 1 as well as in the semiconductor material 13 making the ohmic contact source 1 - drain 2 (FIG. 1 b). This process is described in the publication JAPAN DISPLAY'89, page 506. The third step illustrated in FIG. 1 consists in depositing and etching a semiconductor material 13 or a semiconductor multilayer so as to completely cover the first level 1 1, overflowing preferably on either side of the mesas formed by these layers. The fourth step of this first example of implementation of the method according to the present invention consists in depositing and then etching a layer 14 of a dielectric material so that a contact 5 can be established during the fifth step of the process.
Au cours de cette cinquième et dernière étape, une couche 15 d'un matériau conducteur est déposée puis gravée afin de réaliser la grille 21 du transistor étage direct 20 et d'établir un contact entre cette grille 21 et la connexion 3. Cela est représenté sur la figure 2c et correspond à quatre niveaux de masque. Cette connection 3 peut être par exemple une connection interne entre grille et source. Ce type de transistor ainsi obtenu peut être utilisé de préférence dans la réalisation d'écrans plats munis d'une électronique de commande intégrée. La figure 1 d représente une partie d'un écran à matrice active comportant au moins en partie des transistors 20 étages directs réalisés selon le procédé décrit ci-dessus. La description de cette figure est faite à partir d'un pixel mais peut être bien évidemment étendue à l'ensemble de ces pixels arrangés de façon matricielle.During this fifth and last step, a layer 15 of a conductive material is deposited and then etched in order to produce the gate 21 of the direct stage transistor 20 and to establish contact between this gate 21 and the connection 3. This is shown in Figure 2c and corresponds to four mask levels. This connection 3 can for example be an internal connection between grid and source. This type of transistor thus obtained can preferably be used in the production of flat screens fitted with integrated control electronics. FIG. 1 d represents a part of an active matrix screen comprising at least part of the direct stage transistors produced according to the method described above. The description of this figure is made from a pixel but can obviously be extended to all of these pixels arranged in a matrix.
Au cours de la première étape du procédé, la couche de matériau conducteur transparent 1 1 est déposée sur le substrat isolant 10, ce matériau conducteur transparent pouvant être dopé superficiellement avant ou après sa gravure de manière à former les colonnes de données 25 correspondant à la source 1 du transistor 20, et les électrodes 26 de pixels. Dans l'exemple de cette figure, ces électrodes 26 ont une forme approximativement carrée et sont munies d'une patte 2 correspondant au drain 2 du transistor 20. Le semiconducteur 13 est déposé puis gravé et constitue une mésa joignant la source 1 (colonne 25) au drain 2 (électrode de pixel 26). Le diélectrique 14 est ensuite déposé sur toute la surface afin de réaliser l'isolant de grille et est gravé afin d'établir les contacts 3 (non représentés sur la figure). Enfin, le matériau conducteur 15 est déposé puis gravé réalisant les lignes 28 et ses contacts 3.During the first step of the method, the layer of transparent conductive material 11 is deposited on the insulating substrate 10, this transparent conductive material possibly being surface doped before or after its etching so as to form the data columns 25 corresponding to the source 1 of transistor 20, and electrodes 26 of pixels. In the example of this figure, these electrodes 26 have an approximately square shape and are provided with a tab 2 corresponding to the drain 2 of the transistor 20. The semiconductor 13 is deposited then etched and constitutes a mesa joining the source 1 (column 25 ) at drain 2 (pixel electrode 26). The dielectric 14 is then deposited over the entire surface in order to produce the gate insulator and is etched in order to establish the contacts 3 (not shown in the figure). Finally, the conductive material 15 is deposited and then etched making the lines 28 and its contacts 3.
La figure 1e représente le shéma électrique de principe d'un inverseur 40. Celui-ci comporte deux transistors 41 et 42 connectés en série entre deux polarité + V (47) et -V (46). Lorsqu'un signal haut IN arrive en 44 sur la grille du transistor 42, celui est rendu passant. La grille du transistor 41 étant reliée (43) à la ligne de polarité + V, celui-ci est passant et un signal bas OUT sort en 45. A l'inverse lorsqu'un signal bas entre en 44, le transistor 42 est rendu non passant et c'est un signal haut qui sort en 45 de l'inverseur 40.FIG. 1e represents the electrical diagram in principle of an inverter 40. This comprises two transistors 41 and 42 connected in series between two polarity + V (47) and -V (46). When a high signal IN arrives at 44 on the gate of transistor 42, that is turned on. The gate of transistor 41 being connected (43) to the polarity line + V, the latter is on and a low signal OUT comes out at 45. Conversely when a low signal enters at 44, transistor 42 is returned not passing and it is a high signal which leaves at 45 from the inverter 40.
Cet inverseur 40 réalisé selon le premier mode de mise en oeuvre du procédé selon l'invention est représenté sur la figure 1 f. Le matériau conducteur 1 1 , de préférence transparent et traité superficiellement, est déposé et gravé de manière à former les sources et drains des transistors 41 et 42, ainsi que la ligne de connexion 45. Le semiconducteur 13 est déposé et gravé de manière à former les mesas 29 joignant sources et drains. L'isolant 14 est ensuite déposé et gravé de manière à créer une ouverture 5 au niveau des source et drain externes respectivement des transistors 41 et 42. Le conducteur 15 est déposé et gravé réalisant les contacts de grilles 44 et 43, ainsi que les contacts source - ligne 47 ( + V) et drain - ligne 46 (-V). Ce premier mode de mise en oeuvre du procédé selon l'invention fait apparaître une contrainte qui est que les dépôts de la couche 13 du matériau semiconducteur fin 13 et du matériau diélectrique 14 ne sont pas réalisés au cours du même cycle de vide. Cela peut générer une mauvaise interface entre ces deux niveaux lors de la gravure de la couche 13 du semiconducteur, qui peut avoir pour conséquence la dégradation des propriétés électriques du transistor. Cet inconvénient est évité dans les modes de mise en oeuvre du procédé suivants.This inverter 40 produced according to the first embodiment of the method according to the invention is shown in FIG. 1 f. The conductive material 1 1, preferably transparent and surface-treated, is deposited and etched so as to form the sources and drains of the transistors 41 and 42, as well as the connection line 45. The semiconductor 13 is deposited and etched so as to form mesas 29 joining sources and drains. The insulator 14 is then deposited and etched so as to create an opening 5 at the level of the external source and drain of the transistors 41 and 42 respectively. The conductor 15 is deposited and etched making the contacts of gates 44 and 43, as well as the contacts source - line 47 (+ V) and drain - line 46 (-V). This first embodiment of the method according to the invention reveals a constraint which is that the deposits of the layer 13 of the fine semiconductor material 13 and of the dielectric material 14 are not produced during the same vacuum cycle. This can generate a bad interface between these two levels during the etching of the layer 13 of the semiconductor, which can have the consequence of degrading the electrical properties of the transistor. This drawback is avoided in the following embodiments of the method.
Un second mode de mise en oeuvre du procédé selon l'invention est illustré par les figures 2a à 2d.A second embodiment of the method according to the invention is illustrated by FIGS. 2a to 2d.
Les deux premières étapes (figure 2a et 2b) sont identiques à celles du précédent mode et correspondent à un premier niveau de masque. Au cours de la troisième étape, la couche 13 du matériau semiconducteur et une couche 16 d'un matériau diélectrique sont déposées et gravées simultanément, comme cela est représenté sur la figure 2b. Le fait que le diélectrique 16 et le semiconducteur 13 soient déposés et gravés au cours du même cycle de vide permet de réaliser une bonne interface entre les deux couches.The first two steps (Figure 2a and 2b) are identical to those of the previous mode and correspond to a first level of mask. During the third step, the layer 13 of the semiconductor material and a layer 16 of a dielectric material are deposited and etched simultaneously, as shown in FIG. 2b. The fact that the dielectric 16 and the semiconductor 13 are deposited and etched during the same vacuum cycle makes it possible to achieve a good interface between the two layers.
La quatrième étape consiste à déposer une seconde couche diélectrique 14 sur toute la surface et à la graver de manière à ce que puisse être établi un contact entre la couche conductrice 15 (déposée lors de la cinquième et dernière étape) correspondant à la grille 22 et la connexion 3 et/ou de manière à ce qu'une ouverture 6 dans la couche de diélectique 14 mette en contact le niveau conducteur 15 et le niveau isolant 16, sur l'îlot constitué des sources et drains, du semiconducteur 13 et de l'isolant 16, la couche 14 diélectrique ne recouvrant plus que les bords du blocs gravé constitué par les couches 1 1 , 13 et 16. Dans ce cas, quatre niveaux de masquage sont utilisés.The fourth step consists in depositing a second dielectric layer 14 over the entire surface and in etching it so that contact can be established between the conductive layer 15 (deposited during the fifth and last step) corresponding to the grid 22 and the connection 3 and / or in such a way that an opening 6 in the dielectric layer 14 brings the conductive level 15 and the insulating level 16 into contact, on the island consisting of the sources and drains, of the semiconductor 13 and of the insulator 16, the dielectric layer 14 covering only the edges of the etched block formed by the layers 11, 13 and 16. In this case, four masking levels are used.
Ainsi, ce dernier mode permet, sans rajouter d'étape supplémentaires, de résoudre le problème de mauvaise interface évoqué plus haut , de réaliser différents types de transistors et de capacités dont les caractéristiques peuvent être sélectionnées par un choix approprié des diélectriques 14 et 16 et qui correspondent au figures 2c et 2d. Un premier type de transistor 23 est illustré par la figure 2c et utilise les deux diélectriques 14 et 16 comme diélectrique de grille. Cela rend un tel transistor peu sensible au "stress de grille": phénomène parasite dû au silicium amorphe, lorsque la grille est commandée avec des hautes tensions, les caractéristiques électriques du transistor se dégradent au cours du temps.Thus, this latter mode allows, without adding additional steps, to solve the problem of bad interface mentioned above, to produce different types of transistors and capacitors whose characteristics can be selected by an appropriate choice of dielectrics 14 and 16 and which correspond to Figures 2c and 2d. A first type of transistor 23 is illustrated in FIG. 2c and uses the two dielectrics 14 and 16 as the gate dielectric. This makes such a transistor not very sensitive to "gate stress": parasitic phenomenon due to amorphous silicon, when the gate is controlled with high voltages, the electrical characteristics of the transistor deteriorate over time.
Le second type de transistor 24 est illustré par la figure 2d et utilise uniquement le diélectrique 16 comme diélectrique de grille. Cela permet d'adapter les caratéristiques du transistor à des tensions plus faibles, ce type de transistor pouvant être utilisé sur l'électronique de commande périphérique. En effet, l'isolant de grille étant plus mince, le courant qui traverse le transistor est plus élevé.The second type of transistor 24 is illustrated in FIG. 2d and uses only the dielectric 16 as the gate dielectric. This makes it possible to adapt the characteristics of the transistor to lower voltages, this type of transistor being able to be used on the peripheral control electronics. Indeed, the gate insulator being thinner, the current flowing through the transistor is higher.
Dans le cas d'une électronique intégrée, les transistors de la matrice active peuvent être du premier type. L'électronique de commande peut utiliser les deux types de transistors, ce qui permet de l'adapter à des signaux externes basse tension compatibles avec la technologie actuelle. De façon générale, le choix des deux isolants 16 et 14 permet d'utiliser, soit uniquement des transistors du premier type, soit uniquement des transistors du second type, soit des transistors des deux types mélangés.In the case of integrated electronics, the transistors of the active matrix can be of the first type. The control electronics can use both types of transistors, which makes it possible to adapt it to low-voltage external signals compatible with current technology. In general, the choice of the two insulators 16 and 14 makes it possible to use either only transistors of the first type, or only transistors of the second type, or transistors of the two types mixed.
De la même manière, trois types différents de capacités peuvent être réalisés dans ce même procédé de fabrication en utilisant comme diélectrique, soit la couche 16, soit la couche 14, soit les deux à la fois.In the same way, three different types of capacitors can be produced in this same manufacturing process by using either layer 16 or layer 14 or both at the same time as a dielectric.
D'autre part, un tel procédé permet un bon rendement de fabrication si les matériaux diélectriques 14 et 16 sont différents, les défauts éventuels de l'un ne se transmettant pas à l'autre.On the other hand, such a method allows a good manufacturing yield if the dielectric materials 14 and 16 are different, the possible defects of one not being transmitted to the other.
La figure 2e représente une partie d'un écran à matrice active comportant au moins en partie des transistors 23 et réalisée selon le second mode de mise en oeuvre du procédé selon l'invention des figures 2a, 2b et 2c. La description de cette figure est faite à partir d'un pixel, mais il est bien évident qu'elle s'étend à tous les autres pixels arrangés de façon matricielle.FIG. 2e represents a part of an active matrix screen comprising at least partly transistors 23 and produced according to the second embodiment of the method according to the invention of FIGS. 2a, 2b and 2c. The description of this figure is made from a pixel, but it is obvious that it extends to all the other pixels arranged in a matrix fashion.
Au cours de la première étape du procédé, la couche de matériau conducteur transparent 1 1 est déposée sur le substrat isolant 10, ce matériau conducteur transparent pouvant être dopé superficiellement avant ou après sa gravure de manière à former les colonnes de donnéesDuring the first step of the method, the layer of transparent conductive material 1 1 is deposited on the insulating substrate 10, this transparent conductive material being able to be doped surface before or after its etching so as to form the columns of data
25 correspondant à la source 1 du transistor 23, et les électrodes 26 de pixels. Dans l'exemple de cette figure, ces électrodes 26 ont une forme approximativement carrée et sont munies d'une patte 2 correspondant au drain 2 du transistor 23. Le semiconducteur 13 et le premier diélectrique 16 ont été déposés pendant le même cycle de vide et gravés ensemble de manière à former une mesa 27 joignant la colonne 25 à l'électrode 26, réalisant respectivement la source 1 et le drain 2 du transistor 23. La seconde couche d'isolant 16 déposée sur toute la surface et gravée de manière à créer le contact 5 de la figure 2c entre une connexion 3 quelconque et la grille 22 du transistor 23, n'est pas représentée sur la figure, de même que n'est pas représentée la connexion 3. La ligne d'adressage 28 est obtenue par le dépôt et la gravure lors de la cinquième étape du second mode de mise en oeuvre du procédé des figures 2a, 2b et 2c. Elle peut être en contact avec la connexion 3 qui peut être par exemple la source ou le drain d'un transistor de l'électronique de commande intégrée, et recouvre totalement la mesa 27 constituée par le semiconducteur 13 et le premier isolant 16.25 corresponding to the source 1 of the transistor 23, and the electrodes 26 of pixels. In the example of this figure, these electrodes 26 have an approximately square shape and are provided with a tab 2 corresponding to the drain 2 of the transistor 23. The semiconductor 13 and the first dielectric 16 were deposited during the same vacuum cycle and etched together so as to form a mesa 27 joining the column 25 to the electrode 26, respectively producing the source 1 and the drain 2 of the transistor 23. The second layer of insulator 16 deposited over the entire surface and etched so as to create the contact 5 in FIG. 2c between any connection 3 and the gate 22 of the transistor 23, is not shown in the figure, just as the connection 3 is not shown. The address line 28 is obtained by depositing and etching during the fifth step of the second embodiment of the method of FIGS. 2a, 2b and 2c. It can be in contact with connection 3 which can be for example the source or the drain of a transistor of the integrated control electronics, and completely covers the mesa 27 constituted by the semiconductor 13 and the first insulator 16.
Un tel transistor comporte les deux isolants 14 et 16 de la figure 2c comme diélectrique de grille. La figure 2f représente de la même manière une partie d'une matrice active réalisée selon le second mode de mise en oeuvre du procédé des figures 2a, 2b et 2d, matrice active dont tout ou partie des transistors comporte le premier niveau d'isolant 16 comme diélectrique de grille (transistor 24 de la figure 2d). On retrouve les colonnes de données 25 et les électrodes 26 de formes quelconques mais comportant une patte qui constitue le drain 2 du transistor 24. La différence avec le dispositif de la figure précédente est qu'au moment de la quatrième étape du procédé, le second niveau isolant 14 a été gravé de manière à, en plus de créer un contact entre la ligne d'adressage 28 correspondant à la grille 22 du transistor 24 et une connexion 3 (non représentée sur la figure), ce que le premier isolant 16 forme à lui seul le diélectrique de grille. Cette surface 6 ainsi creusée dans le second isolant 14 est de préférence inférieure à la surface 29 occupée par le semiconducteur 13 et le premier isolant 16. La figure 2g représente l'inverseur 40 de la figure 1e fabriqué par le second mode de mise en oeuvre du procédé selon l'invention comportant deux transistors 41 et 42 du premier type. L'explication donnée lors de la description de la figure 1 e reste valable avec la différence que les mesas 29 sont constituées non plus d'un niveau semiconducteur 13, mais d'un niveau semiconducteur 13 gravé en même temps qu'un premier niveau isolant 16. La figure 2h représente l'inverseur 40 des figures 1 e et 2g fabriqué par le second mode de mise en oeuvre du procédé selon l'invention comportant deux transistors 41 et 42 du second type. La différence par rapport à la figure précédente est l'ouverture 6 gravée au travers du second niveau d'isolant 14. Ainsi, ont été réalisés deux transistors de différents types pouvant cohabiter sur un même circuit, étant fabriqués au cours du même procédé sans ajouter de niveau de masque supplémentaires, la grille de ces transistors pouvant être reliée à une connection sur le même circuit comme par exemple à la source ou au drain d'un transistor de l'électronique de commande périphérique intégrée à l'écran.Such a transistor includes the two insulators 14 and 16 of FIG. 2c as a gate dielectric. FIG. 2f represents in the same way a part of an active matrix produced according to the second embodiment of the method of FIGS. 2a, 2b and 2d, active matrix of which all or part of the transistors comprises the first level of insulator 16 as a gate dielectric (transistor 24 in FIG. 2d). We find the data columns 25 and the electrodes 26 of any shape but having a tab which constitutes the drain 2 of the transistor 24. The difference with the device of the previous figure is that at the time of the fourth step of the process, the second insulator level 14 has been etched so that, in addition to creating contact between the address line 28 corresponding to the gate 22 of the transistor 24 and a connection 3 (not shown in the figure), what the first insulator 16 forms the gate dielectric alone. This surface 6 thus hollowed out in the second insulator 14 is preferably less than the surface 29 occupied by the semiconductor 13 and the first insulator 16. FIG. 2g represents the inverter 40 of FIG. 1e produced by the second embodiment of the method according to the invention comprising two transistors 41 and 42 of the first type. The explanation given during the description of FIG. 1 e remains valid with the difference that the mesas 29 are no longer made up of a semiconductor level 13, but of a semiconductor level 13 etched at the same time as a first insulating level 16. The Figure 2h shows the inverter 40 of Figures 1 e and 2g manufactured by the second embodiment of the method according to the invention comprising two transistors 41 and 42 of the second type. The difference compared to the previous figure is the opening 6 etched through the second level of insulation 14. Thus, two transistors of different types have been produced which can coexist on the same circuit, being manufactured during the same process without adding additional mask level, the gate of these transistors can be connected to a connection on the same circuit as for example at the source or the drain of a transistor of the peripheral control electronics integrated into the screen.
De plus, dans le cas où il ne doit pas y avoir de connexion entre la grille 22 et la connexion 3 (simple croisement de deux lignes), l'une ou l'autre des épaisseurs, ou les deux à la fois, peuvent être choisie pour isoler l'un par rapport à l'autre ces conducteurs. Le diélectrique 14 est utilisé comme passivation des transistors, de l'électrode pixel, comme isolant de grille, et comme diélectrique d'interconnection (isolation de deux couches conductrices superposées).In addition, in the case where there must be no connection between the grid 22 and the connection 3 (simple crossing of two lines), either or both of the thicknesses, or both, can be chosen to isolate one from the other these conductors. The dielectric 14 is used as passivation of the transistors, of the pixel electrode, as a gate insulator, and as an interconnection dielectric (insulation of two superposed conductive layers).
Un troisième mode de mise en oeuvre du procédé selon l'invention comporte les mêmes première et seconde étapes des modes précédents comme représenté sur la figure 3a. La troisième étape de ce mode de mise en oeuvre du procédé selon l'invention consiste à déposer simultanément une couche 13 d'un matériau semiconducteur et une couche 16 d'un matériau diélectrique. Ces deux premières étapes correspondent à deux niveaux de masques.A third embodiment of the method according to the invention comprises the same first and second steps of the preceding modes as shown in FIG. 3a. The third step of this embodiment of the method according to the invention consists in depositing simultaneously a layer 13 of a semiconductor material and a layer 16 of a dielectric material. These first two steps correspond to two levels of masks.
La troisième étape consiste à passiver les zones 131 et 132 non protégées par le diélectrique sur les flancs du semiconducteur. Cette passivation peut être effectuée par une oxydation (plasma O,O2,03,N2O), ou une nitruration (plasma N,NH3), ou une passivation (dépôt de diélectrique planarisant suivi d'une gravure aanisotrope de ce même diélectrique). En effet, à ce stade du procédé de fabrication, il est nécessaire de protéger les flancs 131 et 132 du semiconducteur afin d'éviter les fuites grille - source, ceux-ci n'étant plus protégés par une couche de diélectrique comme dans les deux modes de mise en oeuvre du procédé selon l'invention précédents. Puis, dans une quatrième étape, une couche 15 d'un matériau conducteur est déposée puis gravée, constituant un troisième niveau de masque (figure 3c). Le contact grille 22 - connection 3 est cette fois assuré par le contact direct entre le niveau conducteur 15 et la connexion 3.The third step consists in passivating the zones 131 and 132 not protected by the dielectric on the sides of the semiconductor. This passivation can be carried out by an oxidation (plasma O, O2.03, N2O), or a nitriding (plasma N, NH3), or a passivation (deposition of planarizing dielectric followed by an aanisotropic etching of this same dielectric). Indeed, at this stage of the manufacturing process, it is necessary to protect the sides 131 and 132 of the semiconductor in order avoid grid - source leaks, these no longer being protected by a dielectric layer as in the two previous embodiments of the method according to the invention. Then, in a fourth step, a layer 15 of a conductive material is deposited and then etched, constituting a third level of mask (FIG. 3c). The gate contact 22 - connection 3 is this time provided by the direct contact between the conductor level 15 and the connection 3.
Ce troisième mode peut être complété par une cinquième étape consistant à graver les couches de diélectrique 16 et du matériau semiconducteur 13 en utilisant le conducteur 15 comme niveau de masque. En effet, des zones de la mesa semiconducteur 13 - isolant 16 peuvent s'étendre de part et d'autre de la couche conductrice 15 gravée (grille) dans le plan perpendiculaire au plan de la figure, et devoir être retirées suivant la technologie désirée. Une sixième étape peut ensuite consister à passiver par oxydation ou nitruration ou par un dépôt d'un diélectrique sur les flancs du semiconducteur non protégés par le diélectrique 16.This third mode can be completed by a fifth step consisting in etching the layers of dielectric 16 and of the semiconductor material 13 using the conductor 15 as the mask level. Indeed, zones of the semiconductor mesa 13 - insulator 16 can extend on either side of the conductive layer 15 etched (grid) in the plane perpendicular to the plane of the figure, and must be removed according to the desired technology . A sixth step can then consist of passivating by oxidation or nitriding or by depositing a dielectric on the sides of the semiconductor not protected by the dielectric 16.
D'autre part dans le cas où un contact ne doit pas être établi entre la grille 22 et la connexion 3, une mesa semiconducteur 13 - isolant 16 peut être laissée sur la connexion 3 afin de l'isoler du niveau conducteur 15.On the other hand, in the case where contact must not be established between the grid 22 and the connection 3, a semiconductor mesa 13 - insulator 16 can be left on the connection 3 in order to isolate it from the conductive level 15.
La figure 3d représente une partie d'une matrice active réalisée selon ce troisième mode de mise en oeuvre du procédé selon l'invention décrit à partir des figures 3a à 3c. Une électrode 26 de forme quelconque comporte une patte 2 formant le drain du transistor 30. En même temps que cette électrode 26 est gravée une colonne 25 munie d'une languette en vis à vis du drain 2 et qui forme la source 1 du transistor 30. Au cours de la seconde étape du procédé, le semiconducteur 13 et le diélectrique 16 sont déposés et gravés de manière à former les mésas 31 et 32, la mesa 31 formant le niveau semiconducteur du transistor 30 et la mesa 32 un niveau d'isolation entre la colonne 25 et la grille 28 déposée et gravée au cours de la quatrième étape du procédé. Les flancs des mesas 31 et 32 ont été passivées avant le dépôt et la gravure de la grille 28. Il est à noter que dans cet exemple, les mesas semiconductrices - isolantes débordent de chaque coté de la grille et n'ont donc pas été traitées selon les cinquièmes et sixième étapes du procédé ci-dessus. La figure 3e représente I' inverseur 40 de la figure 1 e fabriqué selon le troisième mode de mise en oeuvre du procédé selon l'invention. On retrouve ainsi les transistors 41 et 42, le premier niveau conducteur constituant les sources et drains de ces transistors ainsi que la connection 45, les mesas 29 dont les flancs ont été passives constituées d'un premier niveau semiconducteur 13 et d'un premier niveau isolant 16, et enfin, le niveau métallique 15 formant les grilles 43 et 44 des transistors 41 et 42 ainsi que les connections 46 et 47.FIG. 3d represents a part of an active matrix produced according to this third embodiment of the method according to the invention described from FIGS. 3a to 3c. An electrode 26 of any shape has a tab 2 forming the drain of the transistor 30. At the same time as this electrode 26 is etched a column 25 provided with a tongue opposite the drain 2 and which forms the source 1 of the transistor 30 During the second step of the process, the semiconductor 13 and the dielectric 16 are deposited and etched so as to form the mesas 31 and 32, the mesa 31 forming the semiconductor level of the transistor 30 and the mesa 32 an isolation level. between column 25 and grid 28 deposited and etched during the fourth step of the process. The sides of mesas 31 and 32 were passivated before depositing and etching the grid 28. It should be noted that in this example, the semiconductor - insulating mesas overflow on each side of the grid and therefore have not been treated according to the fifth and sixth steps of the above process. FIG. 3e represents the inverter 40 of FIG. 1 e manufactured according to the third embodiment of the method according to the invention. We thus find the transistors 41 and 42, the first conductive level constituting the sources and drains of these transistors as well as the connection 45, the mesas 29 whose flanks were passive consisting of a first semiconductor level 13 and a first level insulator 16, and finally, the metal level 15 forming the gates 43 and 44 of the transistors 41 and 42 as well as the connections 46 and 47.
Dans ces second et troisième modes de mise en oeuvre du procédé selon l'invention, le diélectrique 16 déposé dans le même cycle de vide que le niveau semiconducteur 13 permet une bonne interface entre ces deux niveaux.In these second and third embodiments of the method according to the invention, the dielectric 16 deposited in the same vacuum cycle as the semiconductor level 13 allows a good interface between these two levels.
Le procédé selon l'invention peut être mis en oeuvre sur un substrat de verre ou sur un substrat déjà préprocessé (plan de masse, black matrix et niveau isolant) qui permet, par exemple, de rajouter une capacité de stockage et de protéger le transistor contre la lumière par l'arrière de l'écran.The method according to the invention can be implemented on a glass substrate or on an already preprocessed substrate (ground plane, black matrix and insulating level) which allows, for example, to add a storage capacity and to protect the transistor against the light from the back of the screen.
En effet, un perfectionnement particulièrement intéressant de l'invention consiste à déposer et graver un premier niveau opaque directement sur le substrat en début de procédé, de manière à ce que celui-ci masque le canal semiconducteur entre la source et le drain de chaque transistor étage direct. Ce premier niveau opaque peut être déposé et gravé de manière à masquer à la lumière les endroits où vont être déposés les sources, drains et semiconducteurs constituant les transistors commandant les électrodes de pixels, ou ne laisser exposées à la lumière que les zones comportant les électrodes, améliorant ainsi le contraste de l'écran tout en bloquant la photoconductivité des matériaux semiconducteurs utilisés. Cela ne rajoute qu'un niveau de masque au procédé selon l'invention. Ce niveau peut être en métal réfléchissant et, s'il est conducteur, cette première gravure doit être suivie du dépôt sur toute la surface du substrat d'un niveau isolant.Indeed, a particularly advantageous improvement of the invention consists in depositing and etching a first opaque level directly on the substrate at the start of the process, so that the latter masks the semiconductor channel between the source and the drain of each transistor. direct floor. This first opaque level can be deposited and etched so as to mask in the light the places where the sources, drains and semiconductors constituting the transistors controlling the pixel electrodes are going to be deposited, or leave exposed only the areas comprising the electrodes , thereby improving the contrast of the screen while blocking the photoconductivity of the semiconductor materials used. This only adds one level of mask to the method according to the invention. This level can be made of reflective metal and, if it is conductive, this first etching must be followed by the deposition over the entire surface of the substrate of an insulating level.
Un tel premier niveau opaque est appelé "black matrix" et est décrit en détail dans la demande de brevet Français n° 91 12586 déposée par la demanderesse.Such a first opaque level is called "black matrix" and is described in detail in French patent application No. 91 12586 filed by the applicant.
Un autre perfectionnement de la présente invention peut être de rajouter directement sur le substrat au début du procédé, une capacité de stockage sur laquelle sera réalisé la matrice active. Une telle capacité de stockage est décrite en détail dans la demande de brevet Français n° 91 12585 déposée par la demanderesse. Cette capacité de stockage peut être réalisée par une couche conductrice transparente déposée directement sur tout le substrat et recouverte par une couche isolante transparente. Ainsi, aucun nouveau niveau de masque n'a été ajouté. Elle peut aussi être opaque et gravée de manière à ne masquer que les zones semiconductrices ou à ne laisser passer la lumière que sur les zones comportant les électrodes, jouant ainsi le rôle de "black matrix". De préférence, le substrat 10 est une plaque de verre, le matériau transparent et conducteur 1 1 peut être de l'oxyde d'indium et d'étain (ITO) ou de l'oxyde d'étain (SnO2), et le matériau semiconducteur 13 une multicouche ou une monocouche de silicium amorphe hydrogéné (a- Si:H), de silicium polycristallin ou microcristallin. Les matériaux diélectriques 14 et 16 peuvent être du dioxyde de silicium (SiO2), du nitrure de silicium (SiN) ou de l'oxynitrure. De préférence, la couche d'isolant en contact avec le semiconducteur est une couche de nitrure de silicium (SiN) et celle qui est en contact avec le conducteur, une couche de dioxyde de silicium (SiO2). Les matériaux conducteurs 15 peuvent être de l'aluminium, du titane, du chrome, du molybdène, du tungstène, du tantale, de TITO, des alliages ou des multicouches.Another improvement of the present invention can be to add directly to the substrate at the start of the process, a capacity storage on which the active matrix will be produced. Such storage capacity is described in detail in French patent application No. 91 12585 filed by the applicant. This storage capacity can be achieved by a transparent conductive layer deposited directly on the entire substrate and covered by a transparent insulating layer. Thus, no new mask level has been added. It can also be opaque and etched so as to only mask the semiconductor areas or to let light pass only over the areas comprising the electrodes, thus playing the role of "black matrix". Preferably, the substrate 10 is a glass plate, the transparent and conductive material 11 can be indium tin oxide (ITO) or tin oxide (SnO2), and the material semiconductor 13 a multilayer or monolayer of hydrogenated amorphous silicon (a- Si: H), of polycrystalline or microcrystalline silicon. The dielectric materials 14 and 16 can be silicon dioxide (SiO2), silicon nitride (SiN) or oxynitride. Preferably, the insulating layer in contact with the semiconductor is a layer of silicon nitride (SiN) and that which is in contact with the conductor, a layer of silicon dioxide (SiO2). The conductive materials 15 can be aluminum, titanium, chromium, molybdenum, tungsten, tantalum, TITO, alloys or multilayers.
La présente invention s'applique à la fabrication de transistors à couche mince et à structure étagée directe, autopassivée et autoécrantée qui peuvent être utilisés pour la réalisation de tout circuit électronique (électronique de traitement de signaux) intégré sur un substrat préprocessé ou non, ou sur une plaque de verre à base de silicium amorphe comme ceux utilisés pour la photocopie ou le pilotage de barrette de photodiode, et plus particulièrement pour la réalisatiion d'écrans plats à cristaux liquides commandés par une électronique (drivers) externe ou intégrée. The present invention applies to the manufacture of thin film transistors with a direct, self-passivating and self-screening stepped structure which can be used for the production of any electronic circuit (signal processing electronics) integrated on a preprocessed or non-preprocessed substrate, or on an amorphous silicon-based glass plate such as those used for photocopying or driving a photodiode array, and more particularly for making flat liquid crystal screens controlled by external or integrated electronics (drivers).

Claims

REVENDICATIONS
1 . Procédé de fabrication de transistors à couches minces étages directs (20;23;24) à quatre niveaux de masques, caractérisé en ce qu'il comporte les étapes suivantes:1. Method for manufacturing direct-stage thin-film transistors (20; 23; 24) with four mask levels, characterized in that it comprises the following steps:
. dépôt et gravure d'un premier niveau conducteur (1 1 ) sur un substrat isolant (10) de manière à former une source (1 ) et un drain (2),. deposition and etching of a first conductive level (1 1) on an insulating substrate (10) so as to form a source (1) and a drain (2),
. dépôt et gravure d'un niveau semiconducteur (13) suivi d'un premier niveau isolant (16) joignant les source (1 ) et drain (2), . dépôt et gravure d'un second niveau isolant (14),. deposition and etching of a semiconductor level (13) followed by a first insulating level (16) joining the source (1) and drain (2),. deposition and etching of a second insulating level (14),
. dépôt et gravure d'un second niveau conducteur (15) réalisant la grille (22) du transistor (20,23).. deposition and etching of a second conductive level (15) producing the gate (22) of the transistor (20,23).
2. Procédé selon la revendication 1 caractérisé en ce que le second niveau isolant (14) est gravé de manière à créer une ouverture2. Method according to claim 1 characterized in that the second insulating level (14) is etched so as to create an opening
(5) au travers de celui-ci, cette ouverture débouchant sur une connexion (3) déposée et gravée lors de la première étape du procédé,(5) through it, this opening leading to a connection (3) deposited and etched during the first step of the process,
3. Procédé selon la revendication 2 caractérisé en ce que le second niveau isolant (14) est gravé de manière à ce qu'une partie (29) de celui-ci située sur le semiconducteur (13) et le premier niveau isolant (16) soit enlevée, le diélectrique de grille du transistor (24) étant réalisé par le premier niveau isolant (16),3. Method according to claim 2 characterized in that the second insulating level (14) is etched so that a part (29) thereof located on the semiconductor (13) and the first insulating level (16) either removed, the gate dielectric of the transistor (24) being produced by the first insulating level (16),
4. Procédé selon l'une quelconque des revendications précédentes caractérisé en ce que le second niveau conducteur (15) est gravé de manière à bloquer la photoconductivité du niveau semiconducteur (13),4. Method according to any one of the preceding claims, characterized in that the second conductive level (15) is etched so as to block the photoconductivity of the semiconductor level (13),
5. Procédé de fabrication de transistors à couches minces étages directs (30) à trois niveaux de masques, caractérisé en ce qu'il comporte les étapes suivantes:5. Method for manufacturing direct-stage thin-film transistors (30) with three mask levels, characterized in that it comprises the following steps:
. dépôt et gravure d'un premier niveau conducteur (1 1 ) sur un substrat isolant (10) de manière à former une source et un drain (1 ,2),. deposition and etching of a first conductive level (1 1) on an insulating substrate (10) so as to form a source and a drain (1, 2),
. dépôt d'un niveau semiconducteur (13) suivi d'un niveau isolant (16) et gravure de l'ensemble joignant les source (1 ) et drain (2),. deposition of a semiconductor level (13) followed by an insulating level (16) and etching of the assembly joining the source (1) and drain (2),
. oxydation, nitruration ou passivation des flancs (131 ,132) du niveau semiconducteur (13), . dépôt et gravure d'un niveau conducteur (15),. oxidation, nitriding or passivation of the sides (131, 132) of the semiconductor level (13), . deposit and etching of a conductor level (15),
6. Procédé selon la revendication 4 caractérisé en ce que ces étapes sont suivies d'une étape de gravure de la bicouche niveau semiconducteur (13) - niveau isolant (16) en utilisant le niveau gravé conducteur (15) comme niveau de masque,6. Method according to claim 4 characterized in that these steps are followed by a step of etching the bilayer semiconductor level (13) - insulating level (16) using the etched conductive level (15) as the mask level,
7. Procédé selon la revendication 5 caractérisé en ce que cette gravure est suivie d'une étape d'oxydation, de nitruration ou de passivation des flancs gravés du niveau semiconducteur (13),7. Method according to claim 5 characterized in that this etching is followed by an oxidation, nitriding or passivation step of the etched sides of the semiconductor level (13),
8. Procédé selon l'une quelconque des revendications précédentes caractérisé en ce que les sources (1 ), drains (2) et grilles (22) sont gravés de manière à former respectivement les colonnes (25), électrodes de pixels (26) et lignes (28) d'un écran à cristaux liquides à matrice active.8. Method according to any one of the preceding claims, characterized in that the sources (1), drains (2) and grids (22) are etched so as to respectively form the columns (25), pixel electrodes (26) and lines (28) of an active matrix liquid crystal display.
9. Procédé selon l'une quelconque des revendications précédentes caractérisé en ce que les transistors ainsi réalisés sont utilisés pour la réalisation d'une électronique de commande intégrée et/ou une électronique de traitement de signaux.9. Method according to any one of the preceding claims, characterized in that the transistors thus produced are used for the production of integrated control electronics and / or signal processing electronics.
10. Procédé selon l'une quelconque des revendications précédentes caractérisé en ce que le substrat isolant (10) est transparent.10. Method according to any one of the preceding claims, characterized in that the insulating substrate (10) is transparent.
11. Procédé selon l'une quelconque des revendications précédentes caractérisé en ce que le premier niveau conducteur (1 1 ) est transparent,11. Method according to any one of the preceding claims, characterized in that the first conductive level (1 1) is transparent,
12. Procédé selon l'une quelconque des revendications précédentes caractérisé en ce que le premier niveau conducteur transparent (11 ) est dopé superficiellement,12. Method according to any one of the preceding claims, characterized in that the first transparent conductive level (11) is surface doped,
13. Procédé selon l'une quelconque des revendications précédentes caractérisé en ce que le premier niveau conducteur (11 ) est une bicouche conducteur - semiconducteur dopé, 13. Method according to any one of the preceding claims, characterized in that the first conductive level (11) is a conductive bilayer - doped semiconductor,
14. Procédé selon l'une quelconque des revendications précédentes caractérisé en ce que le substrat isolant (10) est prétraité par un niveau conducteur directement déposé sur ce substrat suivi d'un dépôt d'une couche isolante, cet ensemble formant l'électrode et le diélectrique d'une capacité de stockage,14. Method according to any one of the preceding claims, characterized in that the insulating substrate (10) is pretreated by a conductive level directly deposited on this substrate followed by deposition of an insulating layer, this assembly forming the electrode and the dielectric of a storage capacity,
15. Procédé selon la revendication 14 caractérisé en ce que ce niveau conducteur est opaque et gravé de manière à ne laisser passer la lumière venant de dessous qu'au travers des électrodes (26), cette black matrix ainsi réalisée permettant une amélioration du contraste de l'écran,15. The method of claim 14 characterized in that this conductive level is opaque and etched so as to let light pass from below only through the electrodes (26), this black matrix thus produced allowing an improvement in the contrast of the screen,
16. Procédé selon la revendication 14 caractérisé en ce que ce niveau conducteur est opaque et est gravé de manière à ce qu'il masque le niveau semiconducteur (13) du transistor (20;23;24;30) à la lumière venant de dessous de l'écran,16. The method of claim 14 characterized in that this conductive level is opaque and is etched so that it masks the semiconductor level (13) of the transistor (20; 23; 24; 30) from light coming from below. of the screen,
17. Procédé selon l'une quelconque des revendications précédentes caractérisé en ce que le substrat (10) est une plaque de verre,17. Method according to any one of the preceding claims, characterized in that the substrate (10) is a glass plate,
18. Procédé selon l'une quelconque des revendications précédentes caractérisé en ce que le premier niveau conducteur transparent est constitué d'oxyde d'indium et d'étain ou d'oxyde d'étain,18. Method according to any one of the preceding claims, characterized in that the first transparent conductive level consists of indium tin oxide or tin oxide,
19. Procédé selon l'une quelconque des revendications précédentes caractérisé en ce que les matériaux semiconducteurs sont du silicium amorphe hydrogéné, du silicium polycrystallin ou microcristallin.19. Method according to any one of the preceding claims, characterized in that the semiconductor materials are hydrogenated amorphous silicon, polycrystalline or microcrystalline silicon.
20. Procédé selon l'une quelconque des revendications précédentes caractérisé en ce que les matériaux isolants sont du dioxyde de silicium, du nitrure de silicium ou de l'oxynitrure,20. Method according to any one of the preceding claims, characterized in that the insulating materials are silicon dioxide, silicon nitride or oxynitride,
21. Procédé selon l'une quelconque des revendications précédentes caractérisé en ce que les matériaux conducteurs sont de l'aluminium, du titane, du chrome, du molybdène, du tungstène, du tantale, de l'oxyde d'indium et d'étain, des alliages ou des multicouches,21. Method according to any one of the preceding claims, characterized in that the conductive materials are aluminum, titanium, chromium, molybdenum, tungsten, tantalum, indium tin oxide, alloys or multilayers,
22. Ecran à cristaux liquide comportant une matrice active dont les éléments actifs commandant les électrodes de pixels sont des transistors à couches minces étages directs, caractérisé en ce qu'il est fabriqué par le procédé selon l'une quelconque des revendications précédentes,22. Liquid crystal screen comprising an active matrix, the active elements of which control the pixel electrodes are direct-stage thin-film transistors, characterized in that it is manufactured by the method according to any one of the preceding claims,
23. Ecran à cristaux liquide comportant une matrice active et une électronique de commande intégrée dont les éléments actifs commandant les électrodes de pixels ainsi que constituant l'électronique de commande intégrée sont des transistors à couches minces étages directs, caractérisé en ce qu'il est fabriqué par le procédé selon l'une quelconque des revendications précédentes,23. Liquid crystal display comprising an active matrix and integrated control electronics, the active elements of which control the pixel electrodes and constituting the integrated control electronics are direct-stage thin-film transistors, characterized in that it is manufactured by the process according to any one of the preceding claims,
24. Circuit électronique réalisé sur un substrat isolant (10) caractérisé en ce qu'il est fabriqué par un procédé selon l'une quelconque des revendications 1 à 7. 24. Electronic circuit produced on an insulating substrate (10) characterized in that it is manufactured by a method according to any one of claims 1 to 7.
EP94909965A 1993-03-16 1994-03-15 Direct multilevel thin-film transistor production method Withdrawn EP0689721A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR9303012A FR2702882B1 (en) 1993-03-16 1993-03-16 Method for manufacturing direct step thin film transistors.
FR9303012 1993-03-16
PCT/FR1994/000278 WO1994021102A2 (en) 1993-03-16 1994-03-15 Direct multilevel thin-film transistor production method

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EP0689721A1 true EP0689721A1 (en) 1996-01-03

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EP (1) EP0689721A1 (en)
JP (1) JPH09506738A (en)
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WO (1) WO1994021102A2 (en)

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WO1994021102A2 (en) 1994-09-29
JPH09506738A (en) 1997-06-30
US5830785A (en) 1998-11-03
FR2702882B1 (en) 1995-07-28
WO1994021102A3 (en) 1994-11-10
FR2702882A1 (en) 1994-09-23

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