Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
  • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
  • G06F11/16—Error detection or correction of the data by redundancy in hardware
  • G06F11/1608—Error detection by comparing the output signals of redundant hardware
  • G06F11/1625—Error detection by comparing the output signals of redundant hardware in communications, e.g. transmission, interfaces
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
  • H04L9/002—Countermeasures against attacks on cryptographic mechanisms
  • H04L9/004—Countermeasures against attacks on cryptographic mechanisms for fault attacks
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
  • H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
  • Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
  • Y04S40/00—Systems for electrical power generation, transmission, distribution or end-user application management characterised by the use of communication or information technologies, or communication or information technology specific aspects supporting them
  • Y04S40/20—Information technology specific aspects, e.g. CAD, simulation, modelling, system security

Definitions

• This invention relates to fault detection on redundant signal lines and more particularly to a method and apparatus for providing a unique encryption on each of the signal lines in order to enable the detection of shorts, opens, transmission collisions and correlated transient upsets on the signal lines.
• a fault detection method wherein each of the digital signals is combined with a unique encryption key in an exclusive or (XOR) logic gate, the output of which is coupled to a signal line.
• XOR exclusive or
• each of the signals when combined with its unique encryption key in the XOR has a unique waveform different from each of the other encrypted signals, faults such as shorts between adjacent signal lines, open circuits and collisions may be detected.
• the encrypted signal is recombined with its unique encryption signal in a second XOR logic gate, the output of which has the same waveform as the original data input signal if there are no faults.
• Figure 1 is a schematic diagram of a preferred embodiment of the invention.
• Figure 2 is a diagram illustrating the shift from high frequency to low and low to high with different key signal inputs.
• Figure 3 is a diagram illustrating waveforms for a specific four channel implementation of a system of the present invention
• Figure 4 is a schematic diagram illustrating a multiple input system which could be subject to transmission collisions.
• FIG. 1 Shown in Figure 1 is a schematic diagram of the present invention wherein a digital data signal is input on line 10 as an input to XOR gate 16.
• the other input to XOR gate 16 is a key signal 14 which is input on line 12.
• the output at line 18 consists of the combination of data signal A0 and the key signal coming from key zero.
• the encrypted signal on signal line 18 is combined with the same key signal on line 13 through XOR gate 17.
• the receiver key zero, 15, is the same as the transmitter key zero, 14. If there are no faults, the output of XOR gate 17 should be the same as the original digital data signal input on line 10. In a similar fashion a second digital signal which under normal conditions will be identical to that on line 10, is input on line 20, and combined with a different key signal on line 22. The output of XOR gate 26 will therefore be different from that of XOR gate 16 when the data input signals are identical.
• the encrypted signal on line 28 is combined with the unique key signal on line 23 resulting in an output from XOR gate 27 which is identical to the original input data on line 20.
• XOR gate 27 which is identical to the original input data on line 20.
• the output, or data signals from XOR gates 17, 27 and 37 should be identical with identical data inputs on lines 10, 20 and 30. Utilizing a comparison of the outputs of XOR gates 17, 27 and 37, various failures or faults can be detected. For example, if line 18 should short to line 28, the resultant identical signal will be input to gates 17 and 27. Since gates 17 and 27 are receiving different key inputs on lines 13 and 23, respectively, the outputs of gates 17 and 27 will be different and this difference will be detected by the comparison of the output data streams. The comparison may be made using any of numerous known apparatus or methods for comparison of digital signals.
• the encrypted signals on the signal lines will also be different.
• the dominant signal will appear on the affected lines.
• the signals are then decrypted by combining the encrypted signals with their corresponding key signals, any short or collision will cause a difference in output data that should be identical.
• a short of one of the encrypted lines to ground or an open will be detected through the comparison of the decrypted data with that of the other signal lines.
• An additional feature of the fault detection system is a shift in the frequency content of the encrypted data signal when certain particular keys are used. As shown in
• a data signal comprising first a high frequency content, then a low frequency content is mixed with, in the first example a key equal to a constant or continuous logical one and in a second example with a key equal to an alternating zero and one bit pattern.
• a resultant encrypted data signal in the case where the key is equal t a constant logical one is simply the inverse of the original data signal.
• the encrypted dat signal becomes a steady low signal for an input data signal equal to alternating ones an zeros, and it becomes an alternating zero and one pattern where the input data stream i a steady logical zero.
• the frequency content of the encrypted signal may be shifted from a hig frequency to a low frequency content or vise versa.
• the frequency of the encrypte data will tend to be the inverse of the unencrypted data.
• the resultan encrypted data has a low frequency, or in this case a steady state value.
• the dat has a low frequency content, such as a steady state zero
• the encrypted data has a high frequency content.
• This frequency shift can be used to detect errors caused by frequency dependent faults such as those caused by reactances. For example, this will cause any DC component of NRZI encrypted signals to be different, thereby facilitatin the detection of a level-shift induced bit error rate (BER).
• BER level-shift induced bit error rate
• the power usage for various data patterns may be made more nearly constant by changing the frequency spectrum and polarity of the encrypted signals. For example, if the unencrypted data consisted of primarily logical zeros ther would be a significant power change between that data signal and a data signal which consisted primarily of logical ones. By encrypting the like data input signals wit different keys the encrypted data produces an overall average data signal with a more or less constant power requirement.
• Figure 3 illustrates a specific implementation utilizing four separate data signal lines and the specific corresponding key signals shown on lines 60, 70, 80 and 90.
• the input data are identical and comprise a memorized digital data signals as shown on line 50.
• the key has been selected to be a constant logical zero.
• the resultant output from the XOR gate is simply repeat of the encrypted input data, as shown by line 61 having the identical waveform o line 50.
• the key is selected, as shown on line 70, to be series of alternating logical zeros and ones.
• Line 71 shows that the encrypted dat signal now takes on a different waveform from that of line 61.
• the third key labeled as Key 2 in Figure 3, is selected to be a constant logica one. With a constant logical one input as the key signal, the output of the XOR gat will simply be an inversion of the original input signal. This can be seen by noting that waveform 81 is simply the inverse of the original data signal shown as waveform 50.
• the fourth key signal is selected to be a series of alternating ones and zeros, but of reverse polarity from that of Key 1 shown as waveform 70. It can be seen that this key input results in the fourth encrypted data signal waveform 91, having a similar shape, but inverted from that of waveform 71.
• a duplicate of the XOR gate and appropriate key input is shown as being attached to signal lines 18, 28 and 38.
• data streams A0 and BO would not be utilizing signal line 18 at the same time.
• the A data input signals on lines 10 , 20 and 30 may be transmitting at the same time as the B data signal lines on 110, 120 and 130.
• the data on signal lines 18, 28 and 38 would appear normal in that all of the signals would match.
• this collision fault can be detected. Whenever A and B transmit simultaneously, the signals appearing on 18, 28 and 38 will become the dominant value
• Lines with different keys should have different values, but when simultaneous transmission causes a collision, the signals will be the same. This is detected at the receivers when the signals are recombined with the key signals.
• the encryption or decryption respectfully may be easily implemented by simply inverting the inputs to the parallel- to-serial converter, or the outputs from the serial-to-parallel converter, respectively. Where applicable, this method may be used to replace the key generators and XOR gates previously described.
• the decoding with a key repetition smaller than the number of stages in the serial- to-parallel converter may be accomplished without adding any additional hardware. The "decoding" is accomplished by simply utilizing the appropriate Q or Q not outputs of the converter stages.
• the output of an XOR gate having a data signal and a constant logical zero as inputs is the same as the original data signal.
• the XOR gate may simply be deleted.
• the output of an XOR gate having a data signal and a constant logical one as inputs is the original data signal inverted.
• the XOR gate may be replaced by an inverter.
• what has been described as a signal line may be any communication path, such as a wire, fiber optic conductor or
• RF channel and the exclusive OR gate means may be substituted with any functional equivalent for combining a data signal with a key signal to obtain an encrypted or cyphered signal.

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• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Computer Security & Cryptography (AREA)
• Quality & Reliability (AREA)
• Physics & Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Dc Digital Transmission (AREA)
• Detection And Prevention Of Errors In Transmission (AREA)

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• 1992
  • 1992-12-22 US US07/995,107 patent/US5307409A/en not_active Expired - Lifetime
• 1993
  • 1993-12-14 CA CA002134559A patent/CA2134559A1/en not_active Abandoned
  • 1993-12-14 EP EP94905395A patent/EP0676108B1/de not_active Expired - Lifetime
  • 1993-12-14 JP JP6515276A patent/JPH08505021A/ja active Pending
  • 1993-12-14 WO PCT/US1993/012204 patent/WO1994015420A1/en active IP Right Grant
  • 1993-12-14 DE DE69305998T patent/DE69305998T2/de not_active Expired - Fee Related

Non-Patent Citations (1)

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