EP0674252A1 - Circuit to control the voltage between well and source of MOS logic circuit transistors and servo system of the power supply - Google Patents

Abstract

A current source (25) connected between the supply voltage (27) and the drain of a reference MOS transistor (24) imposes a reference current I(ref) on the transistor drain. The drain and grid of the transistor are maintained at the same voltage by a short circuit (CC). A comparator (21) fed from the supply voltage (V+) (27) compares the drain voltage of the transistor (24) with a reference voltage V(tnref) and the difference is fed to a voltage controlled oscillator (22). The oscillator output supplies a multiplier (23) which feeds back to the container thus controlling the threshold voltages of all the transistors in the container.

Description

The present invention relates to circuits produced in CMOS technology and in which transistors of at least one of the types of conductivity are arranged in a common box provided in the substrate of the integrated circuit.

Circuits of this type have the particularity of being able to work with a regulated voltage of polarization of the box in order to adjust the threshold voltage of the transistors, essentially with the aim of reducing the consumption of the circuit.

Such a circuit is described in PCT patent application WO 94/01890. In this case, we seek above all to be able to operate the circuit at different supply voltages, while ensuring the proper functioning of the transistors. To this end, the common box receives a bias voltage which is regulated as a function of a control signal representing the desired supply voltage, so as to adapt the threshold voltages of the transistors located in the box in question. Thus, the consumption of the integrated circuit can be adapted to the operating conditions that it is desired to impose on it according to the circumstances. For example, when a computer equipped with such a circuit is in standby, the box threshold voltage is adapted to this operating condition to allow the circuit to operate at a lower supply voltage.

It is generally known that the control of the threshold voltages of the MOS transistors (and consequently of the box voltages) is a major problem when it is desired to ensure, on the one hand, the operational safety of the circuits and , on the other hand, a minimum consumption of the latter, especially when the threshold voltages are low.

This problem becomes particularly crucial when the circuits are supplied from a limited energy source, such as a battery or electromagnetic radiation. Among the technologies used for low consumption applications is CMOS (Complementary - Metal - Oxide - Semiconductor) technology. It is in this technology that the present invention finds a particular suitable application. This CMOS technology will therefore be taken as the basis of the description which follows, but it should be noted at the outset that it is applicable by analogy to other technologies of the MOS type.

où I_DSn et I_Dsp, sont les courants de drain spécifiques en faible inversion des transistors MOS, respectivement de type n et de type p, f est la fréquence de commutation de la porte logique, C est l'ensemble de ses capacités parasites chargeant sa sortie, V est sa tension d'alimentation, n_n et n_p sont les pentes en faible inversion des transistors MOS respectivement de type n et de type p constituant cette porte logique, V_tn et V_tp sont les tensions de seuil des transistors MOS, respectivement de type n et de type p et UT est la valeur du potentiel thermique de ces transistors MOS. On voit par cette relation qu'un paramètre qui permet de diminuer de façon importante la puissance consommée par la porte logique est la tension d'alimentation V, car ce paramètre apparaît au carré dans la formule (1) ci-dessus.In CMOS technology, the power P _t consumed by a logic gate is equal to the sum of the dynamic power Pdyn and the static power Pstat and it can be expressed as follows:

where I _DSn and I _Dsp , are the specific drain currents in low inversion of the MOS transistors, respectively of type n and of type p, f is the switching frequency of the logic gate, C is the set of its parasitic capacities charging its output, V is its supply voltage, n _n and n _p are the slopes in low inversion of the MOS transistors of type n and of type p respectively constituting this logic gate, V _tn and V _tp are the threshold voltages of the transistors MOS, respectively of type n and of type p and UT is the value of the thermal potential of these MOS transistors. It can be seen from this relation that a parameter which makes it possible to significantly reduce the power consumed by the logic gate is the supply voltage V, since this parameter appears squared in the formula (1) above.

où $$\frac{\text{β}}{\text{2}\mathit{\text{n}}}$$

est un facteur technologique pour chaque transistor MOS. En abaissant seulement la tension d'alimentation, on voit que le délai de la porte logique augmente. Pour éviter que la vitesse de fonctionnement diminue lorsque l'on baisse la tension d'alimentation V, il faut baisser aussi les tensions de seuil. Du point de vue technologique, il est possible d'abaisser les tensions de seuil V_t des transistors MOS. Toutefois, la composante statique de la puissance consommée par la porte logique prend alors une plus grande importance (voir formule (1)). De plus, la dispersion des tensions de seuil due à la technologie ou leur variation due à la température atteint facilement une valeur relativement grande de ± 200 mV. L'existence d'une telle marge d'incertitude sur la valeur des tensions de seuil ne permet pas d'assurer le minimum de consommation.However, the delay Td of a logic gate is expressed, in strong inversion, by the relation: $$\text{(2)}{\mathit{\text{T}}}_{\mathit{\text{d}}}\text{=}\frac{\mathit{\text{<figure-callout id="2" label="CV β" filenames="imgf0001.png,imgf0002.png" state="{{state}}">CV </figure-callout>}}}{\frac{\mathit{\text{β}}}{}}$$

or $$\frac{\text{<figure-callout id="2" label="β" filenames="imgf0001.png,imgf0002.png" state="{{state}}">β</figure-callout>}}{\text{2}\mathit{\text{not}}}$$

is a technological factor for each MOS transistor. By lowering only the supply voltage, we see that the delay of the logic gate increases. To prevent the operating speed from decreasing when the supply voltage V is lowered, the threshold voltages must also be lowered. From the technological point of view, it is possible to lower the threshold voltages V _t of the MOS transistors. However, the static component of the power consumed by the logic gate then takes on greater importance (see formula (1)). In addition, the dispersion of threshold voltages due to technology or their variation due to temperature easily reaches a relatively large value of ± 200 mV. The existence of such a margin of uncertainty on the value of the threshold voltages does not ensure the minimum consumption.

Nevertheless, it is possible to act on the threshold voltage of a MOS transistor by electronic means. As already indicated in the aforementioned prior patent application, this action can be done by polarization of the box voltage with respect to the sources of the MOS transistors produced in this box. To do this, the MOS transistors to which it is desired to impose a given threshold voltage must, on the one hand, all be of the same type of conductivity and, on the other hand, be installed in a box isolated from the supply voltages. It will easily be understood that if several different threshold voltages are desired, it will be necessary to have as many boxes isolated from each other, it being understood that the expression "same box" means here either a single box or several electrically connected boxes .

It will be recalled that, if the substrate is of type n, the simplified structure shown in FIG. 1 is used for an transistor of type n. It is installed in a p-type box 2, the box itself being installed in an n-type substrate 3. The MOS transistor 1 is composed of two n-type regions 4 and 5, respectively the source and the drain, formed in the well 2, as well as an insulated layer 6 forming the gate.

A p-type region 7 is diffused in the well 2 to allow the latter to be polarized. In addition, an n-type region 8 is diffused in the substrate 3 in order to be able to apply a voltage, for example the supply voltage V +, to the MOS transistor 1 and to other transistors (not shown) which constitute the circuit produced. in substrate 3.

The structure shown in FIG. 1 not only forms the MOS transistor 1 but also creates several diode junctions between the adjacent n and p zones. As a result, parasitic bipolar elements are formed by this same structure. FIG. 2 shows the main parasitic bipolar elements associated with the MOS transistor 1 of FIG. 1. Thus, we see in FIG. 2 the diagram of the MOS transistor 1 and the diagrams of the parasitic bipolar transistors 10, 11 and 12. The bipolar transistor 10 is formed in parallel with the MOS transistor 1, the collector and the emitter of the bipolar transistor 11 are formed between the drain of the MOS transistor 1 and the supply voltage V +, while the collector and the emitter of the bipolar transistor 12 are formed between the source of the MOS transistor 1 and the supply voltage V +. The bases of these parasitic transistors are all connected to the well of the MOS transistor.

The bipolar transistors 11 and 12 can be made practically inoperative with regard to the operation of the MOS transistor 1 by known means of technological and topological nature. Only the effect of the bipolar transistor 10 cannot be completely eliminated by these means, its collector-emitter current always flowing parallel to the drain-source current of the MOS transistor 1.

We see in Figure 2 that the voltage applied between the box and the source of the MOS transistor 1, is also applied between the base and the emitter of the transistor bipolar 10 and it can be such that it modifies the collector-emitter current of the latter. By analogy, the same reasoning applies to p-type MOS transistors, which have not been shown for the sake of simplification.

et $$\text{(4)\hspace{1em}\hspace{1em}\hspace{1em}}{\mathit{\text{I}}}_{\mathit{\text{d}}}\text{=}{\mathit{\text{K}}}_{\mathit{\text{W}}}{\mathit{\text{βU}}}_{\mathit{\text{t}}}^{\text{2}}\text{e}{\text{}}^{\frac{{\mathit{\text{V}}}_{\mathit{\text{GS}}}\text{-}{\mathit{\text{V}}}_{\mathit{\text{t}}}}{{\mathit{\text{nU}}}_{\mathit{\text{t}}}}}$$

où β et K_w sont des constantes.The currents of a strong and weak inversion MOS transistor are given, respectively, by the following well-known formulas: $$\text{(3)}{\mathit{\text{I}}}_{\mathit{\text{d}}}\text{=}\frac{\text{<figure-callout id="2" label="β" filenames="imgf0001.png,imgf0002.png" state="{{state}}">β</figure-callout>}}{\text{2}\mathit{\text{not}}}\text{((}{\mathit{\text{V}}}_{\mathit{\text{GS}}}\text{-}{\mathit{\text{V}}}_{\mathit{\text{t}}}{\text{)}}^{\text{2}}$$

and $$\text{(4)}{\mathit{\text{I}}}_{\mathit{\text{d}}}\text{=}{\mathit{\text{K}}}_{\mathit{\text{W}}}{\mathit{\text{βU}}}_{\mathit{\text{t}}}^{\text{2}}\text{e}{}^{\frac{{\mathit{\text{V}}}_{\mathit{\text{GS}}}\text{-}{\mathit{\text{V}}}_{\mathit{\text{t}}}}{{\mathit{\text{bare}}}_{\mathit{\text{t}}}}}$$

where β and K _w are constants.

dans laquelle V_to représente la tension de seuil fixée par la technologie et V_BS est la différence de tension entre le caisson et la source du transistor.Furthermore, the threshold voltage V _t of an MOS transistor can, as a first approximation, be expressed by the relation: $$\text{(5)}{\mathit{\text{V}}}_{\mathit{\text{t}}}\text{=}{\mathit{\text{V}}}_{\mathit{\text{to}}}\text{-}{\mathit{\text{V}}}_{\mathit{\text{BS}}}\text{((}\mathit{\text{not}}\text{-1)}$$

in which V _to represents the threshold voltage set by technology and V _BS is the voltage difference between the well and the source of the transistor.

The formulas (3) and (5) above show that the threshold voltage V _t can be controlled by a polarization of the box. If a low threshold voltage is chosen, it is possible, for a given drain current I _d , to correspondingly reduce the gate-source voltage V _GS . However, if the gate-source voltage can be reduced, it is the same for the supply voltage and this, without the speed of operation of the logic gates being affected. It should, however, be mentioned that in this case the static current, as given by formula (4) above, increases.

The above considerations were applied in the aforementioned patent application to establish the threshold voltage, and therefore the box voltage, in order to be able to adapt the circuit to several supply voltages available in practice.

However, it is known that the operating characteristics of a logic circuit can vary depending on other factors, such as the static current, the temperature, the capacity of the load applied to the circuit and others. The influence of these factors on the operation of the integrated circuit can to a certain extent be compensated by a judicious adaptation of the voltage of the box and, consequently, of the threshold voltages of the transistors which, in their turn, have an influence. on the consumption of the circuit and on its operating speed.

However, the aforementioned patent application does not describe any other solutions than that of adjusting the box voltage of the transistors as a function of certain available supply voltages, without taking into account other parameters which may influence the operation of the integrated circuit. , nor take into account the problems that may arise with regard to the operating speed of the circuit.

The object of the invention is to propose a solution which makes it possible, by adjusting the box and supply voltages, to take into account all the essential factors which can influence the operation of the circuit and in particular its consumption and its operating speed.

Consequently, according to a first of its aspects, the object of the invention is to provide a circuit for controlling the voltages between the box and the sources of a plurality of MOS transistors and of a supply voltage of a logic circuit. integrated, ensuring minimum consumption, while ensuring a suitable operating speed.

• un transistor MOS de référence réalisé dans ledit caisson;
• des moyens pour imposer des conditions de fonctionnement prédéterminées audit transistor MOS de référence,
• des moyens pour comparer une caractéristique de fonctionnement dudit transistor MOS de référence à une valeur de référence et pour produire une tension de commande représentative de la différence entre ladite caractéristique de fonctionnement et ladite valeur de référence, et
• des moyens pour appliquer ladite tension de commande entre ledit caisson et la source dudit transistor MOS de référence afin de maintenir ladite caractéristique de fonctionnement dudit transistor MOS de référence à ladite valeur de référence.

The invention therefore firstly relates to a circuit for controlling the voltages between the box and the sources of a plurality of MOS field effect transistors of the same type of conductivity, said MOS transistors all being produced in the same box of the substrate of an integrated logic circuit, characterized in that it comprises:

• a reference MOS transistor produced in said box;
• means for imposing predetermined operating conditions on said reference MOS transistor,
• means for comparing an operating characteristic of said reference MOS transistor with a reference value and for producing a control voltage representative of the difference between said operating characteristic and said reference value, and
• means for applying said control voltage between said well and the source of said reference MOS transistor in order to maintain said operating characteristic of said reference MOS transistor at said reference value.

Thanks to these characteristics, the circuit according to the invention makes it possible to control the polarization of the box of the MOS transistors and thus to continuously fix the threshold voltage of these according to the operating conditions imposed on the reference transistor, the assembly being able to be made in the form of a single integrated circuit.

The invention also relates to a servo system comprising, at least, a circuit as just defined and making it possible to fix the threshold voltages of all the MOS transistors, having the same type of conductivity and belonging to a logic circuit, so as to minimize the consumption of the logic circuit regardless of its activity rate.

The control system according to the invention makes it possible to fix the threshold voltages of the MOS transistors so as to reduce the consumption to a minimum value, regardless of the operating frequency of the logic circuit or of its activity rate. In addition, this servo system makes it possible to take advantage of a technology with very low threshold voltage. In particular, it makes it possible to reach the lower consumption limit of a logic circuit.

In the case of CMOS technology or transistors of the two types of conductivity exist, the invention proposes using at least two circuits for controlling the threshold voltages, namely a control circuit for each type of conductivity. The servo system will then include one and / or the other of the control circuits.

• la figure 1, déjà décrite, représente une vue schématique en coupe d'un substrat à caisson isolé comportant un transistor à effet de champ MOS de type n;
• la figure 2, également déjà décrite, représente un schéma du transistor MOS de la figure 1 et de ses transistors bipolaires parasites;
• les figures 3a à 3d montrent, respectivement, les symboles utilisés dans les dessins annexés pour une source de courant I, une source de courant commandée par une tension V, une source de tension V et une source de tension commandée par une tension V';
• la figure 4a représente le schéma d'un exemple de circuit de commande selon l'invention pour des transistors MOS de type n;
• les figures 4b, 4c et 4d montrent trois variantes de montage du transistor de référence de la figure 4a permettant de prendre en compte d'autres caractéristiques de fonctionnement;
• la figure 5 est un schéma d'un circuit de commande selon l'invention pour des transistors MOS de type p;
• la figure 6 est un schéma d'un circuit selon la figure 4d, pour des transistors de type p;
• la figure 7 est un schéma d'un exemple de système d'asservissement selon l'invention;
• la figure 8 représente une vue schématique en coupe d'un substrat à caisson isolé comportant des transistors à effet de champ MOS des types n et p;
• les figures 9a et 9b montrent deux variantes de réalisation du générateur de tension 104 de la figure 7; et,
• la figure 10 est un graphique montrant des courbes du courant dynamique, du courant statique et du courant total en fonction de la tension d'alimentation, pour une vitesse constante prédéterminée de fonctionnement du circuit logique;
• la figure 11 montre le schéma très simplifié d'un système d'asservissement selon l'invention dans le cas où la valeur de la tension d'alimentation permet d'omettre certains composants du circuit de commande; et
• les figures 12 et 13 montrent deux variantes du circuit de commande selon l'invention.

Other characteristics and advantages of the invention will appear in the course of the detailed but nonlimiting description which follows of various embodiments of the control circuit and of the servo-control system comprising it, the description being given solely by way of description. 'example and made with reference to the accompanying drawings in which:

• FIG. 1, already described, represents a schematic sectional view of an insulated caisson substrate comprising an n-type MOS field effect transistor;
• FIG. 2, also already described, represents a diagram of the MOS transistor of FIG. 1 and of its parasitic bipolar transistors;
• Figures 3a to 3d show, respectively, the symbols used in the accompanying drawings for a current source I, a current source controlled by a voltage V, a voltage source V and a voltage source controlled by a voltage V ';
• FIG. 4a represents the diagram of an example of a control circuit according to the invention for n type MOS transistors;
• Figures 4b, 4c and 4d show three mounting variants of the reference transistor of Figure 4a to take into account other operating characteristics;
• FIG. 5 is a diagram of a control circuit according to the invention for p-type MOS transistors;
• Figure 6 is a diagram of a circuit according to Figure 4d, for p-type transistors;
• FIG. 7 is a diagram of an example of a servo system according to the invention;
• FIG. 8 represents a schematic sectional view of an insulated box substrate comprising MOS field effect transistors of types n and p;
• Figures 9a and 9b show two alternative embodiments of the voltage generator 104 of Figure 7; and,
• FIG. 10 is a graph showing curves of dynamic current, static current and total current as a function of the supply voltage, for a predetermined constant speed of operation of the logic circuit;
• FIG. 11 shows the very simplified diagram of a control system according to the invention in the case where the value of the supply voltage makes it possible to omit certain components of the control circuit; and
• Figures 12 and 13 show two variants of the control circuit according to the invention.

FIG. 4a represents the diagram of a control circuit 20 according to the invention which is intended to control the threshold voltages of a plurality of MOS transistors of type n constituting, for example, all or part of a logic circuit. These transistors are all made in the same box, or several boxes connected together, of a substrate of an electronic chip (not shown). The control circuit 20 comprises a comparator 21, a voltage-controlled oscillator 22, a multiplier 23, an n-type MOS field effect transistor 24, a current source 25 and a voltage source 26. In addition, the circuit 20 has two terminals 27 and 28, intended to be connected respectively to a V + potential and a V- potential, and an output terminal 31. The difference between the V + and V- potentials feeds the control circuit and can thus power the entire integrated logic circuit on the same electronic chip and it can be supplied by a power source such as, for example, a battery.

The current source 25 is connected between the terminal 27 and the drain of the MOS transistor 24, the source of which is connected to the terminal 28. The current source 25 ensures that the drain-source current of the MOS transistor 24 is substantially equal to an I _ref value. The drain-source voltage of the MOS transistor 24 is imposed between the gate and the source of the MOS transistor 24 by means of a DC short circuit between the gate and the drain.

The comparator 21 is supplied by the terminals 27 and 28 and is, in fact, a PID (Proportional-Integral-Differential) type regulator. The voltage source 26 is connected between the terminals 27 and 28 and supplies a voltage of a value Vtnref to the positive input of the comparator 21. The negative input of the comparator 21 is connected to the drain of the MOS transistor 24. Thus, the comparator 24 performs a comparison between the voltage Vtnref and the drain-source voltage of transistor 24, and provides an error signal at its output representative of the difference between the voltages present at its inputs.

The voltage controlled oscillator 22 is connected between terminals 27 and 28. The frequency of the voltage controlled oscillator 22 is determined by the value of the error signal supplied by the comparator 21. The multiplier 23 is supplied by the terminals 27 and 28 and is connected to the voltage-controlled oscillator 22. It is designed to generate a voltage which depends on the frequency of the oscillator 22. The multiplier 23 is charged by a resistor 32, connected between terminal 27 and the output terminal 31. In a variant, the resistor 32 can be replaced by a current source.

The output of the multiplier 23 is connected to the well 7 (see FIG. 1), so that the voltage produced by the circuit 20 is applied, on the one hand, between the well 7 and the source of the transistor 24 and, on the other hand , between this box 7 and the source of all the other MOS transistors which are produced there.

As we have seen above (see formula (5)), the threshold voltage of a MOS transistor is modified by the polarization of the well in which it is made.

As a result, the threshold voltage of an MOS transistor can be reduced by a positive well bias voltage. However, the maximum value of this voltage is limited by the current flowing through the bipolar transistor 10 which is formed in parallel with the MOS transistor 1 (see FIG. 2). This maximum value must be practically equal to 0.4 volts so that the current in the bipolar transistor 10 can be considered negligible.

Furthermore, the threshold voltage of the MOS transistor can be increased by a negative bias voltage of the well. The limit of this negative voltage is defined by the breakdown voltage of the base-emitter junction of the bipolar transistor 10 (of the order of several volts). Therefore, the excursion of the threshold voltage V _t , when the well voltage V _BS is negative, is greater than in direct polarization. In the case of reverse polarization, the voltages to be applied to the boxes are often greater in absolute value than the supply voltages of the logic circuit.

The embodiment of the circuit according to the invention which has just been described makes it possible to obtain, by means of a setpoint voltage V _tnref imposed, threshold voltages of the transistors very low. It follows that the voltage V _GS of the transistors can be reduced and that the logic circuit equipped with the control circuit according to the invention, can be supplied with a comparatively lower supply voltage.

With the embodiments of FIGS. 4b and 4c, it is possible to use as the reference signal imposing determined operating characteristics on the transistor 24, the static current of the circuit in order to fix a minimum static power consumed by the latter, for a speed of given operation.

In the case of FIG. 4b, the transistor 24 is traversed by a current I _DO which therefore represents the static current and which is imposed by the current source 26 '. The ransistor 24 is connected so that its gate-to-ground voltage is zero. The well voltage is then controlled so that the drain voltage of transistor 24 is maintained at V + / 2.

fournie par un générateur de tension 29. Cette valeur fixe la tension de grille du transistor 24 et ainsi la valeur du courant drain-source du transistor 24.FIG. 4c shows another example of embodiment, in which the setpoint is also the static current which is represented here by a value $${\text{V}}_{\text{GS}}{\text{= nU}}_{\text{t}}\text{.ln (k)}$$

supplied by a voltage generator 29. This value fixes the gate voltage of transistor 24 and thus the value of the drain-source current of transistor 24.

FIG. 4d shows another variant in which the reference signal is the current I _onref of saturation of the transistors which is applied as input signal to the current source 25a. The transistor 24 receives here on its gate the voltage V +. This arrangement allows, for a given operating speed, to minimize the static power consumed as a function of the supply voltage.

The multiplier 23 is capable of ensuring the excursion of the voltage V _BS described above. The description of such a multiplier circuit, often referred to as "charge pump" in Anglo-Saxon literature, can be found in an article by John F. Dickison, entitled "On-Chip High-Voltage Generation in MNOS Integrated Circuits Using an Improved Voltage Multiplier Technique ", and published in the IEEE Journal of Solid-State Circuits, Vol. SC-11, No. 3, June 1976.

FIG. 5 shows a control circuit 80 according to the invention, but this time for the control of the box voltages of p-type MOS transistors. The operating principle of this circuit is substantially identical to that of the control circuit 20.

This circuit 80 includes a comparator 21, a voltage controlled oscillator 22, a multiplier 85, a resistor 32 and a current source 25, all of which operate as described above. In addition, it comprises a p-type MOS transistor 81 and a voltage source 82. The voltage source 82 supplies a voltage equal to a value V + - V _tpref . The source of MOS transistor 81 is connected to terminal 27, while its drain is connected wire rack. The other terminal of the current source 25 is connected to terminal 28.

As in the case of the control circuit 20, the current source 25 ensures that the drain-source current of the MOS transistor 81 is substantially equal to a value Iref. As for the comparator 21, its positive input is connected to the drain of the MOS transistor 81, while its negative input is connected to the voltage source 82.

We see in Figure 5 that the drain potential of the MOS transistor 81 is equal to V + - V _tp , where V _tp is the threshold voltage. By applying a voltage V + - V _tpref between the negative input of the comparator 21 and the terminal 28, a comparison is made between a voltage V _tpref and the voltage V _tp of the MOS transistor 81.

FIG. 6 shows an example according to the invention, as an equivalent of the circuit shown in FIG. 4d, but for p-type transistors. The operating principle of circuit 85 is also substantially identical to that of circuit 23 and we can therefore refer to the aforementioned article for more details.

The circuits represented in FIGS. 4a and 5 (or 4d and 6) make it possible to control the threshold voltage of the MOS transistors of the two types of conductivity n and p, provided that the bias voltage remains within the possible limits defined by the voltage of conduction, on the one hand, and the breakdown voltage of the box-source junction, on the other hand, of the transistors 24 and 81. These circuits are completely integrable and their number of elements is low.

Circuits of the type described in relation to FIGS. 4d and 6 can be used, according to a broader aspect of the present invention, in slave systems in which the threshold voltage is regulated as a function of one or more judiciously chosen parameters , such as temperature, value of current consumed etc.

For example, the value of the threshold voltage V _t can be determined so that the consumption of the logic circuit is minimal and this, for a given activity report of the logic circuit.

There is, in fact, an optimal threshold voltage V _t for reaching the most favorable consumption of a logic circuit, this optimal voltage being a function of the architecture of the logic circuit and of its "activity rate".

The ratio of the number of logic gates that transit at a given time to the total number of gates of the circuit is called the "activity rate" of a logic circuit. This activity report therefore varies over time.

FIG. 7 shows an example of a slave system according to the invention implementing a control circuit according to FIG. 4d and another according to FIG. 8a. In this case, the relationship between the dynamic current and the static current consumed by a logic circuit is controlled. This allows the optimization of the threshold voltages of the MOS transistors constituting the logic circuit as a function of the activity rate thereof.

The servo system 100 shown in FIG. 7 indirectly measures the activity of the logic circuit by the dynamic current consumed and takes a fraction of it as a static current setpoint for the control circuits of the box voltages.

The relationship between these two quantities can be determined from the architecture and topology of the logic circuit.

The control system 100 comprises two control circuits 101 and 102, a current measurement circuit 103 and a reduced voltage source 104. The control circuit 101 comprises a comparator 105, a voltage-controlled oscillator 106, a multiplier 107 , a resistor 108 and an MOS transistor 109 of n type. These elements and their operation are identical to the corresponding elements described with reference to FIGS. 4a and 4d. The circuit of control 101 also includes a current source 111 and a voltage source 110 which will be described below.

Likewise, the control circuit 102 comprises a comparator 112, a voltage-controlled oscillator 113, a multiplier 114, a resistor 115 and a p-type MOS transistor 116. These elements and their operation are identical to the corresponding elements and operation described with reference to FIG. 6.

The control circuit 102 further comprises a current source 118 and a voltage source 117 which will also be described below.

The servo system 100 is intended to maintain at a determined value the ratio between the dynamic power and the static power consumed by a logic circuit 119. This can be for example the microprocessor of a portable computer or any circuit having a predetermined functionality.

This logic circuit 119 includes n type MOS transistors, of which the MOS transistor 109 is a part and which are all created in a first well and p type MOS transistors, of which the MOS transistor 116 is a part and which are all created in a second box. The first and second boxes are electrically isolated from each other.

FIG. 8 shows an advantageous embodiment of such a logic circuit made in a common substrate according to a technology which is particularly well suited to the application of the present invention, a technology which is sometimes called "Real twin well", in which separate boxes are provided for n-type and p-type transistors.

More precisely, this substrate 200 is for example of p type and comprises a first well 201 (or first wells 201) in which the PMOS transistors such as the transistor 202 are made. The substrate 200 also has a region n 203 ( or several regions n 203) in which one or more boxes 204. The NMOS transistors of the logic circuit 119 are provided in this or these box (s) 204.

The arrangement of FIG. 8 has the advantage that in the case where several boxes are respectively provided for the PMOS and NMOS transistors, they can be made to work to the best of their possibilities taking into account the functions which they respectively have to perform. and the speed at which they must work respectively. Indeed, separate voltages perfectly suited to these operating conditions can then be applied to the boxes.

Returning now to FIG. 7, it can be seen that the reduced voltage generator 104 is suitable for delivering a reduced voltage V _log intended to supply the logic circuit 119. The box voltages of the n or p type MOS transistors which make up this generator 104 are controlled by the voltages V _BN or V _BP , supplied by the control circuits 101 and 102. In practice, the generator 104 comprises, as shown in FIGS. 9a and 9b, a voltage source 104a and an impedance adapter 300 or 400. The circuit 300 of FIG. 9a is an amplifier mounted in unity gain. The circuit 400 of FIG. 9b is a DC-DC converter.

It has already been proposed, in an article entitled "A Voltage Reduction Technique for Battery-Operated Systems" and published in the journal IEEE Journal of Solid-State Circuits, Vol. 25, No. 5, October 1990, a technique for adjusting the supply voltage of logic circuits, as a function of speed characteristics, temperature conditions and technological parameters, to obtain a minimum consumption of these logic circuits. Such a technique can advantageously be used to determine the reduced voltage V _log necessary and sufficient for the correct operation of the logic circuit 119. This is how the generator 104 of FIGS. 9a and 9b can be produced by the circuit shown in FIG. 1 or that shown in FIG. 3 of the aforementioned article, it being understood however that the n-type and p-type transistors are produced in separate boxes and polarized by the voltages V _BN and V _BP , respectively.

The current measurement circuit 103 comprises a shunt resistor 124, a differential amplifier 125 and a low-pass filter 126. The resistor 124 is connected in series with the voltage generator 104 and the logic circuit 119. The two inputs of the differential amplifier 125 are respectively connected to the two terminals of resistor 124, while the output of amplifier 125 is connected to the input of low-pass filter 126. The total current consumed by logic circuit 119 is measured by resistance 124 and by the amplifier 125. The low-pass filter 126 averages this current value. In addition, the generator receives information on the operating speed of the logic circuit 119 via a line 119a, this information being representative of the operating rate of this circuit 119.

The output of the low-pass filter 126 is connected to the control input of the current sources 111 and 118, so that the latter supply this mean current value as a reference for the static current in the MOS transistors 109 and 116. The circuits 101 and 102 vary the respective box voltages in response to this instruction so that a current of a value kI _DO flows in the reference MOS transistors 109 and 116, where I _DO is their drain-source current in weak inversion (when their gate-source voltage is equal to zero) and where k is a factor which will be explained later.

$$\text{(7)\hspace{1em}\hspace{1em}\hspace{1em}}{\mathit{\text{I}}}_{\mathit{\text{stat}}}\text{=}\frac{{\mathit{\text{I}}}_{\mathit{\text{dyn}}}}{\mathit{\text{b}}}$$

d'où $$\text{(8)\hspace{1em}\hspace{1em}\hspace{1em}}{\mathit{\text{I}}}_{\mathit{\text{stat}}}\text{=}\frac{\text{1}}{\mathit{\text{b}}\text{+ 1}}{\mathit{\text{I}}}_{\mathit{\text{tot}}}$$

où I _dyn représente la valeur du courant dynamique et I _stat la valeur du courant statique et I _tot la valeur du courant total.The fact that the static current setpoint can be calculated from the total current is shown by the formulas below: $$\text{(6)}{\mathit{\text{I}}}_{\mathit{\text{early}}}\text{=}{\mathit{\text{I}}}_{\mathit{\text{dyn}}}\text{+}{\mathit{\text{I}}}_{\mathit{\text{stat}}}$$

$$\text{(7)}{\mathit{\text{I}}}_{\mathit{\text{stat}}}\text{=}\frac{{\mathit{\text{I}}}_{\mathit{\text{dyn}}}}{\mathit{\text{b}}}$$

from where $$\text{(8)}{\mathit{\text{I}}}_{\mathit{\text{stat}}}\text{=}\frac{\text{1}}{\mathit{\text{b}}\text{+1}}{\mathit{\text{I}}}_{\mathit{\text{early}}}$$

where I _dyn represents the value of the dynamic current and I _stat the value of the static current and I _tot the value of the total current.

The ratio b is given by the value R _s of the resistor 124, the gain A of the amplifier 125 and the gain of the low-pass filter 126 as well as by the factor k. The factor k only serves to facilitate the measurement of the current I _DO of the MOS transistors 109 and 116 in low inversion. The value I _DO is generally small and to make it more easily measurable, a voltage equal to nU _t ln (k) is applied between the gate and the source of each of the MOS transistors 109 by means of the voltage sources 110 and 117. and 116. Consequently, the drain-source current of the MOS transistors 109 and 116 takes the value kI _DO .

The consumption of the logic circuit 119 can be made optimal by choosing the appropriate ratio depending on whether one seeks to minimize the current, power or energy consumed by the logic circuit. FIG. 10 is a graph showing, for a given operating speed of the logic gates, the curves of the dynamic current I _dyn , of the static current I _stat and of the total current I _tot of a MOS circuit with respect to the supply voltage V _DD of the circuit, the threshold voltages of the MOS transistors constituting the logic circuit being assumed to vary so as to satisfy said operating speed.

We see that there are two minima of current consumption, a first close to 0 volts and another which is a function of the activity rate and the architecture of the circuit. The minimum close to 0 volts cannot be used, since the corresponding supply voltage is insufficient to ensure correct operation of the logic circuit. However, there exists for a value A of the supply voltage V _DD , another minimum which, in the example considered, is located at a voltage of approximately 0.5 volts. The ratio between the dynamic current I _dynA and the static current I _statA can be, for example, determined from these curves established for a technology and a speed operating values and the values of b and k can thus be defined.

Numerous modifications can be made to the control circuit and to the servo-control system according to the invention, various embodiments of which have just been described, without however departing from the scope of this invention.

In particular, the assembly formed by the oscillator 22 controlled by a voltage and the voltage multiplier 23 are not necessary for the proper functioning of the servo system, when the supply voltage available is large enough to ensure the excursion of the bias voltage of the boxes, necessary to fix the threshold voltages.

As shown in FIG. 11, the boxes of the logic circuit 119 are then directly connected to the outputs of the respective comparators 105 and 112 supplying the voltages V _bn and V _bp while the transistors n and p of the logic circuit operate using respectively d 'a voltage less than V + and a voltage greater than V-, the voltages V + and V- being supplied by a power source 127. For the sake of simplification, the diagram in FIG. 11 shows a simple block 128 to symbolize the reference transistors 109 and 116 and their associated elements.

Consequently, the polarization voltages of the wells can vary between V + and V-, respectively more positive and more negative than the voltages of the sources of the MOS transistors used in the logic circuit 119. In this case, we can then use the principle described here above fixing threshold voltages to maintain the ratio, either between dynamic power and static power, or between dynamic current and static current, or between dynamic energy and static energy.

According to another variant shown in FIG. 12, it is possible to insert between the comparator 105 or 112 and the outputs of the regulation circuits 20 and 80, a DC / DC converter 129, produced for example at using a coil and capacitors (circuits called buck converter, buck-boost converter or boost converter). This converter 129 can also be produced using switched capacitors.

According to another variant shown in FIG. 13, the circuits 22 and 23 or 106, 107 resp. 113 and 114 can be replaced by an amplifier 130 supplied with voltages V + and V- higher, resp. lower than the supply voltages of logic circuit 119. This case therefore also applies if the supply source makes it possible to supply these voltages.

Those skilled in the art will further note that the means used to impose specific operating conditions on the reference MOS transistors shown in Figures 4, 4d and 5 to 7 are only examples to achieve this goal. Other circuits based on the principles of the invention could therefore be produced without departing from the scope of the invention. Likewise, it is possible to choose another operating characteristic of the reference MOS transistors than those described above in order to implement the principles of the invention, by means of the polarization of the well (s).

Furthermore, to ensure that the reference transistors are as representative as possible of the transistors of the circuit to be controlled, it could be advantageous for them to be formed by putting several transistors placed in several locations of the circuit as a whole in parallel. Such an embodiment makes it possible to overcome variations, such as variations in temperature or technological parameters which may exist from one point to another of the circuit.

Claims (14)

Circuit for controlling the voltages between the box and the sources of a plurality of MOS field effect transistors of the same type of conductivity, said MOS transistors all being produced in the same box (2; 201, 204) of the substrate ( 3) an integrated logic circuit, characterized in that it comprises: - a reference MOS transistor (24) produced in said well (3); means (I _ref , CC) for imposing predetermined operating conditions on said reference MOS transistor, - means (21, 22, 23, 32) for comparing an operating characteristic of said reference MOS transistor with a reference value (V _tnref ) and for producing a control voltage representative of the difference between said operating characteristic and said reference value, and - Means (31) for applying said control voltage between said well (2) and the source of said reference MOS transistor (24) in order to maintain said operating characteristic of said reference MOS transistor (24) at said reference value. Circuit according to claim 1, characterized in that said operating characteristic of the reference MOS transistor (24) is its threshold voltage (FIG. 4a). Circuit according to claim 1, characterized in that said operating characteristic of the reference MOS transistor (24) is its static current (FIG. 4b and 4c). Circuit according to claim 1, characterized in that said operating characteristic of the reference MOS transistor (24) is its saturation current (FIG. 4d). Circuit according to claim 1, characterized in that said means (21,22,23) for comparing and producing said control voltage are arranged to compare the drain-source voltage of said reference MOS transistor (24; 81; 109; 116) at the voltage representative of said reference value. Circuit according to claim 1, characterized in that said means for imposing a reference voltage are arranged to impose a voltage $${\text{V}}_{\text{GS}}{\text{= nU}}_{\text{t}}\text{.ln (k)}$$

between the gate and the source of said reference MOS transistor (24), where n is its slope in low inversion in said substrate, U _t is its value of the thermal potential and k is the ratio between on the one hand its drain current when the voltage V _GS is equal to said reference voltage and, on the other hand, its drain current when the voltage V _GS is equal to zero, Circuit according to any one of the preceding claims, characterized in that the said means for comparing and producing a control voltage comprise a comparator (21) intended to compare said operating characteristic of said reference MOS transistor (24) with said reference value, and to produce an error signal equal to the difference between said operating characteristic and said reference value, and - means (22,23) for producing said control voltage as a function of the magnitude of said error signal. Circuit according to claim 7, characterized in that said means (22,23) for producing said control voltage comprise - an oscillator (22) whose frequency is determined by the magnitude of said error signal, and - a multiplier circuit (23) charged by a resistor (R _L ; R _Ln , R _Lp ) or a current source, and intended to generate a voltage which depends on the frequency of said oscillator and which is sufficient to ensure a desired excursion of said control voltage. A circuit according to claim 7, characterized in that said means for producing said control voltage comprises a DC / DC converter (129). Circuit according to claim 7, characterized in that said means for producing said control voltage comprises an amplifier (130). System for slaving the threshold voltages of a plurality of MOS field effect transistors forming part of an integrated circuit with a view to optimizing consumption in particular, as a function of at least one operating parameter of said integrated circuit, said integrated circuit comprising at least a first plurality of MOS field effect transistors of a first type of conductivity produced in at least one and the same first box provided in the substrate of said integrated circuit, said system being characterized in that it comprises a circuit control (101) according to any one of claims 1 to 10. Control system according to claim 10, characterized in that, in the case where it is a question of controlling said ratio between the dynamic current and the static current consumed by said integrated circuit, it comprises a first control circuit according to any one of claims 1 to 10 for controlling the voltages between the box and the sources of the transistors of a first type of conductivity of said integrated circuit, and - Means (103) for measuring the total current consumed by said logic circuit and for supplying, in response to this measurement, a control signal for said current source so that it supplies a current representative of the desired static current. Control system according to claim 11 in which said logic circuit further comprises a second plurality of MOS field effect transistors of a second type of conductivity produced in a second box of said substrate, characterized in that it comprises
- a second control circuit (102) according to any one of claims 1 to 10 for controlling the voltages between the box and the sources of said second plurality of MOS transistors. Control system according to any one of claims 11 and 12, characterized in that it further comprises
- Means (104) for controlling the supply voltage of the logic circuit as a function, on the one hand, of a desired operating speed of the logic circuit and, on the other hand, of the characteristics of the MOS transistors as determined by said control circuits.

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