EP0660298A1 - Bildverarbeitungsverfahren und vorrichtung, und spielmaschine mit einem bildverarbeitungsteil - Google Patents

Bildverarbeitungsverfahren und vorrichtung, und spielmaschine mit einem bildverarbeitungsteil Download PDF

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Publication number
EP0660298A1
EP0660298A1 EP94919832A EP94919832A EP0660298A1 EP 0660298 A1 EP0660298 A1 EP 0660298A1 EP 94919832 A EP94919832 A EP 94919832A EP 94919832 A EP94919832 A EP 94919832A EP 0660298 A1 EP0660298 A1 EP 0660298A1
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EP
European Patent Office
Prior art keywords
access
image data
video ram
data
vram
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP94919832A
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English (en)
French (fr)
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EP0660298A4 (de
Inventor
Seiichi Kajiwara
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Sega Corp
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Sega Enterprises Ltd
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Filing date
Publication date
Application filed by Sega Enterprises Ltd filed Critical Sega Enterprises Ltd
Publication of EP0660298A1 publication Critical patent/EP0660298A1/de
Publication of EP0660298A4 publication Critical patent/EP0660298A4/de
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/42—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of patterns using a display memory without fixed position correspondence between the display memory contents and the display position on the screen
    • A—HUMAN NECESSITIES
    • A63—SPORTS; GAMES; AMUSEMENTS
    • A63F—CARD, BOARD, OR ROULETTE GAMES; INDOOR GAMES USING SMALL MOVING PLAYING BODIES; VIDEO GAMES; GAMES NOT OTHERWISE PROVIDED FOR
    • A63F2300/00—Features of games using an electronically generated display having two or more dimensions, e.g. on a television screen, showing representations related to the game
    • A63F2300/20—Features of games using an electronically generated display having two or more dimensions, e.g. on a television screen, showing representations related to the game characterised by details of the game platform
    • A63F2300/203—Image generating hardware
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/18—Use of a frame buffer in a display terminal, inclusive of the display panel

Definitions

  • the present invention relates to an improved image processing circuit for generating background images in an image processing system.
  • an image displayed on a rasterscan monitor as in a video game consists of usually a plurality of background images (still pictures) forming a background, and a fore ground image (a dynamic picture) containing characters et cetera appearing in the video game and superimposed on the background images.
  • background images and foreground image have their respective priority levels (hereinafter referred to simply as priorities) for the output.
  • priorities are commonly indicated by predetermined numbers, with the images being displayed closer to the viewer in the ascending order of numbers.
  • the numbers are typically assigned to each of the background images, as well as to each character of the foreground image.
  • a foreground image FG and two background images BG0 and BG1 each having numbers indicating priorities.
  • "6" is assigned to a character CHR in the foreground image FG
  • "2" and "4" to the background images BG0 and BG1, respectively.
  • these images are viewed closer to the viewer in the order of the character CHR, back ground image BG1, and background image BG0, namely, in the order of descending priorities.
  • the background images forming a background picture and the foreground image forming a foreground picture are superimposed in synchronism in a predetermined sequence, thereby outputting an overall image as shown in Fig. 10(b) on a monitor screen.
  • Fig. 11 is the prior image processing system for out putting the background images and foreground image described above.
  • a CPU interface 5 to a CPU 1 via a CPU interface 5 is connected a video processor 2 which is connected to a CRT display 16.
  • a storage unit 3 such as a CD-ROM or a ROM cartridge, and a RAM 4 providing a work area for the CPU 1.
  • the storage unit 3 stores programs for executing games and image data for displaying images for the video games.
  • the image data are composed of the smallest unit called a pixel. And each pixel includes a color code as information, which specifies a color to be output by the predetermined number of bits, and a priority code which indicates an output priority.
  • the storage unit 3 stores also voice data, data to specify specifying when and at which location the image data are to be displayed on the screen coordinates, and data specifying operations for rotation, movement, and scaling processing.
  • the CPU 1 reads these data from the storage unit 3 to provide to the RAM 4, and transfers them by way of the CPU interface 5 to the video processor 2.
  • the video processor 2 includes a synchronous circuit 11 which generates synchronizing signals in synchronism with scanning of the CRT display 16. These synchronizing signals are generated and provided to components within the video processor 2 in order to output the foreground image and background images at the same timing. In addition to the synchronizing signals, image data for the foreground image and the background images are respectively transmitted to a foreground image processing section 6 and a background image processing section 7 under the control of the CPU 1.
  • the command RAM 8 temporarily stores the transmitted image data for foreground image such as characters.
  • Add the command RAM 8 stores, for example in a table format, commands given from the CPU 1 at the execution of a game program.
  • the foreground image processing section 6 reads these commands from the command RAM 8, and for the execution stores them into an internal register.
  • the foreground image processing section 6 reads the image data from the command RAM 8, performs on them various image processing such as coordinate calculations, scaling, and color operations, and writes the image data into predetermined addresses within the frame buffer 9.
  • the image data expanded on the frame buffer 9 are output frame-by-frame to a priority circuit 12.
  • the image data for the background images forwarded to the background image processing section 7 are stored in a video RAM (hereinafter referred to as a VRAM) 10.
  • the image data for the background images consist of pattern data and pattern Name data.
  • the pattern data are each composed of an aggregate of color codes for respective pixels within a cell, the cell being a basic unit composed of for example 8 x 8 pixels in the horizontal and vertical directions as depicted in Fig. 12(a1).
  • the pattern name data contain data addresses of the above-described pattern data on the background images.
  • the background images are each comprised of an aggregate of a predetermined number of cells, and the pattern name data specify the locations of cells on the background images being stored within the VRAM 10, by leading addresses of the cells on the VRAM.
  • the priority circuit 12 checks the priorities in outputting foreground and background image data transferred respectively from the foreground image processing section 6 and the background image processing section 7, and outputs image data in the order of descending priorities to combine the foreground image and the background image, and forwards the results to a colorizing circuit 13.
  • a color RAM 14 is connected to the colorizing circuit 13.
  • the color codes of the image data forwarded from the priority circuit 12 each specifies a specific address in conformity with which specific color data are read from the color RAM 14.
  • These color data are converted into RGB data indicating a mixing ratio of three primary colors (red, green, blue) and delivered to a video signal generation circuit 15 in which the digital signals are converted into analog signals in the form of video signals by a D/A converter.
  • the thus generated video signals are provided as output to the CRT display 16 such as a standard TV monitor.
  • the background image processing section 7 reads image data for background images from the VRAM 10. It also writes the image data for background images into the VRAM 10. These actions are called VRAM access, which are typically controlled by an access circuit 17 included in the background image processing section 7. The VRAM access will now be described.
  • the VRAM access is performed when reading the image data from the VRAM upon the display of background images and when writing new image data supplied from the CPU into the VRAM.
  • the VRAM access will include an "image data readout access” for reading out the image data stored in the VRAM, a “CPU access” for writing new image data from the CPU into the VRAM, and a “parameter readout access” for reading out parameters et cetera necessary for the image display stored in the VRAM.
  • the "image data readout access” is performed during the display period, in which predetermined access actions are specified to read out image data from the VRAM. These access actions consist of a "pattern name read” for specifying the readout of pattern name data within the VRAM, and a “pattern data read” for specifying the readout of pattern data.
  • the number of times of these access actions and the "CPU access" to be performed during the display period can be set as the contents of the VRAM access per unit time in accordance with predetermined restrictions.
  • the unit time for the VRAM access is typically a time taken to output one row (eight pixels) in the horizontal direction within a single cell, which is equivalent to one cycle.
  • the access circuit serves to set one access for the output time of one pixel, thereby allowing the VRAM to be accessed eight times in one cycle.
  • the contents of the eight VRAM access actions per one cycle are called a cycle pattern.
  • the access circuit selects addresses of the predetermined image data within the VRAM in accordance with the cycle pattern, and supplies these addresses to the VRAM, whereby the access to the VRAM can be controlled.
  • concrete description will be given of an example of such VRAM access based on the cycle pattern in the case of using two background images BG0 and BG1.
  • Fig. 14(a) depicts, in a table format, a cycle pattern of the access circuit 17 included in the background image processing section 7 of Fig. 11.
  • Fig. 14(b) depicts a data configuration contained in the VRAM 10 connected to the access circuit 17.
  • cycle patterns for reading image data are previously set in the hardware.
  • the access circuit 17 reads pattern name data (PND) of the background image BG0 at the first access in accordance with a cycle pattern.
  • the access circuit 17 provides to the VRAM 10 a selection signal indicating an address of pattern name data of the background image BG0 within the VRAM. Then, in conformity with the address, the pattern name data for the background image BG0 are read from the VRAM 10.
  • Such access is commonly capable of reading image data for one complete word (16 bits) at a time.
  • the pattern name data are made up of 16 bits containing a leading address of the pattern data (in units of cell) in the background image.
  • the access circuit performs, at the second and subsequent access, readout of the pattern data (PTD) of the background image BG0 in accordance with the cycle pattern.
  • the access circuit reads pattern data specified by the leading address and corresponding to one horizontal row (eight pixels) of a cell. Assuming that for both the background images BG0 and BG1, one word pattern data read by one access contains color codes for four pixels, the same pattern data must be accessed twice in order to read color codes for eight pixels. Therefore, read at the second and third access are pattern data of the background image BG0 corresponding to two words.
  • pattern name data are read at fourth access to obtain a leading address of pattern data of the background image BG1.
  • pattern data for two words are read from the VRAM in conformity with the leading address.
  • the seventh and eighth access of one cycle is composed of a CPU access for writing during the display period into the VRAM new image data supplied from the CPU.
  • addresses of image data to be written are fed from the CPU into the VRAM 10.
  • the image data written into the VRAM by the CPU access during the display period are read at appropriate timing in accordance with an image data readout procedure in the above-described cycle pattern. This will allow a background image to be rewritten in the process of a game to alter the background image.
  • the cycle patterns in the access circuit each serve to specify, as the contents of the access within a unit time, (1) timing to specify the access action during the display period and the number of times of the specification, and (2) the CPU access during the display period.
  • a method has been hitherto employed in which these cycle patterns are previously set up in the hardware. More specifically, the hardware contains a plurality of cycle patterns as models fixed thereto in a predetermined data format, whereby a set of optimum data are selected from thereamong in accordance with a specification of the CPU.
  • Recent video games have a tendency to emphasize a visual effect in playing the games in addition to natures of story the games possess.
  • a measure is indispensable for providing a more beautiful image using multiple colors while complicating both dynamic change in movement or rotation and change in scaling.
  • the above device includes more detailed setting of conditions for display, for example, by increasing the number of background images to be used or by individually varying the number of colors or the scaling factor to be used for each of the background images.
  • such complicated setting of conditions may result in a remarkable increase in the amount of information contained in the image data of the background image.
  • a background image BG0 makes use of 16 colors for displaying only color letters or numbers such as scores
  • a background image BG1 employs 256 colors for displaying a floridly colored background image.
  • color codes per pixel in the pattern data each require the amount of data of four (4) bits and eight (8) bits, respectively, for the 16 colored background image BG0 and for the 256 colored background image BG1.
  • increase in the number of colors for use will lead to the increased amount of data per pixel, and therefore the increased amount of information (number of bits) in the pattern data.
  • the color code per pixel is four (4) bits and eight (8) bits, respectively, in the background images BG0 and BG1.
  • the one word (16 bits) contains color codes for four pixels with respect to the background image BG0, whereas it merely includes color codes for two pixels with respect to the background image BG1.
  • the background image BG0 simply requires that two access times be set in a cycle pattern, whereas the background image BG1 needs the setting of four access times, namely more access times per cycle pattern. In this manner, occurrence of variance in the amount of information of image data will cause a necessity to accordingly change the setting of the cycle pattern.
  • the above-described prior art involved the following problems.
  • the conditions on display such as the number of colors used are set in detail to improve the image representation of the background images
  • the cycle pattern upon the VRAM access also undergoes changes such as increase or decrease in the number of times of access.
  • the conventional access method generally employed a method in which an optimum combination is selected from among a plurality of setting conditions which has been previously assumed. For instance, a method was employed in which predetermined data formats each representing a cycle pattern to be a model are individually numbered for the storage in a register so that the CPU can specify the number.
  • the CPU In order to deal with the problem of increased amount of information of the image data to be written from the CPU, which will lead to a deficiency in write time, the CPU must be accessed as frequently as possible by effectively utilizing free time in the hardware access during the display period. It was however difficult in the conventional access circuit to flexibly set the CPU access time as needed since the access pattern which has been once determined were fixed unchangingly. In this manner, the conventional method in which the access patterns are fixedly set in the hardware had numerous restrictions to display a plurality of background images each having individual display setting.
  • VRAM-A and VRAM-B are respectively assigned to background images BG0 and BG1.
  • the background image BG1 is not displayed at all in scene A of a game, but appears in scene B of the same game.
  • the capacity of the VRAM-B for the background image BG1 in the scene A is merely a "necessary waste" actually out of use although it has been preset allowing for the possible use.
  • the VRAM-B is not permitted to be used for the background image BG0.
  • the conventional use of the VRAM capacity did not find a method providing an effective regulation for the VRAM capacity in accordance with the amount of image data which the respective background images contain as well as the conditions under which the background images are used.
  • the present invention was conceived in view of the above problems, a first object of which is to provide an image processing method capable of flexibly changing access actions within a unit time in a VRAM access in accordance with changes in display setting such as the number of colors of image data, a size reduction ratio, or an access frequency, without increasing an burden on the hardware.
  • a second object of the present invention is to provide an image processing method capable of, in accordance with the amount of image data of each background image and the access frequency, controlling the storage of the image data among a plurality of VRAM's.
  • a third object of the present invention is to provide an image processing method allowing the realization of the third object not merely between the plurality of VRAM's but also between a plurality of banks of the same VRAM.
  • a fourth object of the present invention is to provide an image processing system capable of setting and changing the access actions within a unit time in the VRAM access under the control of a CPU, and of distinctively outputting background images having different display conditions.
  • a fifth object of the present invention is to provide an image processing system ensuring an automatic and smooth execution in sequence of access actions within a preset unit time in the VRAM access.
  • a sixth object of the present invention is to provide an image processing system in which addresses of the image data on the VRAM are generated by calculation and selected for the supply to the VRAM in the VRAM access.
  • a seventh object of the present invention is to provide an image processing system having a configuration capable of specifying a predetermined action in the VRAM access and of executing the action promptly.
  • Ad eighth object of the present invention is to provide an image processing system realizing the seventh object without burdening the memory capacity.
  • a ninth object of the present invention is to provide an image processing system having a concrete configuration allowing an easy setting and change of VRAM access actions within a predetermined unit time.
  • a tenth object of the present invention is to provide an image processing system having a concrete configuration capable of controlling the VRAM access actions within the predetermined unit time by means of the CPU.
  • Ad eleventh object of the present invention is to provide an image processing system having a concrete configuration ensuring an automatic and smooth execution in sequence of access actions to the VRAM.
  • a twelfth object of the present invention is to provide an image processing system capable of easily implementing, under the control of the CPU, a configuration for allocating the VRAM capacity to the image data as well as changing the allocation.
  • a thirteenth object of the present invention is to provide an image processing system capable of setting and changing, under the control of the CPU, the access actions within a unit time in the VRAM access and capable of distinctively outputting the background images having different display conditions.
  • a fourteenth object of the present invention is to provide a game machine ensuring an automatic and smooth execution in sequence of access actions within a preset unit time in the VRAM access.
  • a fifteenth object of the present invention is to provide a game machine of a type in which addresses of image data on the VRAM are generated by calculation and selected for the supply to the VRAM in the VRAM access.
  • a sixteenth object of the present invention is to provide a game machine having a configuration capable of specifying a predetermined action in the VRAM access as well as of executing the action promptly.
  • a seventeenth object of the present invention is to provide a game machine accomplishing the sixteenth object without burdening the memory capacity.
  • An eighteenth object of the present invention is to provide a game machine having a concrete configuration capable of easily setting and changing the VRAM access actions within a predetermined unit time.
  • An nineteenth object of the present invention is to provide a game machine having a concrete configuration capable of controlling the VRAM access actions within a predetermined unit time by the CPU.
  • a twentieth object of the present invention is to provide a game machine having a concrete configuration in which the access to the VRAM is automatically and smoothly executed in sequence.
  • a twenty-first object of the present invention is to provide a game machine implementing, under the control of the CPU, a configuration for allocating the VRAM capacity to the image data and setting the change of the allocation.
  • an image processing method in which image data for forming a foreground image are stored into a frame buffer while simultaneously storing image data for forming background images into a video RAM and in which the image data for a foreground image are read from the frame buffer in a foreground image processing section in synchronism with the read of the image data for background images from the video RAM in a background image processing section, whereby at the same timing the foreground image and background images are generated and superimposed with each other to be output in the form of a synthetic image, the method comprising the steps of specifying the contents of concrete actions to be imparted to the video RAM in order to perform read and write of the background image data, setting the specified contents of actions at given unit time intervals, the setting being instructed by a CPU, and accessing the video RAM in conformity with an instruction from the CPU.
  • the invention defined in claim 2 provides an image processing method in which one ore more video RAM's are provided for storing image data for background images and in which the video RAM's store image data and are simultaneously accessed, the method comprising the steps of by means of a CPU, specifying the read of the video RAM's and image data stored in the video RAM's.
  • the video RAM defined in claim 2 is segmented into two banks which are plurality of RAM portions each having the same capacity, and the CPU specifies the read of the banks and image data stored in the banks.
  • an image processing system including a foreground image processing means which stores image data for forming a foreground image into a RAM and develops the image data into a frame buffer and at a predetermined timing reads out the image data for a foreground image from the frame buffer, a background image processing means which reads out image data for forming background images from a video RAM, a priority determining means which determines display priority among image data for a foreground image transferred from the foreground image processing means and image data for background images transferred from the background image processing means, and an output means which outputs the image data for a foreground image and background images in conformity with the priority, the system comprising, a specifying means for specifying actions reading or writing image data stored in the video RAM; a first setting means for setting at given unit time intervals the actions specified by the specifying means, a storage means for storing the contents of the actions set at given unit time intervals by the first setting means, an access control means for controlling
  • the access con trol means defined in claim 4 includes a conversion means for converting a specification by the specifying means into a control signal, and an address selection means for selecting an address on the video RAM of image data read out from the video RAM.
  • the address selection means defined in claim 5 includes a first generation means for generating an address on the video RAM of pattern name data, and a second generation means for generating an address on the video RAM of pattern data.
  • the image processing system defined in claim 4 uses an access command as a specification means for specifying the action reading or writing the pattern data or pattern name data.
  • the access command defined in claim 7 is a binary code consisting of a predetermined number of bits.
  • the image processing system defined in claim 7 sets a cycle pattern in the form allowing read-in by the CPU as a setting means for setting in one cycle unit during the display period the action specified by the access command.
  • the image processing system defined in claim 7 uses a video RAM access register as a storage means for storing the cycle pattern.
  • the image processing system defined in claim 7 executes access to the video RAM in conformity with the access command sequentially read from the cycle pattern stored in the access register.
  • the image processing system defined in claim 4 further comprises a second setting means for setting whether the video RAM is to be divided into a plurality of banks or not, and an access means allowing simultaneous access to the plurality of video RAM's or to the plurality of banks, by allocating a plurality of the storage means to each of the plurality of video RAM's or each of the plurality of banks of the video RAM.
  • a game machine including a foreground image processing means which stores image data for forming a foreground image into a RAM and develops the image data into a frame buffer and at a predetermined timing reads out the image data for a foreground image from the frame buffer, a background image processing means which reads out image data for forming background images from a video RAM, a priority determining means which determines display priority among image data for a foreground image transferred from the foreground image processing means and image data for background images transferred from the background image processing means, and an output means which outputs the image data for a foreground image and background images in conformity with the priority, the game machine comprising a specifying means for specifying actions reading or writing image data stored in the video RAM, a first setting means for setting at given unit time intervals the actions specified by the specifying means, a storage means for storing the contents of the actions set at given unit time intervals by the first setting means an access control means for controlling access
  • the access control means defined in claim 13 includes a conversion means for converting a specification by the specifying means into a control signal, and an address selection means for selecting an address on the video RAM of image data read out from the video RAM.
  • the address selection means defined in claim 14 includes a first generation means for generating an address on the video RAM of pattern name data, and a second generation means for generating an address on the video RAM of pattern data.
  • the game machine defined in claim 13 uses an access command as a specification means for specifying the action reading or writing the pattern data or pattern name data.
  • the access command defined in claim 16 is a binary code consisting of a predetermined number of bits.
  • the game machine defined in claim 16 sets a cycle pattern in the form allowing read-in by the CPU as a setting means for setting in one cycle unit during the display period the action specified by the access command.
  • the game machine defined in claim 16 uses a video RAM access register as a storage means for storing the cycle pattern.
  • the game machine accesses the video RAM in conformity with the access command sequentially read from the cycle pattern stored in the access register.
  • the game machine defined in claim 13 further comprises a second setting means for setting whether the video RAM is to be divided into a plurality of banks or not, and an access means allowing simultaneous access to the plurality of video RAM's or to the plurality of banks, by allocating a plurality of the storage means to each of the plurality of video RAM's or each of the plurality of banks of the video RAM.
  • the conditions include the number of colors used in each background image, scaling, the presence or absence of CPU access, and on-VRAM storage locations of image data required for each background image.
  • a cycle pattern of access to the VRAM for reading and writing image data is set for each of VRAM's arranged. That is, decided are access commands needed for one cycle, the number of times of access actions by these commands, and access timing.
  • a cycle pattern set in conformity with the above conditions is prepared in a software or a ROM, the contents being read by a CPU upon the execution of a game so as to allow a specification or change.
  • predetermined image data to be stored in each VRAM are set in advance, and the read of the image data can be specified by using the cycle pattern which is read by the CPU upon the execution of the game.
  • the above processing can be more freely set by a programmer familiar with the contents of a game program or various data and conditions used in the program. It is thus possible to set proper conditions, resulting in increased efficiency. Also, when changing such setting, it is merely required to change the software or ROM. This will allow an easy change of use of an idle area in the access time or VRAM capacity. Therefore, useless access time or useless VRAM capacity can be saved which have been hitherto fixedly set in the hardware regardless of possible no use.
  • the invention defined in claim 3 ensures an effective utilization of the limited VRAM capacity as well as read of plenty of image data from the VRAM.
  • allocation of image data of each background image to each bank would contribute to the increased number of background images to be displayed at one time.
  • use of the cycle pattern setting would allow a rational allocation of the VRAM capacity since it is possible to freely increase or decrease banks to be allocated to image data or the number of the banks.
  • the invention defined in claim 4 realizes an image processing system capable of flexibly changing, as needed, a cycle pattern in the VRAM access.
  • the specifying means specifies an access action it the VRAM.
  • the first setting means sets the contents of the access actions to be performed it a given unit time, and keeps the thus set contents of access in the form capable of being read into the CPU.
  • the CPU stores the read-in contents of access into the storage means.
  • the access control means controls the VRAM access referring to the stored contents of access.
  • the output bit control means performs an allocating operation based on the number of bits of image data in order to ensure a correct output of a plurality of background images whose respective image data have different amount of information. Thus, image data of the same background image can be output together.
  • the image processing system there can be obtained a configuration in which the contents of the access actions are read from the storage means in the VRAM access so that the access is controlled in accordance with the contents.
  • the information of the contents of access written into the storage means are divided into two portions, one for the kind of image data specified, the other for the specification of read and write, which are in synchronism transferred through two different paths to the VRAM. That is, the conversion means generates a read/write signal from the information of the access command, and designates the read or write of the specified image data.
  • the address selection means selects an address on VRAM of the specified image data, and delivers it to the VRAM.
  • the VRAM receives the address of the image data and the read/write signal to read the specified image data, and thereafter stores the image data into a predetermined data buffer.
  • the processing system by the kind of image data there can be generated addresses on VRAM of image data required for the read of the image data from the VRAM or for the write into the VRAM. More specifically, if the access command is "pattern name read", the first generation means generates the addresses on VRAM of the pattern name data and supplied them to the VRAM. On the contrary, if the access command is "pattern data read”, the second generation means generates addresses on VRAM of the pattern data and supplies them to the VRAM.
  • a predetermined access command is used as a specification means representing access actions such as read or write of both the pattern data which are image data of the background image to be stored in the VRAM and the pattern name data. This will allow a simple representation of each access action, contributing to a simple specification of setting or change in the access actions.
  • cycle patterns can be effectively and collectively set in the form allowing a read-in by the CPU, for example, in a CD-ROM, the cycle patterns each being a series of access actions set for each cycle during the display period.
  • the cycle patterns in the image processing system are stored in the VRAM access registers, allowing the control of the read and write by the CPU.
  • the invention defined in claim 12 realizes a concrete image processing system allowing an effective use of the VRAM capacity. That is, the second setting means sets whether the VRAM is to be divided into a plurality of banks or not. As a result of this, it can be determined depending on the amount of image data whether the whole of the VRAM capacity is to be used or a part thereof is to be used. Further, the access means accesses the VRAM or the VRAM banks at the same time. To be concrete, for each of VRAM's or the VRAM banks provided, a cycle pattern is set in accordance with the display conditions such as the amount of information of the image data stored therein and access frequency. This will accomplish a simultaneous display of a plurality of background images, and an increase in the amount of image data to be read, and an effective use of VRAM capacity.
  • the invention defined in claim 12 implements a game machine capable of flexibly changing, as needed, a cycle pattern in the VRAM access. That is, the specifying means specifies the access action in the VRAM. Then, using the specifying means, the first setting means sets the contents of the access actions to be performed in a given unit time, and keeps the thus set contents of access in the form capable of being read into the CPU. The CPU stores the read-in contents of access into the storage means. Further, the access control means controls the VRAM access referring to the stored contents of access. At that time, the output bit control means performs an allocating operation based or the number of bits of image data in order to ensure a correct output of a plurality of background images whose respective image data have different amount of information. Thus, image data of the same background image can be output together.
  • the contents of the actess actions are read from the storage means in the VRAM access so that the access is controlled in accordance with the contents.
  • the information of the contents of access written into the storage means are divided into two portions, one for the kind of image data specified, the other for the specification of read and write, which are in synchronism transferred through two different paths to the VRAM. That is, the conversion means generates a read/write signal from the information of the access command, and designates the read or write of the specified image data.
  • the address selection means selects an address on VRAM of the specified image data, and delivers it to the VRAM.
  • the VRAM receives the address of the image data and the read/write signal to read the specified image data, and thereafter stores the image data into a predetermined data buffer.
  • a predetermined access command is used as a specification means representing access actions such as writeout or read-in of both the pattern data which are image data of the background image to be stored in the VRAM and the pattern name data. This will allow a simple representation of each access action, contributing to a simple specification of setting or change in the access actions.
  • cycle patterns can be effectively and collectively set in the form allowing a read-in by the CPU, for example, in a CD-ROM, the cycle patterns each being a series of access actions set for each cycle during the display period.
  • the cycle patterns in the image processing system are stored in the VRAM access registers, allowing the control of the read and write by the CPU.
  • the invention defined in claim 12 realizes a concrete game machine allowing an effective use of the VRAM capacity. That is, the second setting means sets whether the VRAM is to be divided into a plurality of banks or not. As a result of this, it can be determined depending on the amount of image data whether the whole of the VRAM capacity is to be used or a part thereof is to be used. Further, the access means accesses the VRAM or the VRAM banks at the same time. To be concrete, for each of VRAM's or the VRAM banks provided, a cycle pattern is set in accordance with the display conditions such as the amount of information of the image data stored therein and access frequency. This will accomplish a simultaneous display of a plurality of background images, and an increase in the amount of image data to be read, and an effective use of VRAM capacity.
  • a configuration of an image processing system including a background image processing section of the present invention Assumed in the present embodiment are display screens for a foreground image and for a background image, on which images formed from image data are displayed. Among these display screens, one for the foreground image is referred to as a sprite screen, and one for the background images is referred to as a scroll screen.
  • Fig. 2 is a block diagram depicting an embodiment of an image processing system according to the present invention.
  • a CPU 1 a RAM 2, and a video processor 3 are linked to a bus 14 whose use permission is controlled by a bus controller 13.
  • the video processor 3 comprises a sprite engine 5, scroll engine 6, and a D/A converter 7.
  • To the sprite engine 5 are coupled a command RAM 8 and a frame buffer 9.
  • a scroll engine 6 includes therewithin a color RAM 10 and a variety of registers 11, and is coupled to a VRAM 12. Functions of the scroll engine 6 are set in the registers 11 by the CPU 1.
  • VRAM access register intended to store cycle patterns for controlling VRAM access actions during a display period
  • a monitor 4 is coupled to the video processor 3.
  • the CPU 1 stores into the RAM 2 a game program read from an external storage unit (not shown) such as a CD-ROM, and transfers to the video processor 3 read output image data together with commands or instructions needed for image processing.
  • the sprite engine 5 serving as an image processing section for foreground temporarily stores in the form of a command table in the command RAM 8 a foreground command transferred from the CPU 1.
  • the command is read by the sprite engine and set in an internal system register for execution.
  • image data for foreground also transferred from the CPU 1.
  • the sprite engine 5 reads the image data from the command RAM 8 for image processing such as rotation, scaling and color operation.
  • the image data are written into predetermined addresses on the frame buffer 9 to develop a dynamic picture for a foreground image.
  • the image data for background image FG in the frame buffer 9 are read in sequence by the sprite engine 5, and supplied to the scroll engine 6 directly without using the bus 14.
  • Fig. 3 depicts a configuration of the scroll engine 6 for forming background images.
  • the scroll engine 6 comprises a window control section 21 for window processing on the sprite and scroll screens, a background image generation section 22 (described later) for processing the image data on the scroll screen, and a display control section 23.
  • the display control section 23 includes a priority circuit 24 and a colorization circuit 25.
  • the display control section 23 judges an output priority on pixel-by-pixel basis to synthesize an image.
  • the image data are further colorized by a color RAM 10 coupled thereto.
  • the thus processed image data are transferred, along with RGB data generated in the colorization circuit 25, through a terminal B to the D/A converter 7 of Fig. 2.
  • the image data are converted into color video signals in analog representation, and then fed to the display 4 represented by a standard TV monitor.
  • the background image generation section 22 in particular is characterized in that it includes therewithin a variety of registers 11 allowing writing from the CPU 1 so as to perform both the control of VRAM access and the regulation of VRAM capacity to be allocated to the image data.
  • a VRAM access register is provided to allow the CPU to write the contents of access actions within one cycle (a cycle pattern) to be executed during the display period of the image data.
  • the background image generation section 22 is coupled to the VRAM 12 and comprises an access circuit 31 for controlling the VRAM access, a synchronous circuit 32, data buffers (registers 33 to 36) for temporarily storing image data to be read from the VRAM until they are output, image data output circuits (37 and 38), and a coordinate calculation section 39 for controlling the movement such as vertical and horizontal movement and rotation of the scroll screen.
  • the access circuit 31 includes a VRAM access register 40, a decoder 41, and an address selector 42.
  • a terminal C is linked to the CPU 1 to allow the supply of commands from a game program, image data, addresses of the image data and so on.
  • the synchronous circuit 32 generates horizontal and vertical synchronizing signals in synchronism with the scan of the monitor 4 as well as synchronizing signals on dot-by-dot basis. These synchronizing signals are fed through a terminal D to the sprite engine while simultaneously being supplied via the coordinate calculation section 39 to each parts of the back ground image generation circuit 22. This will allow the coincidence of position and timing in the output of the foreground images and background image.
  • the synchronous circuit 32 further generates address signals of one dot (pixel) cycle and supplies them to the VRAM access registers.
  • the image data on pixel-by-pixel basis generated in the image data output circuits 37 and 38 within the background image generation circuit 22 are provided as output to the display control section 23 of Fig. 3 by way of terminals E and F.
  • the following conditions by way of example need to be preset prior to the setting of a cycle pattern designating the contents of VRAM access within a unit time (one cycle).
  • This embodiment employs two scroll screens BG0 and BG1 for display, the scroll screen BG0 using 16 colors and the scroll screen BG1 using 256 colors. Also assume that these scroll screens are subjected to no size reduction, and that a single VRAM is not divided for use in storing image data. Further suppose there is no change in images with respective to the scroll screens and no need for CPU access time.
  • the VRAM access register 40 within the access circuit 31 consists of eight separate registers R1 to R8 each corresponding to one access time.
  • access commands are each composed of a four-bit binary code and serve to specify from which scroll screen the image date are to be read.
  • a cycle pattern is set by specifying these access commands at appropriate timing within one cycle.
  • the pattern data are comprised of cell-by-cell color codes each having a predetermined number of bits providing pixel color information among informations possessed by each pixel. With a cell configuration of eight pixels in vertical and horizontal directions, for example, the pattern data will contain color codes for 64 (8 x 8) pixels.
  • the number of times of access actions depends on the amount of information of the pattern data.
  • the amount of information of the pattern data in turn depends on the display conditions such as the number of bits of a color code per pixel contained in the pattern data and the size reduction ratio.
  • the color code per pixel contained in the pattern data is four bits long. Accordingly, 16-bit pattern data read by one access action contain color codes for four pixels.
  • the predetermined amount of pattern data to be read by the VRAM access is for eight pixels (in the horizontal row of a cell). Therefore, two consecutive access actions are required in order to read the pattern data in the scroll screen BG0, which will necessitate two consecutive setting of "BG0 pattern data read”.
  • the cycle pattern as described above is set in a manner capable of being read in by the CPU.
  • Setting means includes, for example, a method in which an optimum cycle pattern is determined by a unique program, or a method in which a previously prepared cycle pattern is specified into a CD-ROM, a memory cartridge or the life.
  • the cycle pattern is read from the setting means by the CPU, and then stored from the CPU into the VRAM access register 40.
  • Fig. 4 depicts, by way of example, a cycle pattern stored in the registers within the VRAM access register.
  • the VRAM access register of Fig. 1 consists of eight registers R1 to R8 and receives address signals of one dot (pixel) period from the synchronous circuit 32.
  • the address signals sequentially designate addresses in the VRAM access register of the eight registers.
  • the VRAM access register 40 reads out in sequence access commands stored in the registers designated by the address signals. The thus read access commands are decoded in the decoder 37, and resultant read/write control signals are fed to the address selector 42 and the VRAM 12.
  • addresses in the VRAM of the image data requiring read or write are selected and fed to the VRAM. Detailed description will be given hereinbelow of the operation of generating addresses of the image data to be supplied to the VRAM.
  • pattern name read For reading out the pattern name data of the scroll screens, first generated are addresses on the VRAM 12 of the specified pattern name data (pattern name addresses).
  • pattern name addresses The operation of generating the pattern name addresses is as follows.
  • the coordinate calculation section 39 of Fig. 1 receives from the synchronous circuit 32 vertical and horizontal synchronizing signals of the scroll screens BG0 and BG1 as well as dot (pixel)-period synchronizing signals.
  • the coordinate calculation section 39 subjects the scroll screens BG0 and BG1 to processing such as vertical and horizontal movement or rotation. Such processing is needed in the case of representing the action of an airplane by rotating or moving the background images with the position of the airplane remaining fixed, such as for example, when desiring to represent the state on the earth viewed from the airplane flying through the air.
  • the coordinate calculation section 39 performs coordinate calculations pixel by pixel in accordance with both the synchronizing signals from the synchronous circuit 32 and the instructions of the CPU 1 received through the terminal C.
  • a pixel address coordinate values of each pixel on the scroll screens are referred to as a pixel address.
  • the pixel address has coordinate data consisting of, for example, X-coordinate of nine bits (X0 - X8) and Y-coordinate of nine bits (Y0-Y8).
  • XY coordinate data upper six bits (X3 - X8, Y3 - Y8) except lower three bits (X0 - X2, Y0 - Y2) are data representing a position on the scroll screen of a cell as shown in Fig. 5(d).
  • the X and Y coordinate data are combined with the exception of their respective lower three bits, to generate 12-bit pattern name address (X3 - X8 / Y3 - Y8) for the supply to the address selector 42.
  • the lower three bits (X0 - X2, Y0 - Y2) of the X and Y coordinates, among the coordinate data of the pixel address, are respectively used to represent, by the combination of codes 0 or 1 possessed by these bits, X and Y coordinate values of 64 pixels in a cell consisting of 8 x 8 pixels in vertical and horizontal directions.
  • X and Y coordinate values 64 pixels in a cell consisting of 8 x 8 pixels in vertical and horizontal directions.
  • control signals representing the number of bits of a color code for each pixel as shown in Fig. 5(c).
  • the image data output circuit 37 for the scroll screen BG0 (four-bit color code), but to the image data output circuit 38 for the scroll screen BG1 (eight-bit color code).
  • the Y-coordinate lower three bits (Y0 - Y2) are fed to the address selector 42 intact and used as data in generating pattern data addresses.
  • the address selector 42 receives 12-bit pattern name addresses fed from the coordinates calculation section 39 as well as addresses of the VRAM 12 supplied through the terminal C. On the basis of the addresses of the VRAM 12, the address sector 42 accesses the VRAM 12 to impart the pattern name addresses to the VRAM 12.
  • the VRAM 12 is coupled, for each of the scroll screens, to a plurality of data buffers corresponding to the kinds of the image data.
  • the register 33 is a buffer for storing pattern name data for the scroll screen BG0
  • the register 34 is a buffer for storing pattern name data for the scroll screen BG1.
  • the VRAM 12 is supplied with pattern name addresses from the address selector 42, and reads pattern name data based on the addresses. In synchronism with this, the VRAM 12 is fed with control signals (write) from the decoder 41 whereupon the thus read pattern name data if associated with the scroll screen BG0 are stored into the register 33, and if associated with the scroll screen BG1 into the register 34.
  • the access command "pattern name read" in the VRAM access is put into execution, so that pattern name data are read and stored into the predetermined data buffer.
  • the access circuit 31 After the completion of the readout of the pattern name data, the access circuit 31 reads the subsequent access command in accordance with the cycle pattern stored in the VRAM access register 40. In other words, the access circuit 31 starts to read the pattern data which are cell-by-cell color data for output.
  • pattern data read The following is a description of the procedure when the access command has advanced to "pattern data read".
  • the decoder 41 supplies control signals (read) to the registers 33 and 34.
  • pattern name data are read from the register 33 (for the scroll screen BG0) or alternatively from the register 34 (for the scroll screen BG1) and sent to the address selector 42.
  • the pattern name data typically contain in its lower nine bits a leading address of pattern data in the scroll screen (or the VRAM 12). The leading address serves to specify which cell to be read.
  • the address selector 42 receives lower three bits (Y0 - Y2) of Y-coordinate data for specifying eight Y-coordinate values within a cell, among the lower three bits of X and Y coordinate data from pixel addresses generated through the procedure 2.
  • the lower three bits of Y-coordinate data serve to specify Y-coordinates of pixels within a cell.
  • a pattern data address is generated in the form of 12 bits obtained by combining the leading address with the lower three bits of the Y-coordinate data.
  • the pattern data address functions to specify one of the eight horizontal rows within the cell.
  • to the pattern data address are affixed a predetermined number of bits designating which read access action has read the pattern data specified by the address.
  • the address selector 42 is fed with 12-bit pattern data addresses of the pattern data on the VRAM 12 generated through the procedure 5, as well as addresses of the VRAM 12 supplied from the CPU 1 through the terminal C. Based on the addresses of the VRAM 12, the address selector 42 accesses the VRAM 12 to impart the pattern data addresses to the VRAM 12.
  • the VRAM 12 is coupled, for each of the scroll screens, to a plurality of data buffers for pattern data.
  • the register 35 is a buffer for storing pattern data for the scroll screen BG0
  • the register 36 is a buffer for storing pattern data for the scroll screen BG1.
  • the VRAM 12 is supplied with pattern data addresses from the address selector 42, and reads pattern data on the basis of the addresses. In synchronism with this, the VRAM 12 is fed with control signals (write) from the decoder 41 whereupon the thus read pattern data if associated with the scroll screen BG0 are stored into the register 35, and if associated with the scroll screen BG1 into the register 36.
  • the access command "pattern data read” in the VRAM access is put into execution, so that pattern data are read and stored into the predetermined data buffer.
  • the image data output circuits 37 and 38 receive from the coordinate calculation section 39 both control signals for specifying the number of bits of pixel color codes and lower three bits (X0 - X2) of pixel address X-coordinate data. If control signal specifies four bits, the image data output circuit 37 is allowed to receive pattern data for two words (32 bits) read out from the register 35 for scroll screen BG0 (using 16 colors). These are pattern data for eight pixels in the horizontal row of a cell read by two access actions in accordance with the cycle pattern. As depicted in Fig. 7(a1), the pattern data for eight pixels are segmented into eight portions (P0 - P7) every four bits from the lowest or rightmost bit.
  • the X-coordinate lower three bits select one of eight-segmented four-bit data.
  • one of X-coordinate values in a horizontal row is selected to specify one pixel of the eight pixels in the horizontal row.
  • a color code for one pixel within the pattern data is specified.
  • the image data output circuit 38 is allowed to receive pattern data for four words (64 bits) read from the register 34 for the scroll screen BG1 (using 256 colors). These are pattern data for eight pixels in the horizontal row read by four access actions in accordance with the cycle pattern. As shown in Fig. 7(a2), the pattern data for eight pixels are segmented into eight portions (P0 to P7) every eight bits from the lowest or rightmost bit.
  • the X-coordinate lower three bits selects one of the eight-segmented eight-bit data. In other words, one of X-coordinate values in a horizontal row is selected to specify one pixel of the eight pixels in the horizontal row. Thus, a color code for one pixel within the pattern data is specified.
  • the pixel-by-pixel image data thus formed are output from the image data output circuits 37 or 38 via the terminal E or F into the priority circuit 24 of the display control section 23 of Fig. 3.
  • the access circuit of the present invention specifies access actions in the VRAM access using access commands in a predetermined form. Further, a cycle pattern is set in such a manner as to allow read into the CPU and is stored in such a manner as to allow write from the CPU, the cycle pattern setting an access command for eight access actions in one cycle of unit time. As a result, in the case of changing the cycle pattern, it is merely required to specify an access command rewriting work by the CPU. Also, in the case of providing additional VRAM access registers so as to correspond to a plurality of VRAM's, it is merely required to appropriately modify and set the access command by the CPU, thus making it possible to flexibly cope with such situation.
  • the present invention is not intended to be limited to the above embodiment.
  • the present invention will rather allow an implementation of an access circuit having a flexible configuration in conformity with the original aim and need.
  • Other reference examples will be described hereinbelow.
  • the access circuit of the present invention is provided with additional VRAM's as needed, and with additional access registers corresponding to the VRAM's. Providing that the VRAM's are now allocated to image data for each of the scroll screens, it is possible as shown in Fig. 8 to set CPU access in one cycle even with the scroll screen BG1 using a multiplicity of colors, thus enabling new image data to be written from the CPU during the display period. Since the VRAM's and associated access registers can be additionally provided in this manner, there is no need to fixedly set useless access time which may not possibly be used to the hardware as in the prior art. In this context, burden imposed on the hardware will be alleviated.
  • the image processing system of the present invention allows not only a simultaneous access to the plurality of VRAM's or VRAM banks but also a free setting of VRAM capacity allocation for each of the scroll screens by means of the CPU in previous consideration of, for instance, the quantity of the image data possessed by each scroll screen, or the difference in the states of use of the VRAM depending on the access frequency.
  • Three scroll screens BG0, BG1 and BG2 are present.
  • the number of colors used in the scroll screen BG2 especially increases.
  • the scroll screen BG1 needs to be subjected to many display changes, the scroll screen BG2 being not displayed at all.
  • VRAM-1 and VRAM-2 two VRAM's of the present invention are provided and named VRAM-1 and VRAM-2, respectively.
  • a setting is performed for halving VRAM-1 into two banks. This depends on whether one bit within the register for controlling the RAM is 0 or 1.
  • image data of the scroll screen BG0 and scroll screen BG1 for the scene A are stored in the VRAM-2 not subjected to bank division.
  • respective VRAM's are correspondingly associated with the access registers to individually set the cycle pattern to read the image data at the scene A.
  • the image data for the scene B of the scroll screen BG0 are stored into the back 1a within the VRAM-1. Then the contents of the cycle pattern for the VRAM-1 are changed into ones for the read of the image data of the scroll screen BG0. Also, into the VRAM-2 are stored image data of the scroll screen BG1 for the scene B. Then, the contents of the cycle pattern of the access register for the VRAM-2 are changed into ones for the read of the image data of the scroll screen BG1. As a result of this, in the scene B, more CPU access time can be allocated to the image data of the scroll screen BG1.
  • the VRAM capacity can be saved with respect to the scroll screen BG2 which is not displayed at all in the scene B.
  • the present invention ensures an easy change of setting of the cycle pattern and hence the free and appropriate control of the allocation of the VRAM capacity in accordance with the amount of information of the image data or the necessity of access. This will contribute to an effective application of the restricted VRAM capacity.
  • the cycle pattern upon the VRAM access which may vary depending on the display conditions can be more freely set and changed, thus providing an image processing system and a game machine having a higher degree of freedom allowing changeful image display.
  • an image processing system and a game machine can be provided capable of saving the VRAM capacity by appropriately determining the amount of information of the image data required for each of the background image, without depending on the fixed cycle pattern. Also, an image processing system and a game machine can be provided which enables the allocation of the VRAM capacity to be varied in accordance with the amount of information of the image data.

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