Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N7/00—Television systems
  • H04N7/12—Systems in which the television signal is transmitted via one channel or a plurality of parallel channels, the bandwidth of each channel being less than the bandwidth of the television signal
  • H04N7/122—Systems in which the television signal is transmitted via one channel or a plurality of parallel channels, the bandwidth of each channel being less than the bandwidth of the television signal involving expansion and subsequent compression of a signal segment, e.g. a frame, a line
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N7/00—Television systems
  • H04N7/12—Systems in which the television signal is transmitted via one channel or a plurality of parallel channels, the bandwidth of each channel being less than the bandwidth of the television signal
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
  • H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
  • H04N19/587—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal sub-sampling or interpolation, e.g. decimation or subsequent interpolation of pictures in a video sequence
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
  • H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
  • H04N19/59—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving spatial sub-sampling or interpolation, e.g. alteration of picture size or resolution
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
  • H04N19/90—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals

Definitions

• the present invention relates to an image processing system particularly, although not exclusively, envisaged for use in reducing the bandwidth requirements for transmission of video signals (i.e. for high definition television(HDTV) , TV, video and video-phones), increasing the resolution of a video picture for a given bandwidth (HDTV) and in digitising ' signals for storage onto video cassette tapes.
• video signals i.e. for high definition television(HDTV) , TV, video and video-phones
• HDTV high definition television
• the present invention is able to do this by taking into consideration the psychophysical attributes of the human visual perception system, namely BETA APPARENT MOVEMENT and SUPER EDGING (the Julesz stereopsis experiment) .
• Synchronisation achieved by sequentially scanning video pictures starting at the top left of the frame and progressing to the bottom right on a line by line basis, and repeating the process for subsequent frames.
• the BETA effect was u ⁇ ed in Au ⁇ tralian Patent No. 493435 where, instead of relying on large number ⁇ of pixel ⁇ in order to di ⁇ play graphical images of high resolution, the BETA effect was simulated and the human visual system was tricked into perceiving a resolution much higher than was actually being displayed.
• the channel would need to be able to handle a rate of 1,562,500 x 8, or approximately 12.5 megabit ⁇ , 25 times each second! This is equivalent to 12.5 x 25 i.e. 312.5 mega bit/sec.
• the challenge is to reduce this data rate to the capabilities of ISDN network communication speeds of the order of 64 kb/sec.
• the first step in handling ⁇ uch a huge task i ⁇ to implement a ⁇ y ⁇ tem which can compress the picture, free it of any redundant information, and further reduce transmission times by sending only the field and block differences rather than the whole field information.
• This is the intention of the proposed CCITT H261 JPEG/MPEG document covering the Discrete Cosine Transform (DCT), Motion Estimation Prediction (MEP) and ancillary algorithms.
• the BETA APPARENT MOVEMENT effect (the BETA effect) ;
• Two dimensional interlacing
• the present invention relies on these techniques to enable considerable depletion of an image without causing significant los ⁇ of visual intelligibility of the image.
• the BETA effect is used in a scanning and raster technique which work ⁇ equally well whether the video image is stationary or moving and is referred to as a DEPLETION OPTIMISATION TECHNIQUE raster (DOT ra ⁇ ter) .
• the DOT ra ⁇ ter adopt ⁇ the BETA effect described in Australian patent 493435, except that, instead of requiring the video image to move with respect to a plurality of spaced apart stationary column ⁇ of video element ⁇ , a ra ⁇ ter of column ⁇ are moved backward ⁇ and forward ⁇ with re ⁇ pect to a fixed or moving video image. Hence, the pixel ⁇ are moved backwards and forwards to create apparent movement - even in still video image ⁇ .
• Thi ⁇ i ⁇ equivalent to taking the picket fence analogy of Au ⁇ tralian patent 493435 and moving the picket fence with respect to the video image instead of moving the video image with respect to the stationary picket fence.
• the effect can be simulated by clo ⁇ ing one eye, ⁇ preading your finger ⁇ slightly apart and waving them in your field of view.
• a row ra ⁇ ter can ⁇ imultaneou ⁇ ly be used to provide a horizontal depletion - to create a two dimensional interlace raster, as shown in Figure la.
• the raster movement of the pixel ⁇ doe ⁇ not have to be limited to linear movement in rows and column ⁇ , but can be random in 2 dimen ⁇ ions, as shown in Figure lb.
• the DOT raster produces highly viewable video images even where the fields are reduced from 625 to 64 picture columns, each with only 128 out of 625 vertically arranged picture element ⁇ (pixels). This represent ⁇ a horizontal depletion of 10:1 and a vertical depletion of 4:1, giving an overall depletion of 40:1. That i ⁇ , each field is depleted by 40:1, but a time separated interlace of a plurality of the fields which build up a full video image having a resolution of 625 x 625 pixels.
• the horizontal resolution which can be achieved is not dependent upon the number of pixels in a single field, but is dependent on the number of unique positions that the DOT raster can acquire over time.
• the columns can be broken up and rearranged into a two dimensional interlaced array (a checker board pattern a ⁇ ⁇ hown in Figure ⁇ 2a, 2b and 2c).
• Thi ⁇ ha ⁇ the effect of allowing the entire image to build up over a number of field ⁇ and to reduce the tendency for the viewer to lock onto the moving checker board.
• the DOT raster does not preclude the use of other data compression techniques such as Discrete Cosine Transform (DCT) and motion prediction algorithms. Hence, even greater ⁇ aving ⁇ in bandwidth are possible.
• DCT Discrete Cosine Transform
• the increase in sharpness can be explained by a consideration of the SUPER EDGING effect (see Figures 3a and 3b), where any random structure improves the sharpness of an image, this is the property of the viewer to "see" non ⁇ existent details between certain point ⁇ .
• the edge ⁇ of the shapes shown in Figure ⁇ 3a and 3b appear extremely sharp even though the edges are formed from a random arrangement of pixels. The sharpne ⁇ s of the edges in the ⁇ e examples would be unobtainable by ⁇ imple connecting lines.
• an object of the pre ⁇ ent invention to provide an image proce ⁇ ing ⁇ y ⁇ tem relying upon the BETA APPARENT MOVEMENT effect to enhance the perceived re ⁇ olution of a video image.
• an image proce ⁇ sing sy ⁇ tem having: interlocking means for interlacing the pixel ⁇ of subsequent fields of pixels horizontally; whereby, the interlacing causes the pixels to move backwards and forwards at a rate substantially imperceptible to a human viewer for creating a perceived resolution of a video image formed by a plurality of the fields so interleaved, wherein the perceived resolution is greater than the actual resolution.
• an image processing system for compressing a video image referred to as an oniginal video image
• the image processing system comprising: a digitiser mean ⁇ for digitising the original video image, the original video image being formed of a plurality of original video fields each having M rows of pixel ⁇ and N column ⁇ of pixel ⁇ ; and, a process control means for proces ⁇ ing the digitised original fields, the proces ⁇ control mean ⁇ ⁇ electing one pixel out of every d pixels and for deleting the remainder of the d-l pixels for generating depleted field ⁇ in a depleted video image, the depleted field having m row ⁇ of pixel ⁇ and n column ⁇ of pixel ⁇ where m is less than M and n is les ⁇ than N; whereby, a receiver means can receive the depleted video image and can generate d-l pixel ⁇ from each selected pixel and can display each selected pixel and its a ⁇ sociated d-l generated pixel ⁇ in a manner to
• a method for compre ⁇ sing a video image referred to as an oniginal video image the method compri ⁇ ing the steps of: digitising a field of the original video image into a plurality of data bytes referred to a ⁇ pixel ⁇ , each original video field having M row ⁇ of pixel ⁇ and N column ⁇ of pixel ⁇ ; selecting one pixel out of every d pixel ⁇ ; deleting the remainder of the d-l pixel ⁇ ; and, generating a depleted field of pixels in a depleted video image, the depleted field having m row ⁇ of pixel ⁇ and n column ⁇ of pixel ⁇ where m i ⁇ le ⁇ than M and n i ⁇ less than N; whereby, a receiver means can receive the depleted video image, generate d-l pixels from each ⁇ elected pixel and di ⁇ play each ⁇ elected pixel and its associated d-l generated pixels on a di ⁇ play mean ⁇ in a manner to simulate movement
• an image proce ⁇ ing ⁇ y ⁇ tem for decompressing a video image referred to a ⁇ a depleted video image
• the image processing system comprising: a digitiser means for digitising the depleted video image, the depleted video image being formed of a plurality of depleted video fields each having m rows of pixels and n columns of pixel ⁇ ; and, a proce ⁇ control mean ⁇ for proce ⁇ ing the digitised depleted fields, the proce ⁇ control mean ⁇ generating d-l pixel ⁇ from each selected pixel and displaying each selected pixel and its as ⁇ ociated d-l generated pixel ⁇ over a period of time imperceptible to a viewer for ⁇ imulating movement of the pixels on a display to regenerate an original video image having M rows of pixels and N column ⁇ of pixels; wherein, the process controller relies upon the BETA APPARENT MOVEMENT effect in regenerating the original video image.
• a method for decompressing a video image referred to as a depleted video image the method compri ⁇ ing the ⁇ teps of: digitising the depleted video image, the depleted video image being formed of a plurality of depleted video fields each having m rows of pixel ⁇ and n columns of pixels; selecting a pixel from the depleted video image; generating d-l pixel ⁇ from each selected pixel; displaying each selected pixel and it ⁇ associated d-l generated pixels over a period of time imperceptible to a viewer for ⁇ imulating movement of the pixels on a display means for reconstructing an original video image with the selected pixels and the generated pixels, the reconstructed video image having M rows of pixels and N columns of pixels, where M is greater than m and N in greater than n; wherein, the simulated movement relies upon the BETA APPARENT MOVEMENT effect in reconstructing the original video image.
• luminance determining means is provided to determine the luminance of the adjacent pixels and to set the luminance component of the pseudo pixel to a value proximate the actual value but different enough so a ⁇ to induce an observer' ⁇ perception sy ⁇ tem to ⁇ elect vi ⁇ ually the mo ⁇ t probable value.
• Figure la shows a two dimensional interlace of pixel ⁇ , being in an ODD field "0" and an EVEN field "E";
• Figure lb shows a two dimensional random raster movement of pixels for a modulo-3 raster ⁇ cheme
• Figures 2a to 2c show the break-up of a plurality of columns of video (Figure 2a) into a single depleted field (Figure 2b) and into two interlaced depleted fields (Figure 2c);
• Figures 3a and 3b are diagrams showing the effect known a ⁇ SUPER EDGING in relation to a ⁇ quare and a triangle;
• Figures 4a and 4b are diagra ⁇ ⁇ howing the effect known a ⁇ FILLING-IN in relation to a triangle;
• Figure 5 i ⁇ a block diagram of an image proce ⁇ ing ⁇ y ⁇ tem in accordance with the pre ⁇ ent invention
• Figure 6 i ⁇ a block diagram of a receiver of the image proce ⁇ ing sy ⁇ tem shown in Figure 5;
• Figure 7 is a block diagram showing a transmitter of the image proces ⁇ ing ⁇ y ⁇ tem shown in Figure 5;
• Figure 8 is a graphical representation of a two interlaced regenerated fields U and G of the receiver shown in Figure 6; and,
• Figure 9 shows a modulo-4 raster ⁇ cheme.
• the image proce ⁇ ing system 9 comprises a transmitter 10 and a receiver 12, shown in Figure ⁇ 6 and 7 re ⁇ pectively.
• a CODEC 14 is connected to an output of the transmitter 10 and another CODEC 16 is connected to an input of the receiver 12.
• a video ⁇ ource 18 is connected to an input of the tran ⁇ mitter 10 and a video monitor 20 i ⁇ connected to an output of the receiver 12.
• the receiver 12 ha ⁇ a video ⁇ ignal conditioner 32a and a sync separator 32b connected to a video input 33 which is connected to the CODEC 16.
• the sync ⁇ eparator 32b i ⁇ connected to a clock circuit 32c and a timing controller 32d which controls a clock timer 32e.
• the clock circuit 32c typically operates at a frequency of 12 megahertz and is hereinafter referred to as the "pixel clock" 32c.
• the video conditioner 32a is connected to an analogue digital converter 34a and thereby to a field store 34b.
• the output of the field store 34b is typically an 8-bit databus which is shown as a thick line in Figure 6.
• the field store 34b i ⁇ connected to a delay circuit 34c and thereby to an 8-bit latch 34d.
• the delay of the delay circuit 34c i ⁇ typically about 1 micro ⁇ econd ⁇ o a ⁇ to enable correct ⁇ yncing.
• the 8- bit latch 34d typically ha ⁇ a refresh rate of about 5 million times per second.
• the sync and colour subcarrier components are extracted from the video signal at the video input 33 by a colour extractor 32 connected to the video input 33.
• the colour extractor 32 i ⁇ connected to a colour processor 34 which typically includes a control circuit ⁇ ubstantially the same a ⁇ the remainder of the receiver 12.
• the colour extractor 34 operate ⁇ on ⁇ tandard B-Y and R-Y ⁇ ignal ⁇ ⁇ ent in the video signal from the transmitter 10.
• the B-Y and R-Y ⁇ ignal ⁇ are at a reduced re ⁇ olution, ⁇ uch a ⁇ half the re ⁇ olution of the video ⁇ ignal proce ⁇ ed by the pixel processor 26 (the compres ⁇ ed Y ⁇ ignal).
• the analogue to digital converter 34a and the field store 34b digitise the video luminance signal from the video conditioner 32a.
• the analogue to digital converter 34a generates digital values corre ⁇ ponding to the luminance of each pixel (hereinafter referred to as the "pixels") "on the fly” as the luminance ⁇ ignal is p-ocessed by the video conditioner 32a.
• the pixel ⁇ are then ⁇ tored in the appropriate memory address of the field store 34b.
• the luminance for each pixel is determined to be, for example, one of 256 luminance levels per pixel depending on the instantaneous voltage of the video signal (i.e. one in 2 8 ) .
• the field store 34b collect ⁇ one full field of the luminance ⁇ ignal and ⁇ tore ⁇ it for further processing. That is, consider that the receiver 12 operates one field behind the incoming video signals at the video input 33.
• the clock circuit 32c controls the timing of the analogue to digital converter 34a so a ⁇ to digitise the signal received from the video conditioner 34a at the appropriate time to correspond to each pixel location of the video source 18.
• the ⁇ ync ⁇ eparator 32b re-aligns the clock circuit 32c at the beginning of each line of the video signal by use of the horizontal sync signal contained therein.
• the outputs of the field ⁇ tore 34b and the 8-bit latch 34d are connected to a pixel proce ⁇ or 36.
• the pixel proce ⁇ or 36 ha ⁇ a proce ⁇ controller 36a connected to latche ⁇ and buffer ⁇ 36c, 36d and 36e.
• the latch and buffer 36c is connected to an ALU unit 38c and thereby to a latch and buffer 38d.
• the clock timer 32e is connected to the 8- bit latch 34d, the latches and buffers 36c, 36d, 36e and 38d.
• the clock timer 32e combines the clock and sync signal ⁇ from the ⁇ ync ⁇ eparator 32b and the clock circuit 32c for controlling the timing of the pixel proce ⁇ or 36.
• the proce ⁇ controller 36a reads the pixels from the field store 34b and allows them to proceed to the latch and buffer 36d. Also, the proce ⁇ controller 36a can allow pa ⁇ age of the pixel ⁇ to the latch and buffers 36c and 36e.
• the pixels which pa ⁇ to the latch and buffer 36d correspond to those un-depleted pixels which were tran ⁇ mitted to the receiver 12.
• a pseudo noise generator 38a is connected to the
• the pseudo noise generator 38a allow ⁇ injection of noise pixels into the video image di ⁇ played on the monitor 20.
• the p ⁇ eudo noi ⁇ e generator 38a typically generates pixels with luminance values which have a random value between the values of the adjacent pixels.
• the outputs of the latches and buffer ⁇ 36d, 36e and 38d are connected to a digital to analogue converter 40 which i ⁇ connected to a video output 42 and hence to the monitor 20.
• the pixel from the latches and buffers 36d, 36e and 38d are recombined with the colour information at the digital to analogue converter 40 via the colour proces ⁇ or 34 and with the ⁇ ync information from the ⁇ ync ⁇ eparator 32b hence forming a video signal corresponding to a regenerated video field for display on the monitor 20.
• the proce ⁇ controller 36a reads pixels from the field store 34b one at a time in sequential order, corre ⁇ ponding to row ⁇ of the video signal from the video source 18 i.e. Ull, U13,...Ul,n (where n is the number of columns) a ⁇ ⁇ hown in Figure 8. However, once the pixel ⁇ Ull, U13...Ul,n have been read the proce ⁇ controller 36a generate ⁇ pixel ⁇ G12, G14,...Gln-l and sends them to the latch and buffer 36d before their each of as ⁇ ociated pixels Ull, U13,...Uln are ⁇ ent to the latch and buffer 36d via the 8-bit latch 34d.
• the proce ⁇ controller 36a generates the pixels between the un-depleted pixels from the video signal as it reads the un-depleted pixel ⁇ and ⁇ end ⁇ each generated pixel for di ⁇ play before it ⁇ end ⁇ the la ⁇ t pixel read from the field store 34b to the latch and buffer 36d.
• the pixel ⁇ are referred to a ⁇ "un-depleted pixel ⁇ " because they are the pixel ⁇ which remain after the depletion proce ⁇ of the transmitter 10, described hereinafter.
• the control processor 36a generates the generated pixel ⁇ G by con ⁇ idering the luminance value ⁇ (between and 0 and 255) of the last two pixels read from the field store 34b and makes the generated pixel luminance value ⁇ tatistically dependent thereon.
• the value of the generated pixel could be a polynomial interpolation of the values of the two un-depleted pixels.
• the value could be a random value with the values of the two depleted pixels as its upper and lower limits.
• the process controller passes control to the latch and buffer 36c and the pixel is generated by the pseudo noise generator 38a and sent to the DAC 40 via the latch and buffer 38d.
• the process controller 36a then reads the pixels U31, U33,...U3,n of row three of the video image. These are the next pixels in the field store 34b.
• the control proce ⁇ or 36a al ⁇ o generate ⁇ the pixel ⁇ G32, G34, ...G3n+1.
• the control proce ⁇ or 36a generate ⁇ the pixels G21, G22,...G2n for the line of pixels between the first and third lines of pixels read from the field store 34b.
• each depleted field commences with only 312 out of 625 pixels acro ⁇ and 312 out of 625 pixel ⁇ down in each column but re ⁇ ult ⁇ in a full 625 line video ⁇ ignal.
• each depleted field had only one quarter of the pixels of the original field and the receiver 12 regenerates the other three quarters of the pixels, as shown graphically in Figure 8.
• the above de ⁇ cription relate ⁇ to a modulo-2 depletion of the pixels of the original video signals. It amounts to a horizontal and vertical interlace of two fields, namely Un,m/Gn,m and un,m/gn,m.
• the horizontal interlace has the effect of moving the image back and forth behind "a picket fence" and hence induces the BETA effect to give the illu ⁇ ion of higher than actual re ⁇ olution to the viewer.
• the vertical interlace give ⁇ higher vertical re ⁇ olution.
• the transmitter 10 ha ⁇ a tran ⁇ mi ⁇ ion ⁇ ignal conditioner 22a and a ⁇ ince ⁇ eparator 22b connected to a video input 23 which i ⁇ driven by the video ⁇ ource 18 (such as a video camera or HDTV program or VCR or the like).
• the ⁇ ync separator 22b is connected to a clock circuit 22c and a timing controller 22d which controls a clock timer 22e.
• the clock circuitry 22c typically operates at a frequency of 12 megahertz and is hereinafter referred to as the pixel clock 22c.
• the video conditioner 22a is connected to an analogue digital converter 24a and thereby to a field store 24b.
• the output of the field store 24b is typically an 8-bit databus which i ⁇ ⁇ hown a ⁇ a thick line in Figure 7.
• the field ⁇ tore 24b is connected to a delay circuit 24c and thereby to an 8- bit latch 24d.
• the delay of the delay circuit 24c is typically about 1 microsecond ⁇ o a ⁇ to enable correct syncing.
• the 8-bit latch 24d typically has a refresh rate of about 5 million times per ⁇ econd.
• the signal conditioner 22a extracts the luminance component from the video signal.
• a colour extractor 22 extracts the colour component from the video signal received from the video source 18.
• the colour extractor 22 i ⁇ connected to a colour proce ⁇ or 27 which typically includes a control circuit substantially the same as the remainder of the transmitter 10.
• the colour extractor 27 operates on standard B-Y and R-Y signals sent in the video signal from the tran ⁇ mitter 10.
• the B-Y and R-Y ⁇ ignal ⁇ are at a reduced re ⁇ olution, such a ⁇ half the re ⁇ olution of the video ⁇ ignal processed by the pixel processor 26 (the compres ⁇ ed Y signal) .
• the analogue to digital converter 24a and the field store 24b digitise each field received from the video source 18 and store it for digital proces ⁇ ing.
• the analogue to digital converter 24a generate ⁇ digital values of the luminance of each pixel , (hereinafter referred to as "pixels") "on the fly" as the luminance signal is processed by the video conditioner 22a.
• the luminance is determined to be, for example, one of 256 luminance levels per pixel (i.e. one in 2 8 ) .
• the clock circuit 22c controls the timing of the analogue to digital converter 24a so a ⁇ to digitise the signal received from the video conditioner 24a at the appropriate time to correspond to each pixel location of the video source 18.
• the sync separator 22b re-aligns the clock circuit 22c at the beginning of each line of the video signal by use of the horizontal sync ⁇ ignal contained therein.
• the pixel processor 26 has a proces ⁇ controller 26a connected to latches and buffers 26c and 26d.
• the latch and buffer 26c is connected to an ALU unit 28a and thereby to a latch and buffer 28b.
• the clock timer 22e is connected to the 8-bit latch 24d and the latches and buffer ⁇ 26c, 26d and 28b.
• the clock timer 22e combines the clock and sync signal ⁇ from the ⁇ ync ⁇ eparator 22b and the clock circuit 22c for controlling the timing of the pixel processor 26.
• the proces ⁇ controller 26a read ⁇ luminance value ⁇ from the field ⁇ tore 24b one at a time in ⁇ equential order, corresponding to rows of the video signal from the video source 18.
• the field store 24b collects one full field of the luminance ⁇ ignal and ⁇ tore ⁇ it for further proce ⁇ ing. That i ⁇ , consider that the transmitter 10 operates one field behind the incoming video signal ⁇ at the video input 23.
• the proce ⁇ controller 26a ⁇ elect ⁇ , for example, the pixel ⁇ corre ⁇ ponding to the ODD rows and the ODD columns, i.e. Un,m for all values of n and . These pixels are referred to as the "un-depleted pixels" and are allowed to proceed to the latch and buffer 26d for transmission to the receiver 12. Also, the proces ⁇ controller 26a allow ⁇ pa ⁇ age of other one ⁇ of the pixel ⁇ the latch and buffer 26c.
• the pixel ⁇ which pass to the latch and buffer 26c are used to be displayed on a monitor 15 by the ALU unit 28a, the latch and buffer 28b and a digital to analogue converter 31.
• the digital to analogue converter 31 is al ⁇ o connected to an output of the latch and buffer 26d and therefore, the monitor 15 can ⁇ how a video ⁇ ignal similar to that which will be shown on the monitor 20 at the receiver 12.
• a pseudo noi ⁇ e generator 28c i ⁇ connected to the ALU unit 28a via a latch 28d.
• the p ⁇ eudo noi ⁇ e generator 28c allow ⁇ injection of noi ⁇ e pixel ⁇ into the video image displayed on the monitor 15.
• the process controller 26a ha ⁇ the effect of, for example, selecting ODD pixels from ODD video fields and EVEN pixels from EVEN video fields.
• the combined effect i ⁇ a field having two fields which are interlaced both horizontally and vertically a ⁇ ⁇ hown in Figure 8. That i ⁇ , every ⁇ econd column and every ⁇ econd row from the original video ⁇ ignal ha ⁇ been deleted.
• the re ⁇ ultant video ⁇ ignal for tran ⁇ mission i ⁇ referred to a ⁇ "depleted" .
• each field i ⁇ depleted from 625 down to 312 pixels across and from 625 down to 321 pixels down in each column.
• each depleted field has one quarter of the information of the original field. This correspond ⁇ to a modulo-2 depletion of the pixel ⁇ of the original video ⁇ ignal ⁇ .
• the luminance of the depleted pixels is recombined with the sync and colour information at the digital to analogue converter 30 via the colour proce ⁇ or 27 and the sync separator 22b respectively.
• a ⁇ with the receiver 12 other forms of depletion of the video signal could be u ⁇ ed, ⁇ uch as, for example, modulo 3, 4, 5 etc. or even a relatively random form of depletion as shown in Figure lb in which over sub ⁇ equent fields each pixel describes the path ⁇ hown by line ⁇ 1 to 9.
• the displayed picture looks similar to Figure 2a where part of a 64 column pattern is depicted;
• the image proce ⁇ ing ⁇ y ⁇ tem of the present invention allows for considerable compres ⁇ ion of a video signal by relying on the psychophy ⁇ ical attribute ⁇ of the human perception ⁇ ystem to undertake appropriate interpolation of the video image to provide a perceived resolution which is substantially the same a ⁇ that of the unco pre ⁇ sed signal - even though the actual resolution has been ⁇ everely depleted.
• the DOT ⁇ y ⁇ tem relie ⁇ on the BETA APPARENT MOTION effect to achieve the high compre ⁇ ion by deletion of all information from the video ⁇ ignal which is not necessary for the human perception sy ⁇ tem.
• the viewability of the interlaced field ⁇ i ⁇ enhanced due to the very high ⁇ tatistical correlation - between the pixels of sub ⁇ equent fields (by stepping the pixels backward ⁇ and forward ⁇ ).
• the VET then add ⁇ random noi ⁇ e to the ⁇ ignal, once received, in order to make the re ⁇ ultant video image sharper - by relying on the phenomenon of SUPER EDGING.
• the system of the present invention preferably operates in a digital format and so avoids analogue artefacts (i.e. overshoot and smear) which are very difficult to remove. Statistical manipulation of the video signal can allow for even greater compres ⁇ ion.
• the video ⁇ ignal, a ⁇ compre ⁇ ed by the DOT ra ⁇ ter could be proce ⁇ ed by a DCT to give a further compression of 40:1, thus giving a total compression of 1600:1.
• a video signal can be compres ⁇ ed and tran ⁇ mitted via a telephone line having a bandwidth of 64kHz - thu ⁇ being applicable to video telephone without requiring ⁇ pecial or multiple telephone line ⁇ .
• the DOT can be used to enhance the resolution of a ⁇ tandard video signal to achieve a high definition video result. And, such high definition can be achieved ⁇ imply by proce ⁇ es at the receiver.
• the DOT could be used to digitise video signals for video recorders and video camera ⁇ .

Applications Claiming Priority (3)

Publications (2)

Family

ID=3776314

Family Applications (1)

Country Status (5)

Families Citing this family (1)

Citations (1)

Family Cites Families (8)

• 1993
  • 1993-07-21 CA CA002140893A patent/CA2140893A1/en not_active Abandoned
  • 1993-07-21 WO PCT/AU1993/000368 patent/WO1994003013A1/en not_active Application Discontinuation
  • 1993-07-21 KR KR1019950700287A patent/KR950703256A/ko not_active Application Discontinuation
  • 1993-07-21 EP EP93915546A patent/EP0651932A4/en not_active Withdrawn
  • 1993-07-21 JP JP6504031A patent/JPH07509111A/ja active Pending

Patent Citations (1)

Non-Patent Citations (3)

Also Published As

Similar Documents

Legal Events