EP0644524B1 - Verbesserungen in Synchronisationsschaltungen - Google Patents

Verbesserungen in Synchronisationsschaltungen Download PDF

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Publication number
EP0644524B1
EP0644524B1 EP19940306065 EP94306065A EP0644524B1 EP 0644524 B1 EP0644524 B1 EP 0644524B1 EP 19940306065 EP19940306065 EP 19940306065 EP 94306065 A EP94306065 A EP 94306065A EP 0644524 B1 EP0644524 B1 EP 0644524B1
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EP
European Patent Office
Prior art keywords
clock signal
reference clock
circuit
data
altered
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP19940306065
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English (en)
French (fr)
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EP0644524A1 (de
Inventor
Hugh Mair
John Yin
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Texas Instruments Inc
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Texas Instruments Inc
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/18—Timing circuits for raster scan displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/02—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed
    • G09G5/06—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed using colour palettes, e.g. look-up tables

Definitions

  • This invention relates to electronic circuits and more particularly relates to synchronization circuits in video palette applications.
  • FIG.1 is a prior art block diagram illustrating the problem.
  • a video circuit 10 has a controller chip 12 connected to a video color palette chip 14.
  • Controller chip 12 sends data to color palette 14 at a first frequency and color palette 14 manipulates the data at a second frequency which is greater than the first frequency.
  • Typical examples would be a first frequency of 50 Mhz and a second frequency of 200 Mhz.
  • FIG.2 is a prior art solution to obtain synchronization between data of controller chip 12 and a reference clock signal CLKref of color palette 14.
  • This solution is limited by the fact that one must assume what delay will be needed to appropriately synchronize data to CLKref.
  • the delay through controller chip 12 is a strong function of temperature, supply voltage, and process variation, therefore the delay may constantly vary.
  • a second disadvantage is that multiple flip flops 16a-16d are needed for each data bit.
  • a method of synchronizing a data signal of a controller chip 12 to a reference clock signal of a color palette chip 12 in a video driving system 10 includes the steps of altering the reference clock signal frequency, adjusting the phase of an output clock signal from the palette chip 12 wherein the output clock signal coupled with delay from controller chip 12 produces a feedback clock signal that is synchronized with the altered reference clock signal, and latching the data signal with the feedback clock signal thereby synchronizing the data signal to the reference clock signal.
  • FIG.1 is a prior art block diagram illustrating a video circuit 10.
  • FIG.2 is a prior art schematic diagram illustrating a synchronization methodology.
  • FIG.3 is a schematic diagram illustrating the preferred embodiment of the invention, a synchronization circuit 30 within video palette 14 for a video circuit 10 that is independent of process, temperature, or supply voltage variations.
  • FIG.3 is a schematic diagram illustrating the preferred embodiment of the invention, a synchronization circuit 30 within color palette 14 that provides synchronization between a reference clock (CLKref) and a feedback clock (CLKin) that is independent of process, temperature, or supply voltage variation and occupies less area and dissipates less power than prior art synchronization solutions.
  • Synchronized feedback clock CLKin is then used to latch data (DATAin) from controller chip 12 thereby synchronizing data to CLKref.
  • Synchronization circuit 30 includes a divide circuit 32 that receives a reference clock signal CLKref. Divide circuit 32 is connected to a phase locked loop circuit (PLL) 34.
  • PLL phase locked loop circuit
  • PLL 34 receives feedback clock signal CLKin from controller chip 12 (not shown) and a signal from divide circuit 32 and outputs a clock signal CLKout.
  • Feedback clock signal CLKin is also connected to a D-type flip flop 36.
  • Flip flop 36 takes an external data signal (DATAin) from controller chip 12 as its data input and feedback clock signal CLKin as its clock input and outputs a data signal (DATAout).
  • FIG.3 operates in the following manner.
  • Synchronization circuit 30 takes reference clock signal CLKref that is operating at 200 Mhz, in this particular embodiment, and divides it down to 50 Mhz through divide circuit 32. It should be understood that other operating frequencies may also be used and that the operating frequency of CLKref is not limited to the frequency of this example.
  • Divide circuit 32 may be a standard counter as is well known by those skilled in the art and may divide down, in alternative embodiments, reference clock CLKref by any value such as, for example, divide by eight or divide by sixteen.
  • Divide circuit 32 outputs a 50 Mhz signal (which may be called altered CLKref) to PLL 34.
  • PLL 34 takes the output of divide circuit 32 and feedback clock signal CLKin, which is also operating at 50 Mhz and synchronizes CLKin to the output of divide circuit 32. PLL 34 obtains synchronization between altered CLKref and CLKin by adjusting the frequency of output clock signal CLKout thereby adjusting the phase of CLKin. Synchronization via adjustment of frequency in phase locked loops is well known by those skilled in the art of circuit design. CLKout then feeds back to controller chip 12 (as shown in FIG.1) where further delay due to various standard operations of controller chip 12 is added. The output clock of controller chip 12 is feedback clock signal CLKin which is then (due to added or removed delay from CLKout via PLL 34) synchronized with altered CLKref.
  • the input of PLL 34 which is CLKin
  • CLKin also serves as a clock input for flip flop 36 which latches data on the rising edge of CLKin. Therefore, data is synchronized with reference clock signal CLKref. More accurately, data is synchronized with the output signal of divide circuit 32 which is altered CLKref. However, if the altered clock reference signal (altered CLKref) is delayed less than a half cycle of CLKref then synchronization between data and CLKref is considered close enough to be considered “effectively" synchronized.
  • Synchronization circuit 30, within color palette 14, advantageously provides synchronization of data to CLKref that is independent of temperature and supply voltage variations as well as differences in process conditions. Still further, synchronization circuit 30 replaces a plurality of flip flops (as shown in FIG.2) with a single phase locked loop circuit 34 thus significantly reducing the area and power dissipation of color palette 14.

Claims (10)

  1. Verfahren zum Synchronisieren eines Datensignals eines Controller-Chips mit einem Referenztaktsignal eines Farbpaletten-Chips in einem Videotreibersystem, mit den folgenden Schritten:
    Verändern der Referenztaktsignalfrequenz in der Weise, daß die veränderte Frequenz des Referenztaktsignals gleich der Frequenz eines Rückkopplungstaktsignals des Controller-Chips ist;
    Einstellen der Phase eines Ausgangstaktsignals, wobei das Rückkopplungstaktsignal und das geänderte Referenztaktsignal synchronisiert sind; und
    Verriegeln des Taktsignals mit dem Rückkopplungstaktsignal, wodurch die Daten mit dem Referenztaktsignal synchronisiert werden.
  2. Verfahren nach Anspruch 1, ferner mit dem Erzeugen des Rückkopplungstaktsignals durch Koppeln des Ausgangstaktsignals mit einer Verzögerung vom Controller-Chip.
  3. Verfahren nach Anspruch 1 oder Anspruch 2, bei dem das Einstellen der Phase des Ausgangstaktsignals die folgenden Schritte enthält:
    Vergleichen der Phase des Rückkopplungstaktsignals mit der Phase des geänderten Referenztaktsignals; und
    Einstellen der Frequenz des Ausgangstaktsignals, bis die Phasen des Rückkopplungstaktsignals und des geänderten Referenztaktsignals synchronisiert sind.
  4. Schaltung zum Synchronisieren eines Datensignals eines Controller-Chips mit einem Referenztaktsignal eines Farbpaletten-Chips in einem Videotreibersystem, mit:
    einer Einrichtung zum Verändern der Referenztaktsignalfrequenz in der Weise, daß die veränderte Frequenz des Referenztaktsignals gleich der Frequenz eines Rückkopplungstaktsignals des Controller-Chips ist; einer Phaseneinstelleinrichtung zum Einstellen der Phase eines Ausgangstaktsignals; und
    einer Verriegelungseinrichtung zum Verriegeln des Datensignals mit dem Rückkopplungstaktsignal in der Weise, daß die Daten dadurch mit dem Referenztakt synchronisiert werden, wobei der Rückkopplungstakt und das veränderte Referenztaktsignal synchronisiert sind.
  5. Schaltung nach Anspruch 4, ferner mit:
    einer Teilungsschaltung, für die das Referenztaktsignal einen Eingang bildet und das veränderte Referenztaktsignal einen Ausgang bildet, wobei die Frequenz des veränderten Referenztaktsignals ein Bruchteil der Frequenz des Referenztaktsignals ist;
    wobei die Phaseneinstelleinrichtung eine an die Teilungsschaltung angeschlossene Phaseneinstellschaltung enthält, für die das geänderte Referenztaktsignal einen ersten Eingang bildet und das Rückkopplungstaktsignal einen zweiten Eingang bildet, wobei die Frequenz des geänderten Referenztaktsignals und des Rückkopplungstaktsignals gleich sind, wobei das Rückkopplungstaktsignal durch Verzögerung aus dem Ausgangstaktsignal hervorgeht, wobei die Verzögerung zwischen dem Ausgangstaktsignal und dem Rückkopplungstaktsignal in Abhängigkeit von der Temperatur, der Speisespannung und der Prozeßschwankung variiert, wobei die Phaseneinstellschaltung als Antwort auf die Phasenbeziehung zwischen dem geänderten Taktsignal und dem Rückkopplungstaktsignal zum Ausgangstaktsignal eine Verzögerung hinzufügt oder von diesem eine Verzögerung abzieht, so daß durch die Addition bzw. die Subtraktion der Verzögerung zu dem bzw. von dem Ausgangstaktsignal das Rückkopplungssignal mit dem geänderten Referenztaktsignal synchronisiert ist;
    und die Verriegelungseinrichtung ein Datenspeicherelement enthält, das einen an das Rückkopplungstaktsignal angeschlossenen Freigabeeingang, den an das Datensignal angeschlossenen Dateneingang und den Ausgang besitzt, wobei das Rückkopplungstaktsignal das Datensignal mit dem Ausgang des Datenspeicherelements verriegelt, wodurch das Datensignal mit dem Referenztaktsignal synchronisiert wird.
  6. Schaltung nach Anspruch 5, bei der die Teilungsschaltung einen Zähler enthält.
  7. Schaltung nach Anspruch 6, bei der der Zähler einen programmierbaren Zähler enthält.
  8. Schaltung nach irgendeinem der Ansprüche 5 bis 7, bei der die Phaseneinstellschaltung eine Phasenregelschleife enthält.
  9. Schaltung nach irgendeinem der Ansprüche 5 bis 8, bei der das Datenspeicherelement einen Zwischenspeicher enthält.
  10. Schaltung nach irgendeinem der Ansprüche 5 bis 9, bei der das Datenspeicherelement ein Flipflop enthält.
EP19940306065 1993-08-17 1994-08-17 Verbesserungen in Synchronisationsschaltungen Expired - Lifetime EP0644524B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10802193A 1993-08-17 1993-08-17
US108021 1993-08-17

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EP0644524A1 EP0644524A1 (de) 1995-03-22
EP0644524B1 true EP0644524B1 (de) 1998-01-21

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US10771068B2 (en) 2018-02-20 2020-09-08 International Business Machines Corporation Reducing chip latency at a clock boundary by reference clock phase adjustment

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DE68924737T2 (de) * 1988-08-09 1996-05-02 Seiko Epson Corp Anzeigesignalgenerator.
US5291187A (en) * 1991-05-06 1994-03-01 Compaq Computer Corporation High-speed video display system

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EP0644524A1 (de) 1995-03-22
DE69408063T2 (de) 1998-06-10

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