EP0642072B1 - Current mirror - Google Patents

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Publication number
EP0642072B1
EP0642072B1 EP94113819A EP94113819A EP0642072B1 EP 0642072 B1 EP0642072 B1 EP 0642072B1 EP 94113819 A EP94113819 A EP 94113819A EP 94113819 A EP94113819 A EP 94113819A EP 0642072 B1 EP0642072 B1 EP 0642072B1
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EP
European Patent Office
Prior art keywords
transistors
transistor
eighteenth
series
well
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP94113819A
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German (de)
French (fr)
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EP0642072A1 (en
Inventor
Oliver Dr. Ing. Kiehl
Rudolf Dr. Koch
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Siemens AG
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Siemens AG
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Publication of EP0642072B1 publication Critical patent/EP0642072B1/en
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors

Definitions

  • a further development of the invention provides that only field effect transistors are used, the ratio of channel width to channel length in the second, fourth, fifth and tenth transistor being approximately equal to one third of the ratio of channel width to channel length in the seventeenth and eighteenth, fifteenth and sixteenth transistors. This measure ensures that the seventeenth and eighteenth transistors or fourteenth, fifteenth and sixteenth transistors are operated at the saturation limit, which increases the accuracy and minimizes the voltage drop across these transistors.
  • the drain connection of the transistor 3 is connected to the gate connections of a plurality of MOS field-effect transistors of the n-channel type, namely the transistors 9 to 13, and to the drain connection of the transistor 9.
  • the source connections of the transistors 9 to 13 are each connected to the drain connections of further MOS field-effect transistors of the n-channel type, namely the transistors 10, 14, 15, 16, the source connections of which are in turn connected to a negative supply potential n.
  • the gate connections of the transistors 14, 15, 16, like the drain connection of the transistor 11, are coupled to the drain connection of the transistor 6.
  • the gates of transistors 17 and 18 are connected to the drains of transistors 7 and 12.

Abstract

A current mirror includes first through eighteenth transistors. The load paths of the first and second transistors are in series for carrying an input current to a first supply potential. The control terminals of the first through eighth transistors receive the input current. The load paths of the fourth, third, ninth and tenth transistors are in series between the first and a second supply potential. The third and ninth transistors form a tap being connected to the control terminals of the ninth, tenth, eleventh, twelfth and thirteenth transistors. The load paths of the fifth, sixth, eleventh and fourteenth transistors are in series between the first and second supply potentials. The sixth and eleventh transistors form a tap being connected to the control terminals of the fourteenth through sixteenth transistors. The load paths of the seventeenth, seventh, twelfth and fifteenth transistors are in series between the first and second supply potentials. The seventh and twelfth transistors form a tap being connected to the control terminals of the seventeenth and eighteenth transistors. The load paths of the eighteenth and eighth transistors are in series for tapping a first output current proportional to the input current from the first supply potential. The load paths of the sixteenth and thirteenth transistors are in series for tapping a second output current equal to the first from the second supply potential. The ninth through sixteenth transistors are of one, and the seventeenth, eighteenth and first through eighth transistors being of the other, conduction type.

Description

Die Erfindung betrifft einen Stromspiegel.The invention relates to a current mirror.

Wenn keiner der beiden Anschlüsse eines mit einem eingeprägten Strom zu betreibenden Verbrauchers mit einem festen Potential verbunden werden darf, finden sogenannte "schwimmende Stromquellen" Anwendung. Diese sind beispielsweise aus U.Tietze, Ch.Schenk "Halbleiter-Schaltungstechnik", 8. Auflage 1986, S. 363-364 bzw. der EP-A-0 373 471 bekannt und bestehen aus zwei geerdeten Stromquellen, die entgegengesetzt gleich große Ströme liefern und den Verbraucher über die jeweils andere Stromquelle speisen. Wesentlich ist dabei, daß beide Stromquellen möglichst exakt betragsmäßig gleichgroße Ströme abgeben. Diese Forderung ist allerdings umso schwieriger zu erfüllen, wenn die Stromquellen abhängig von einer gemeinsamen Eingangsgröße steuerbar sein sollen. Dies ist beispielsweise bei einem Stromspiegel der Fall, der einen zu einem Potential behafteten Eingangsstrom proportionalen, potentialfreien Ausgangsstrom erzeugen soll.If neither of the two connections of a consumer to be operated with an impressed current may be connected to a fixed potential, so-called "floating current sources" are used. These are known, for example, from U.Tietze, Ch.Schenk "Semiconductor Circuit Technology", 8th edition 1986, pp. 363-364 and EP-A-0 373 471 and consist of two grounded current sources which have currents of equal magnitude deliver and feed the consumer via the other power source. It is essential that both current sources deliver currents of the same magnitude as precisely as possible. However, this requirement is all the more difficult to meet if the power sources are to be controllable depending on a common input variable. This is the case, for example, in the case of a current mirror which is intended to generate a potential-free output current which is proportional to an input current which has a potential.

Aufgabe der Erfindung ist es, einen derartigen Stromspiegel bereitzustellen.The object of the invention is to provide such a current mirror.

Die Aufgabe wird durch einen Stromspiegel gelöst, bei dem ein Eingangsstrom über die in Reihe geschalteten Laststrecken eines ersten und zweiten Transistors auf ein erstes Versorgungspotential sowie auf die Steueranschlüsse des ersten und zweiten Transistors sowie eines dritten, vierten, fünften, sechsten, siebten und achten Transistors geführt wird, bei dem zwischen das erste Versorgungspotential und ein zweites Versorgungspotential hintereinander die Laststrecken des dritten und vierten Transistors sowie eines neunten und zehnten Transistors geschaltet sind, wobei am Abgriff zwischen drittem und neuntem Transistor die Steueranschlüsse von neuntem und zehntem Transistor sowie einem elften, zwölften und dreizehnten Transistor angeschlossen sind, bei dem zwischen das erste und zweite Versorgungspotential hintereinander die Laststrecken des fünften, sechsten und elften Transistors sowie eines vierzehnten Transistors geschaltet sind, wobei am Abgriff zwischen sechstem und elftem Transistor die Steueranschlüsse des vierzehnten Transistors sowie eines fünfzehnten und sechzehnten Transistors angeschlossen sind, bei dem zwischen das erste und zweite Versorgungspotential hintereinander die Laststrecken eines zehnten Transistors sowie des siebten, zwölften und fünfzehnten Transistors geschaltet sind, wobei am Abgriff zwischen siebtem und zwölftem Transistor die Steueranschlüsse des siebzehnten Transistors sowie eines achtzehnten Transistors angeschlossen sind, bei dem vom ersten Versorgungspotential über die in Reihe geschalteten Laststrecken von achtzehntem und achtem Transistor ein zu dem Eingangsstrom proportionaler erster Ausgangsstrom abnehmbar ist, bei dem vom zweiten Versorgungspotential über die in Reihe geschalteten Laststrecken von sechszehntem und dreizehntem Transistor ein zu dem ersten Ausgangsstrom gleich großer zweiter Ausgangsstrom abnehmbar ist und bei dem neunter bis sechzehnter Transistor vom einen Leitungstyp und siebzehnter, achtzehnter sowie erster bis achter Transistor vom anderen Leitungstyp sind.The object is achieved by a current mirror, in which an input current over the load paths of a first and second transistor connected in series to a first supply potential and to the control connections of the first and second transistor and a third, fourth, fifth, sixth, seventh and eighth transistor, in which the load paths of the third and fourth transistor and a ninth and tenth transistor are connected in series between the first supply potential and a second supply potential, the control connections of the ninth being tapped between the third and ninth transistor and tenth transistor and an eleventh, twelfth and thirteenth transistor are connected, in which the load paths of the fifth, sixth and eleventh transistor and a fourteenth transistor are connected in series between the first and second supply potential, the control terminals of the fourteenth transistor and a fifteenth and sixteenth transistor are connected, in which the load paths of a tenth transistor and of the seventh, twelfth and fifteen are connected in succession between the first and second supply potentials ten transistors are connected, the control connections of the seventeenth transistor and an eighteenth transistor being connected to the tap between the seventh and twelfth transistors, in which a first output current proportional to the input current can be removed from the first supply potential via the series load paths of the eighteenth and eighth transistors , in which a second output current which is equal to the first output current can be removed from the second supply potential via the load paths connected in series of the sixteenth and thirteenth transistor, and in the case of the ninth to sixteenth transistor of one line type and seventeenth, eighteenth and first to eighth transistor of the other line type are.

Der erfindungsgemäße Stromspiegel mit potentialfreiem Ausgangsstrom zeichnet sich durch eine hohe relative Genauigkeit der einzelnen potentialbehafteten Ausgangsströme sowie durch einen sehr geringen Spannungsabfall im Eingang- und Ausgangszweig aus.The current mirror according to the invention with floating output current is characterized by a high relative accuracy of the individual floating output currents and by a very low voltage drop in the input and output branches.

Eine Weiterbildung der Erfindung sieht vor, daß ausschließlich Feldeffekttransistoren verwendet werden, wobei das Verhältnis von Kanalweite zu Kanallänge beim zweiten, vierten, fünften und zehnten Transistor etwa gleich einem Drittel des Verhältnisses von Kanalweite zu Kanallänge bei siebzehntem und achtzehntem, fünfzehntem und sechzehntem Transistor ist. Durch diese Maßnahme wird erreicht, daß siebzehnter und achtzehnter Transistor bzw. vierzehnter, fünfzehnter und sechzehnter Transistor an der Sättigungsgrenze betrieben werden, wodurch die Genauigkeit erhöht und der Spannungsabfall an diesen Transistoren minimiert wird.A further development of the invention provides that only field effect transistors are used, the ratio of channel width to channel length in the second, fourth, fifth and tenth transistor being approximately equal to one third of the ratio of channel width to channel length in the seventeenth and eighteenth, fifteenth and sixteenth transistors. This measure ensures that the seventeenth and eighteenth transistors or fourteenth, fifteenth and sixteenth transistors are operated at the saturation limit, which increases the accuracy and minimizes the voltage drop across these transistors.

Außerdem bevorzugt zweiter, vierter, fünfter, siebzehnter und achtzehnter Transistor untereinander, erster, dritter, sechster, siebter und achter Transistor untereinander, neunter elfter, zwölfter und dreizehnter Transistor untereinander sowie zehnter, vierzehnter, fünfzehnter und sechzehnter Transistor untereinander jeweils gleiche Kanallängen. Desweiteren weisen zweiter, vierter und fünfter Transistor tereinander, veirzehnter, fünfzehnter und sechzehnter Transistor untereinander, erster, dritter, sechster, siebter und achter Transistor untereinander, siebzehnter und achtzehnter Transistor untereinander sowie neunter, elfter, zwölfter und dreizehnter Transistor untereinander jeweils gleiche Kanalweiten auf. Dadurch ist insbesondere bei integrierter Schaltungstechnik unabhängig von produktionsbedingter Streuungen ein hoher Gleichlauf garantiert.In addition, second, fourth, fifth, seventeenth and eighteenth transistors are preferred, first, third, sixth, seventh and eighth transistors among one another, ninth eleventh, twelfth and thirteenth transistors among one another as well as tenth, fourteenth, fifteenth and sixteenth transistors among each other the same channel lengths. Furthermore, the second, fourth and fifth transistors with one another, fourteenth, fifteenth and sixteenth transistors with one another, first, third, sixth, seventh and eighth transistors with one another, seventeenth and eighteenth transistors with one another and ninth, eleventh, twelfth and thirteenth transistors with one another each have the same channel widths. This is particularly important for integrated circuit technology high synchronization guaranteed regardless of production-related variations.

Die Erfindung wird nachfolgend anhand des in der einzigen Figur der Zeichnung dargestellten Ausführungsbeispiels näher erläutert.The invention is explained in more detail below with reference to the embodiment shown in the single figure of the drawing.

Beim Ausführungsbeispiel wird ein Eingangsstrom e an die Gateanschlüsse mehrerer MOS-Feldeffekttransistoren vom p-Kanal-Typ, nämlich der Transistoren 1 bis 8, angelegt. Außerdem wird der Eingangsstrom e auch dem Drainanschluß des Transistors 1 zugeführt. Der Sourceanschluß des Transistors 1 ist ebenso wie die Sourceanschlüsse der Transistoren 3, 6, 7, 8 mit jeweils dem Drainanschluß der Transistoren 2 bzw. 4 bzw. 5 bzw. 17 bzw. 18 verbunden, deren Sourceanschlüsse wiederum an ein positives Versorgungspotential p angeschlossen sind.In the exemplary embodiment, an input current e is applied to the gate connections of a plurality of MOS field-effect transistors of the p-channel type, namely transistors 1 to 8. In addition, the input current e is also supplied to the drain of the transistor 1. The source connection of transistor 1, like the source connections of transistors 3, 6, 7, 8, is connected to the drain connection of transistors 2 or 4 or 5 or 17 or 18, the source connections of which are in turn connected to a positive supply potential p .

Der Drainanschluß des Transistors 3 ist mit den Gateanschlüssen mehrerer MOS-Feldeffekttransistoren vom n-Kanal-Typ, nämlich den Transistoren 9 bis 13, sowie mit dem Drainanschluß des Transistors 9 verbunden. Die Sourceanschlüsse der Transistoren 9 bis 13 sind jeweils mit den Drainanschlüssen weiterer MOS-Feldeffekttransistoren vom n-Kanal-Typ, nämlich den Transistoren 10, 14, 15, 16, verschaltet, deren Sourceanschlüsse wiederum an ein negatives Versorgungspotential n angeschlossen sind. Die Gateanschlüsse der Transistoren 14, 15, 16 sind ebenso wie der Drainanschluß des Transistors 11 mit dem Drainanschluß des Transistors 6 gekoppelt. Die Gateanschlüsse der Transistoren 17 und 18 sind mit den Drainanschlüssen der Transistoren 7 und 12 verbunden. Schließlich ist an den Drainanschlüssen der Transistoren 8 und 13 Ausgangsströme a bzw. a' abnehmbar. Die Ströme a und a' sind dabei betragsmäßig gleich groß und proportional zum Eingangsstrom e. Eine sogenannte "schwimmende Last" wird folglich zwischen die Drainanschlüsse der Transistoren 8 und 13 geschaltet.The drain connection of the transistor 3 is connected to the gate connections of a plurality of MOS field-effect transistors of the n-channel type, namely the transistors 9 to 13, and to the drain connection of the transistor 9. The source connections of the transistors 9 to 13 are each connected to the drain connections of further MOS field-effect transistors of the n-channel type, namely the transistors 10, 14, 15, 16, the source connections of which are in turn connected to a negative supply potential n. The gate connections of the transistors 14, 15, 16, like the drain connection of the transistor 11, are coupled to the drain connection of the transistor 6. The gates of transistors 17 and 18 are connected to the drains of transistors 7 and 12. Finally, at the drains of the transistors 8 and 13 output currents a and a 'removable. The currents a and a 'are of the same magnitude and proportional to the input current e. A so-called "floating load" is consequently connected between the drain connections of transistors 8 and 13.

Claims (4)

  1. Current mirror, in which an input current (e) is passed via the series-connected load paths of a first and second transistor (1, 2) to a first supply potential (p) as well as to the control terminals of the first and second transistors (1, 2) as well as of a third, fourth, fifth, sixth, seventh and eighth transistor (3 to 8), in which the load paths of the third and fourth transistors (3, 4) as well as of a ninth and tenth transistor (9, 10) are connected in series between the first supply potential (p) and a second supply potential (n), the control terminals of the ninth and tenth transistors (9, 10) as well as of an eleventh, twelfth and thirteenth transistor (11, 12, 13) being connected to the tap between the third and ninth transistors (3, 9), in which the load paths of the fifth, sixth and eleventh transistors (5, 6, 11) as well as of a fourteenth transistor (14) are connected in series between the first and second supply potentials (p, n), the control terminals of the fourteenth transistor (14) as well as of a fifteenth and sixteenth transistor being connected to the tap between the sixth and eleventh transistors (6, 11), in which the load paths of a seventeenth transistor (17) as well as of the seventh, twelfth and fifteenth transistors (7, 12, 15) are connected in series between the first and second supply potentials (p, n), the control terminals of the seventeenth transistor (17) as well as of an eighteenth transistor (18) being connected to the tap between the seventh and twelfth transistors (7, 12), in which a first output current (a), which is proportional to the input current (e), can be picked off from the first supply potential (p) via the series-connected load paths of the eighteenth and eighth transistors (18, 8), in which a second output current (a') which has the same magnitude as the first output current (a) can be picked off from the second supply potential (n) via the series-connected load paths of the sixteenth and thirteenth transistors (16, 13), and in which the ninth to sixteenth transistors (9 to 16) are of one conduction type and the seventeenth, eighteenth and first to eighth transistors (17, 18, 1 to 8) are of the other conduction type.
  2. Current mirror according to Claim 1, characterized in that provision is made exclusively of field-effect transistors, the ratio of channel width to channel length in the second, fourth, fifth and tenth transistors (2, 4, 5, 10) being equal to a third of the ratio of channel width to channel length in the seventeenth and eighteenth and fourteenth, fifteenth, sixteenth transistors (17, 18, 14, 15, 16).
  3. Current mirror according to Claim 1 or 2, characterized in that the second, fourth and fifth transistors (2, 4, 5), the third and sixth transistors (3, 6), the seventh and eighth transistors (7, 8), the twelfth and thirteenth transistors (12, 13), the fifteenth and sixteenth transistors (15, 16) as well as the seventeenth and eighteenth transistors (17, 18) are in each case constructed identically.
  4. Current mirror according to Claim 1 or 2, characterized in that the second, fourth, fifth, seventeenth and eighteenth transistors (2, 4, 5, 17, 18) together, the first, third, sixth, seventh and eighth transistors (1, 3, 6, 7, 8) together, the ninth, eleventh, twelfth and thirteenth transistors (9, 11, 12, 13) together as well as the tenth, fourteenth, fifteenth and sixteenth transistors (10, 14, 15, 16) together in each case have the same channel lengths, and in that the second, fourth and fifth transistors (2, 4, 5) together, the fourteenth, fifteenth and sixteenth transistors (14, 15, 16) together, the first, third, sixth, seventh and eighth transistors (1, 3, 6, 7, 8) together, the seventeenth and eighteenth transistors (17, 18) together as well as the ninth, eleventh, twelfth and thirteenth transistors (9, 11, 12, 13) together in each case have the same channel widths.
EP94113819A 1993-09-03 1994-09-02 Current mirror Expired - Lifetime EP0642072B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE4329866 1993-09-03
DE4329866A DE4329866C1 (en) 1993-09-03 1993-09-03 Current mirror

Publications (2)

Publication Number Publication Date
EP0642072A1 EP0642072A1 (en) 1995-03-08
EP0642072B1 true EP0642072B1 (en) 1997-05-07

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EP94113819A Expired - Lifetime EP0642072B1 (en) 1993-09-03 1994-09-02 Current mirror

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US (1) US5598094A (en)
EP (1) EP0642072B1 (en)
AT (1) ATE152843T1 (en)
DE (2) DE4329866C1 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2347524B (en) * 1995-11-17 2001-01-24 Fujitsu Ltd High precision current output circuit
JP3593396B2 (en) * 1995-11-17 2004-11-24 富士通株式会社 Current output circuit
US5990714A (en) * 1996-12-26 1999-11-23 United Microelectronics Corporation Clock signal generating circuit using variable delay circuit
US6020768A (en) * 1998-05-13 2000-02-01 Oak Technology, Inc. CMOS low-voltage comparator
US6788134B2 (en) 2002-12-20 2004-09-07 Freescale Semiconductor, Inc. Low voltage current sources/current mirrors
US7102393B2 (en) * 2004-09-30 2006-09-05 Exar Corporation Detection of a closed loop voltage
US9405308B2 (en) * 2014-05-19 2016-08-02 Telefonaktiebolaget Lm Ericsson (Publ) Method and apparatus to minimize switching noise disturbance

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4544878A (en) * 1983-10-04 1985-10-01 At&T Bell Laboratories Switched current mirror
US4618815A (en) * 1985-02-11 1986-10-21 At&T Bell Laboratories Mixed threshold current mirror
ATE82808T1 (en) * 1985-09-30 1992-12-15 Siemens Ag SWITCHABLE BIPOLAR POWER SOURCE.
US4857863A (en) * 1988-08-25 1989-08-15 Motorola, Inc. Low power output driver circuit with slew rate limiting
IT1228034B (en) * 1988-12-16 1991-05-27 Sgs Thomson Microelectronics CURRENT GENERATOR CIRCUIT WITH ADDITIONAL CURRENT MIRRORS
NL9001018A (en) * 1990-04-27 1991-11-18 Philips Nv REFERENCE GENERATOR.
US5245273A (en) * 1991-10-30 1993-09-14 Motorola, Inc. Bandgap voltage reference circuit
DE4233850C1 (en) * 1992-10-08 1994-06-23 Itt Ind Gmbh Deutsche Circuit arrangement for current setting of a monolithically integrated pad driver

Also Published As

Publication number Publication date
ATE152843T1 (en) 1997-05-15
DE4329866C1 (en) 1994-09-15
EP0642072A1 (en) 1995-03-08
DE59402650D1 (en) 1997-06-12
US5598094A (en) 1997-01-28

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