EP0642070A1 - Current mirror - Google Patents

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Publication number
EP0642070A1
EP0642070A1 EP94113817A EP94113817A EP0642070A1 EP 0642070 A1 EP0642070 A1 EP 0642070A1 EP 94113817 A EP94113817 A EP 94113817A EP 94113817 A EP94113817 A EP 94113817A EP 0642070 A1 EP0642070 A1 EP 0642070A1
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EP
European Patent Office
Prior art keywords
transistor
current
resistor
terminal
current mirror
Prior art date
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Granted
Application number
EP94113817A
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German (de)
French (fr)
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EP0642070B1 (en
Inventor
Oliver Dr. Ing. Kiehl
Michael Dipl.-Ing. Alger-Meunier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
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Siemens AG
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Publication of EP0642070A1 publication Critical patent/EP0642070A1/en
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Publication of EP0642070B1 publication Critical patent/EP0642070B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only

Definitions

  • the invention relates to a current mirror which is driven by an input current and which outputs an output current proportional to it.
  • the object of the invention is to provide a current mirror with high accuracy, low voltage drop and low circuit complexity.
  • the input current is routed to the control connections of a first and second transistor coupled to one another and, with the interposition of a resistor, to a connection of the load path of the first transistor in that the other connection of the first transistor and a connection of the load path of the second transistor is connected via the load path of a third or fourth transistor to a common reference point, that the coupled control connections of the third and fourth transistor are connected to one connection of the first transistor and that the output current at the other connection of the second transistor is removable .
  • a further development of the invention provides that the first and second transistor as well as third and fourth transistor are each constructed identically.
  • a resistor fed with the output current is selected to be identical to a second resistor, on which the input current in turn is dependent. Finally, the one resistor is selected such that its scatter is equal to the scatter of the second and third resistor.
  • an input current i e is passed on the one hand to the mutually coupled gate connections of a MOS transistor 1 and a MOS transistor 2 and on the other hand with the interposition of a resistor 5 to the drain connection of the transistor 1.
  • the source terminal of transistor 1 and the source terminal of transistor 2 are each connected to the drain terminal of a MOS transistor 3 and the drain terminal of a MOS transistor 4, respectively.
  • the source connections of transistors 3 and 4 are supplied with a supply potential 6.
  • the supply potential 6 is positive in the exemplary embodiment shown, so that the transistors 1 to 4 are consequently p-channel types acts.
  • the transistors 1 and 2 and the transistors 3 and 4 are preferably each constructed identically, that is to say that they have essentially the same width to length ratios of the channels and therefore have largely identical properties.
  • a current source circuit which has a MOS transistor 8 of the n-channel type controlled by an operational amplifier 7 and a resistor 10 connected to a negative supply potential 9 and a reference voltage source 11 connected to the supply potential 9 .
  • the other connection of the resistor 10 is coupled to the inverting input of the operational amplifier 7 and to the source connection of the transistor 8.
  • the other connection of the reference voltage source 11 is connected to the non-inverting input of the operational amplifier 7.
  • the input current i e is impressed at the drain connection of the transistor 8. It is therefore connected to the gate connections of transistors 1 and 2 and to a connection of the resistor. Furthermore, the output current i a is conducted via a resistor 12 to the negative supply potential 9.
  • the resistors 10 and 12 are constructed identically, the voltage across the two resistors is the same, namely the voltage of the reference voltage source 11.
  • the identical structure of the two resistors 10 and 12 completely eliminates any scatter, for example caused by temperature fluctuations or production-related variations.
  • identical design of both resistors can be carried out very easily and with high precision, particularly in the case of integrated circuit technology.
  • the resistor 5 is also in the same Technology as the two resistors 10 and 12 performed, for example, its resistance value does not have to be equal to that of the resistors 10 and 12, so its scatter can be largely compensated.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)
  • Amplifiers (AREA)
  • Gyroscopes (AREA)

Abstract

A current mirror which is activated by an input current (ie) and outputs an output current (ia) proportional thereto, in which the input current (ie), on the one hand, is conducted to the interconnected gates of a first and second transistor (1, 2) and, on the other hand, with interposition of a resistor (5), to a terminal of the load path of the first transistor (1), in which the other terminal of the first transistor (1) and a terminal of the load path of the second transistor (2) are in each case connected via the load path of a third and, respectively, fourth transistor (3, 4) to a common reference point, in which the interconnected gates of the third and fourth transistor (3, 4) are connected to one terminal of the first transistor (1) and in which the output current can be picked up at the other terminal of the second transistor (2). <IMAGE>

Description

Die Erfindung betrifft einen Stromspiegel, der durch einen Eingangsstrom angesteuert wird und der einen dazu proportionalen Ausgangsstrom abgibt.The invention relates to a current mirror which is driven by an input current and which outputs an output current proportional to it.

Aus U. Tietze, Ch. Schenk, "Halbleiter-Schaltungstechnik", 8. Auflage 1986, Seiten 62 bis 64 und 94 bis 97 sind verschiedene Ausgestaltungen von Stromspiegeln bekannt. Dabei lassen sich drei Forderungen an Stromspiegel nur schwer vereinen. Neben hoher Genauigkeit bei geringem schaltungstechnischem Aufwand sollte der Spannungsabfall im Eingangszweig und Ausgangszweig des Stromspiegels möglichst gering sein. Präzise Stromspiegel mit geringem Spannungsabfall sind jedoch nur mit erheblichem Schaltungsaufwand zu realisieren. Dagegen sind weniger aufwendige Stromspiegel entweder relativ ungenau oder verursachen einen hohen Spannungsabfall.Various configurations of current mirrors are known from U. Tietze, Ch. Schenk, "Semiconductor Circuit Technology", 8th edition 1986, pages 62 to 64 and 94 to 97. It is difficult to combine three requirements for current mirrors. In addition to high accuracy with low circuit complexity, the voltage drop in the input branch and output branch of the current mirror should be as small as possible. Precise current mirrors with a low voltage drop, however, can only be achieved with a considerable amount of circuitry. In contrast, less expensive current mirrors are either relatively inaccurate or cause a high voltage drop.

Aufgabe der Erfindung ist es, einen Stromspiegel mit hoher Genauigkeit, geringem Spannungsabfall und geringem schaltungstechnischen Aufwand anzugeben.The object of the invention is to provide a current mirror with high accuracy, low voltage drop and low circuit complexity.

Die Aufgabe wird dadurch gelöst, daß bei einem Stromspiegel der eingangs genannten Art der Eingangsstrom zum einen auf die miteinander gekoppelten Steueranschlüsse eines ersten und zweiten Transistors und zum anderen unter Zwischenschaltung eines Widerstandes auf einen Anschluß der Laststrecke des ersten Transistors geführt ist, daß der andere Anschluß des ersten Transistors und ein Anschluß der Laststrecke des zweiten Transistors jeweils über die Laststrecke eines dritten bzw. vierten Transistors an einen gemeinsamen Bezugspunkt angeschlossen ist, daß die miteinander gekoppelten Steueranschlüsse von drittem und viertem Transistor mit dem einen Anschluß des ersten Transistors verbunden sind und daß der Ausgangsstrom am anderen Anschluß des zweiten Transistors abnehmbar ist.The object is achieved in that, in the case of a current mirror of the type mentioned at the outset, the input current is routed to the control connections of a first and second transistor coupled to one another and, with the interposition of a resistor, to a connection of the load path of the first transistor in that the other connection of the first transistor and a connection of the load path of the second transistor is connected via the load path of a third or fourth transistor to a common reference point, that the coupled control connections of the third and fourth transistor are connected to one connection of the first transistor and that the output current at the other connection of the second transistor is removable .

Eine Weiterbildung der Erfindung sieht vor, daß erster und zweiter Transistor sowie dritter und vierter Transistor jeweils identisch aufgebaut sind.A further development of the invention provides that the first and second transistor as well as third and fourth transistor are each constructed identically.

Bei einer Ausgestaltung der Erfindung wird ein mit dem Ausgangsstrom gespeister Widerstand identisch zu einem zweiten Widerstand gewählt, von dem wiederum der Eingangsstrom abhängig ist. Schließlich wird der eine Widerstand derart ausgewählt, daß dessen Streuung gleich der Streuung von zweitem und dritten Widerstand ist.In one embodiment of the invention, a resistor fed with the output current is selected to be identical to a second resistor, on which the input current in turn is dependent. Finally, the one resistor is selected such that its scatter is equal to the scatter of the second and third resistor.

Bei dem in der einzigen Figuren der Zeichnung dargestellten Ausführungsbeispiel wird ein Eingangsstrom ie zum einen auf die miteinander gekoppelten Gateanschlüsse eines MOS-Transistors 1 und eines MOS-Transistors 2 und zum anderen unter Zwischenschaltung eines Widerstands 5 auf den Drainanschluß des Transistors 1 geführt ist. Der Sourceanschluß des Transistors 1 sowie der Sourceanschluß des Transistors 2 ist jeweils mit dem Drainanschluß eines MOS-Transistors 3 bzw. dem Drainanschluß eines MOS-Transistors 4 verbunden. Die Sourceanschlüsse der Transistoren 3 und 4 sind mit einem Versorgungspotential 6 beaufschlagt. Das Versorgungspotential 6 ist beim gezeigten Ausführungsbeispiel positiv, so daß es sich demzufolge bei den Transistoren 1 bis 4 um p-Kanal-Typen handelt. Bevorzugt sind nun die Transistoren 1 und 2 sowie die Transistoren 3 und 4 jeweils identisch aufgebaut, d.h., daß sie im wesentlichen gleiche Weiten- zu Längenverhältnisse der Kanäle und daher weitestgehend identische Eigenschaften aufweisen.In the exemplary embodiment shown in the single figures of the drawing, an input current i e is passed on the one hand to the mutually coupled gate connections of a MOS transistor 1 and a MOS transistor 2 and on the other hand with the interposition of a resistor 5 to the drain connection of the transistor 1. The source terminal of transistor 1 and the source terminal of transistor 2 are each connected to the drain terminal of a MOS transistor 3 and the drain terminal of a MOS transistor 4, respectively. The source connections of transistors 3 and 4 are supplied with a supply potential 6. The supply potential 6 is positive in the exemplary embodiment shown, so that the transistors 1 to 4 are consequently p-channel types acts. The transistors 1 and 2 and the transistors 3 and 4 are preferably each constructed identically, that is to say that they have essentially the same width to length ratios of the channels and therefore have largely identical properties.

Zur Erzeugung des Eingangsstroms ie ist eine Stromquellenschaltung vorgesehen, die einen durch einen Operationsverstärker 7 angesteuerten MOS-Transistor 8 vom n-Kanal-Typ sowie jeweils einen einerseits an ein negatives Versorgungspotential 9 angeschlossenen Widerstand 10 und eine an das Versorgungspotential 9 angeschlossene Referenzspannungsquelle 11 aufweist. Der andere Anschluß des Widerstands 10 ist dabei mit dem invertierenden Eingang des Operationsverstärkers 7 und mit dem Sourceanschluß des Transistors 8 gekoppelt. Der andere Anschluß der Referenzspannungsquelle 11 ist an den nichtinvertierenden Eingang des Operationsverstärkers 7 gelegt. Am Drainanschluß des Transistors 8 ist der Eingangsstrom ie eingeprägt. Er ist daher mit den Gateanschlüssen der Transistoren 1 und 2 sowie mit einem Anschluß des Widerstandes verbunden. Desweiteren wird der Ausgangsstrom ia über einen Widerstand 12 gegen das negative Versorgungspotential 9 geleitet. Da die Widerstände 10 und 12 identisch aufgebaut sind, ist die Spannung über beiden Widerständen gleich groß, nämlich gleich der Spannung der Referenzspannungsquelle 11. Durch den identischen Aufbau beider Widerstände 10 und 12 heben sich sämtliche, beispielsweise durch Temperaturschwankungen hervorgerufene oder fertigungsbedingte Streuungen vollständig auf. Darüber hinaus ist eine identische Ausbildung beider Widerstände insbesondere bei integrierter Schaltungstechnik sehr einfach und mit hoher Präzision durchzuführen. Wird nun auch der Widerstand 5 in gleicher Technik wie die beiden Widerstände 10 und 12 ausgeführt, wobei beispielsweise sein Widerstandswert nicht gleich dem der Widerstände 10 und 12 sein muß, so können auch dessen Streuungen weitestgehend kompensiert werden.To generate the input current i e , a current source circuit is provided which has a MOS transistor 8 of the n-channel type controlled by an operational amplifier 7 and a resistor 10 connected to a negative supply potential 9 and a reference voltage source 11 connected to the supply potential 9 . The other connection of the resistor 10 is coupled to the inverting input of the operational amplifier 7 and to the source connection of the transistor 8. The other connection of the reference voltage source 11 is connected to the non-inverting input of the operational amplifier 7. The input current i e is impressed at the drain connection of the transistor 8. It is therefore connected to the gate connections of transistors 1 and 2 and to a connection of the resistor. Furthermore, the output current i a is conducted via a resistor 12 to the negative supply potential 9. Since the resistors 10 and 12 are constructed identically, the voltage across the two resistors is the same, namely the voltage of the reference voltage source 11. The identical structure of the two resistors 10 and 12 completely eliminates any scatter, for example caused by temperature fluctuations or production-related variations. In addition, identical design of both resistors can be carried out very easily and with high precision, particularly in the case of integrated circuit technology. Now the resistor 5 is also in the same Technology as the two resistors 10 and 12 performed, for example, its resistance value does not have to be equal to that of the resistors 10 and 12, so its scatter can be largely compensated.

Abschließend sei darauf hingewiesen, daß zu einer weiteren Erhöhung der Rückwirkungsfreiheit vorteilhafterweise mehrere erfindungsgemäße Stromspiegel hintereinander geschaltet werden, wobei dementsprechend der Leitungstyp der Stromspiegel fortlaufend wechselt. Außerdem ist neben einer Ausführung in MOS-Technik auch eine Realisierung in Bipolartechnik ohne weiteres möglich.In conclusion, it should be pointed out that to further increase the freedom from interference, a plurality of current mirrors according to the invention are advantageously connected in series, the line type of the current mirror correspondingly changing accordingly. In addition to an implementation in MOS technology, implementation in bipolar technology is also readily possible.

Claims (4)

Stromspiegel, der durch einen Eingangsstrom (ie) angesteuert wird und der einen dazu proportionalen Ausgangsstrom (ia) abgibt,
dadurch gekennzeichnet, daß der Eingangsstrom (ie) zum einen auf die miteinander gekoppelten Steueranschlüsse eines ersten und zweiten Transistors (1, 2) und zum anderen unter Zwischenschaltung eines Widerstandes (5) auf einen Anschluß der Laststrecke des ersten Transistors (1) geführt ist,
daß der andere Anschluß des ersten Transistors (1) und ein Anschluß der Laststrecke des zweiten Transistors (2) jeweils über die Laststrecke eines dritten bzw. vierten Transistors (3, 4) an einen gemeinsamen Bezugspunkt angeschlossen sind, daß die miteinander gekoppelten Steueranschlüsse von drittem und viertem Transistor (3, 4) mit dem einen Anschluß des ersten Transistors (1) verbunden sind und
daß der Ausgangsstrom am anderen Anschluß des zweiten Transistors (2) abnehmbar ist.Current mirror which is driven by an input current (i e ) and which outputs an output current (i a ) proportional thereto,
characterized in that the input current (i e ) is conducted on the one hand to the interconnected control connections of a first and second transistor (1, 2) and on the other hand with the interposition of a resistor (5) to a connection of the load path of the first transistor (1) ,
that the other connection of the first transistor (1) and a connection of the load path of the second transistor (2) are each connected via the load path of a third or fourth transistor (3, 4) to a common reference point, that the control connections coupled to one another by a third and fourth transistor (3, 4) are connected to one terminal of the first transistor (1) and
that the output current at the other terminal of the second transistor (2) is removable. Stromspiegel nach Anspruch 1,
dadurch gekennzeichnet, daß erster und zweiter Transistors (1, 2) sowie dritter und vierter Transistor (3, 4) jeweils identisch aufgebaut sind.Current mirror according to claim 1,
characterized in that the first and second transistors (1, 2) and third and fourth transistors (3, 4) are each constructed identically. Stromspiegel nach Anspruch 1 oder 2,
dadurch gekennzeichnet, daß der Eingangsstrom (ie) von einem zweiten Widerstand (10) abhängig ist und daß mit dem Ausgangsstrom (ia) ein dem zweiten Widerstand (10) identischer dritter Widerstand (12) gespeist wird.Current mirror according to claim 1 or 2,
characterized in that the input current (i e ) is dependent on a second resistor (10) and that a third resistor (12) identical to the second resistor (10) is fed with the output current (i a ). Stromspiegelanordnung nach einem der Ansprüche 1 bis 3,
dadurch gekennzeichnet, daß zweiter und dritter Widerstand (10, 12) um einen identischen Faktor streuen.Current mirror arrangement according to one of claims 1 to 3,
characterized in that the second and third resistors (10, 12) scatter by an identical factor.
EP94113817A 1993-09-03 1994-09-02 Current mirror Expired - Lifetime EP0642070B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE4329868 1993-09-03
DE4329868 1993-09-03

Publications (2)

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EP0642070A1 true EP0642070A1 (en) 1995-03-08
EP0642070B1 EP0642070B1 (en) 1998-04-01

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EP94113817A Expired - Lifetime EP0642070B1 (en) 1993-09-03 1994-09-02 Current mirror

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EP (1) EP0642070B1 (en)
AT (1) ATE164692T1 (en)
DE (1) DE59405569D1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0953891A1 (en) * 1998-05-01 1999-11-03 STMicroelectronics Limited Current mirrors

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4550284A (en) * 1984-05-16 1985-10-29 At&T Bell Laboratories MOS Cascode current mirror
US4583037A (en) * 1984-08-23 1986-04-15 At&T Bell Laboratories High swing CMOS cascode current mirror
GB2209254A (en) * 1987-08-29 1989-05-04 Motorola Inc Current minor amplifier with reduced supply voltage sensitivity
US5142696A (en) * 1991-04-16 1992-08-25 Motorola, Inc. Current mirror having increased output swing

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4550284A (en) * 1984-05-16 1985-10-29 At&T Bell Laboratories MOS Cascode current mirror
US4583037A (en) * 1984-08-23 1986-04-15 At&T Bell Laboratories High swing CMOS cascode current mirror
GB2209254A (en) * 1987-08-29 1989-05-04 Motorola Inc Current minor amplifier with reduced supply voltage sensitivity
US5142696A (en) * 1991-04-16 1992-08-25 Motorola, Inc. Current mirror having increased output swing

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
AUS U. TIETZE, CH. SCHENK: "Halbleiter-Schaltungstechnik", 1986, pages: 62 - 64,94-97

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0953891A1 (en) * 1998-05-01 1999-11-03 STMicroelectronics Limited Current mirrors

Also Published As

Publication number Publication date
ATE164692T1 (en) 1998-04-15
EP0642070B1 (en) 1998-04-01
DE59405569D1 (en) 1998-05-07

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