GB2209254A

GB2209254A - Current minor amplifier with reduced supply voltage sensitivity

Info

Publication number: GB2209254A
Application number: GB8720474A
Authority: GB
Inventors: Andreas Rusznyak
Original assignee: Motorola Inc
Current assignee: Motorola Solutions Inc
Priority date: 1987-08-29
Filing date: 1987-08-29
Publication date: 1989-05-04
Anticipated expiration: 2007-08-29
Also published as: GB8720474D0; GB2209254B

Abstract

A current mirror comprises an input pair of transistors M1A and M1B, an output pair of transistors M2A and M2B and a subsidiary current mirror composed of a first pair of complementary transistors M3A and M3B and a second pair of complementary transistors M4A and M4B. The subsidiary current mirror is powered from a supply voltage VDD and is biased by an input voltage V1 to produce an output voltage which is used to control input and output transistors M1B and M2B so as to maintain them in saturation. With input and output transistors M1A and M2A being controlled by the input voltage V1, the current mirror has reduced sensitivity to supply voltage variation and also has an increased voltage range, being openable with lower supply voltages. <IMAGE>

Description

Current Mirror This invention relates to current mirrors and more particularly to a current mirror with extended operating range.

Current mirrors are well known and generally contain at least two pairs of transistors, one pair for receiving the input current and one pair for producing an output current which mirrors the input current. The input transistor of the first pair and the output transistor of the second pair are generally chosen to have drain-source voltage characteristics matching those of the other transistor of the respective pair so as to guarantee that mirroring of the current will be output. voltage independent.

One of the problems with this kind of current mirror is that the voltage range is limited at the lower end. As is known from an article "Switched Capacitor Filters for Communications Applications" by Choi et al in IEEE Journal of Solid-State Circuits Vol. SC-18 No. 16, Dec 1983, p. 661, it is possible to decrease this lower limit for the output by inserting a level shifting d.c. source between the gates of the input transistor of the first pair and the output transistor of the second pair. As explained in the article, by making the value of the level shift equal to the threshold voltage of the transistors, the lower limit of the voltage range for the output is reduced by an amount equal to the threshold voltage.

However, the above circuits only work when the input voltage to the input transistor of the first pair is at least twice as high as the threshold voltage. For. lower input voltages, the first pair of transistors cannot conduct.

Accordingly, the present invention provides a current mirror comprising first and second input transistors coupled respectively to an input node and a first reference potential line and connected in series therebetween, first and second output transistors coupled respectively to an output node and said first reference potential line and connected in series therebetween, wherein the control electrodes of the second input and second output transistors are coupled to said input node, and a subsidiary current mirror having an input coupled to said input node and an output coupled to the control electrodes of the first input and first output transistors.

In a preferred embodiment the subsidiary current mirror comprises first and second biasing transistors of complementary type coupled respectively to a second reference potential line and said first reference potential line and connected in series therebetween via a first node, the control electrode of the second biasing transistor forming the input of the subsidiary current mirror, and first and second bias mirror transistors of complementary type coupled respectively to said second reference potential line and said first reference potential line and connected in series therebetween via a second node, said second node forming the output of the subsidiary current mirror, the control electrode of said second bias mirror transistor is coupled to said second node and the control electrode of said first bias mirror transistor is coupled to the control electrode of said first biasing transistor and to said first node.

The current mirror is preferably formed in MOS technology. However such a current mirror may also be formed in bipolar technology.

The invention will now be more fully described by way of example with reference to the drawings of which: Figure 1 shows a well known current mirror; Figure 2 shows an improved known current mirror; and Figure 3 shows a current mirror according to the invention.

As described above, current mirrors are well known and generally comprise, as shown in Figure 1, two pairs of transistors; one pair for receiving an input current I1 and the second pair for producing an output current which mirrors the input current. The input pair is formed by two transistors M1B and M1A both coupled as diodes and connected in series between an input node 1 and a reference potential line 2. The output pair is formed by two transistors M2B and M2A connected in series between an output node 3 and the reference potential line 2 with the gate electrode of transistor M2B being coupled to the gate electrode of transistor M1B and the gate electrode of transistor M2A being coupled to the gate electrode of transistor M1A.In this way, transistors M1B and M2B match the drain-source voltage of transistors M1A and M2A to guarantee output-voltage-independent mirroring. In order to decrease the lower limit of the output voltage V2, it has been proposed to introduce an additional pair of transistors MTB and MTA as shown in Figure 2. This pair of transistors is connected in series between a power line VDD and the reference potential line 2, with the gate electrode of transistor MTB coupled to the gate electrode of transistor M1B and the gate electrode of transistor MTA coupled to the gate electrode of transistor M1A. In this case, however, the gate electrode of transistor M2B is coupled to the junction between transistors MTB and MTA. As discussed in the reference cited above, this extra pair of transistors inserted between the gate electrodes of transistors M1B and M2B acts as a level-shifting d.c. source.By making the value of this source equal to the threshold voltage VT of the transistors, the lower limit of the output voltage V2 is decreased by the amount VT.

However, the above current mirrors only work when the input voltage V1 is at least as high as twice the threshold voltage VT. If V1 is lower, the input pair M1B and M1A cannot conduct.

The input current may be defined by a resistor R connected between the input pair of transistors and the supply voltage VDD, as shown in dotted lines. In this case, however, the input current is very sensitive to variations in the supply voltage VDD, especially when the value of VDD is not much higher than twice the threshold voltage VT. It is thus an object of the present invention to reduce the sensitivity of the input current on the supply voltage VDD.

The current of a transistor controlled by a voltage V is defined by I = K(V-VT)2 where I is the current, VT is the threshold voltage and K is a constant for the particular transistor.

Solving for V-VT gives:

where V - VT is the gate-source voltage above VT required to sustain current I. Therefore, for the input pair of transistors in the current mirror of Figure 1, the current and voltages are described by:

if the transistors are matched and I1 is the input current.

Derivation of the equation leads to

or

Setting

the sensitivity

is expressed by

Thus, the loss of 2VT increases sensitivity.

Turning now to Figure 3, the current mirror according to the invention comprises an input pair of transistors M1B and M1A and an output pair of transistors M2B and M2A, as in Figures 1 and 2, but in this case a subsidiary current mirror composed of two pairs of complementary transistors M3A, M3B and M4A, M4B is provided between the input and output pairs.

The first pair of complementary transistors M3A and M3B of the subsidiary current mirror is biased by the input voltage V1 which also determines the input and output currents by biasing input transistor M1A and output transistor M2A. The current in the second pair of complementary transistors M4A and M4B of the subsidiary current mirror mirrors the current in the first pair so that the output voltage from the second pair at the junction between transistors M4A and M4B controls transistors M1B and M2B so as to maintain them in saturation. The subsidiary current mirror is powered by the supply voltage VDD, as shown, so that at start-up, the subsidiary current mirror produces an output voltage for biasing transistor M1B and current flows through the input pair of transistors M1B and M1A establishing steady-state operation.

The current mirror of Figure 3 thus not only reduces the lower limit of the voltage range by an amount equal to VT, as in the current mirror of Figure 2, but also reduces the sensitivity of the input current to variations in VDD by an amount equal to VT as given by

Claims

Claims 1. A current mirror comprising first and second input transistors coupled respectively to an input node and a first reference potential line and connected in series therebetween, first and second output transistors coupled respectively to an output node and said first reference potential line and connected in series therebetween, wherein the control electrodes of the second input and second output transistors are coupled to said input node, and a subsidiary current mirror having an input coupled to said input node and an output coupled to the control electrodes of the first input and first output transistors.
2. A current mirror according to claim 1 wherein said subsidiary current mirror comprises first and second biasing transistors of complementary type coupled respectively to a second reference potential line and said first reference potential line and connected in series therebetween via a first node, the control electrode of the second biasing transistor forming the input of the subsidiary current mirror, and first and second bias mirror transistors of complementary type coupled respectively to said second reference potential line and said first reference potential line and connected in series therebetween via a second node, said second node forming the output of the subsidiary current mirror and wherein the control electrode of said second bias mirror transistor is coupled to said second node and the control electrode of said first bias mirror transistor is coupled to the control electrode of said first biasing transistor and to said first node.
3. A current mirror according to any preceding claim wherein the transistors are formed in MOS technology.
4. A current mirror according to any one of claims 1 or 2 wherein the transistors are bipolar.
5. A current mirror substantially as hereinbefore described with reference to Figure 3 of the drawings.