EP0625277B1 - Flat screen having individually dipole-protected microdots - Google Patents

Flat screen having individually dipole-protected microdots Download PDF

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Publication number
EP0625277B1
EP0625277B1 EP94900903A EP94900903A EP0625277B1 EP 0625277 B1 EP0625277 B1 EP 0625277B1 EP 94900903 A EP94900903 A EP 94900903A EP 94900903 A EP94900903 A EP 94900903A EP 0625277 B1 EP0625277 B1 EP 0625277B1
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EP
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Prior art keywords
microtip
dipole
layer
flat
protected
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EP94900903A
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German (de)
French (fr)
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EP0625277A1 (en
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Michel Garcia
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Pixtech SA
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Pixel International SA
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J29/00Details of cathode-ray tubes or of electron-beam tubes of the types covered by group H01J31/00
    • H01J29/02Electrodes; Screens; Mounting, supporting, spacing or insulating thereof
    • H01J29/04Cathodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J1/00Details of electrodes, of magnetic control means, of screens, or of the mounting or spacing thereof, common to two or more basic types of discharge tubes or lamps
    • H01J1/02Main electrodes
    • H01J1/30Cold cathodes, e.g. field-emissive cathode
    • H01J1/304Field-emissive cathodes
    • H01J1/3042Field-emissive cathodes microengineered, e.g. Spindt-type
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2201/00Electrodes common to discharge tubes
    • H01J2201/30Cold cathodes
    • H01J2201/319Circuit elements associated with the emitters by direct integration

Definitions

  • the present invention relates to a screen microtip dish individually protected by dipole.
  • Known microtip screens are vacuum tubes generally consisting of two plates of thin glass tightly sealed the plate rear or cathode plate comprising an array array of field effect transmitters formed by microtips, and the front plate or anode plate being covered with a transparent conductive layer and phosphors.
  • each light point is associated with a cathodic emissive surface located opposite screw and made up of a large number of microtips (approximately 10,000 per mm2).
  • This emissive surface is defined by the intersection of a line (grid) and a column (cathode conductor) of the matrix.
  • a potential difference of less than 100 volts applied between row and column allows to get to the top of the peak, an electric field sufficient to cause electron emission and high luminance with a low voltage phosphor.
  • the main purpose of the resistive layer is to limit the current in each transmitter so to homogenize the electronic emission, and to limit the maximum current that would pass in the tip in case tip / grid short circuit.
  • the load characteristic which results from the placing in series, with the point, of a resistance is a line.
  • the voltage drop in this resistance is proportional to the current flowing through it and can prove to be quite significant if the current emitted by the tip is important.
  • the tension that must be applied to the tip-resistance protection system is increased by the same amount, which has consequences important on the consumption of the screen in particular.
  • the device according to the present invention proposes to solve these problems. It allows effect not only of getting an effective limitation of current flowing through each microtip by self-regulation of the emission current beyond a threshold, even if the tip is in direct contact with the grid, but also better homogeneity and efficient and simplified control of the screen luminance.
  • EP-A-0496572 describes a microtip flat screen in which the addressing system is integrated. Tripole components such as bipolar or MOS transistors are associated with microtips to order them.
  • An electron beam 11 emitted under vacuum by microtips 12 electrically connected to cathodic conductors and modulated by the potential of the grid 6 is accelerated towards the anode 9 where it excites the phosphors 10 (typical operation triode). Thanks to the short tip-anode distance, the focusing is obtained by proximity effect without no electronic optics.
  • each microtip 12 is protected against excess current by putting in series of a load resistor (fig 2).
  • This resistance generally consists of a layer resistive 3 of amorphous silicon (or other material resistant).
  • each microtip 12 is no longer by putting a series load resistance, but by the serialization of a dipole 13 whose voltage-current characteristic is not not linear.
  • This dipole consists of a transistor with field effect (FET), preferably of the grid type depleted insulator, whose drain D is connected to the microtip 12 and source S to conductor column 3 corresponding, the door or "gate" G (or pinch electrode) of each transistor being directly connected either to the source S or to the drain D.
  • FET transistor with field effect
  • This arrangement allows for a complete protection of microtip 12 against frank short circuits between tip and grid 6 by complete blockage of current in the tip.
  • the dipoles 13 will advantageously manufactured in integrated technology, on a substrate 14 single silicon (solid or thin layer), so that we can, by polarizing said substrate, which may be common to all the dipoles 13, modify globally (on all points in same time) the protection threshold and the level of emission current (modulation of the brightness of screen).
  • Figure 4 shows a partial section of a microtip emissive cathode protected by dipoles 13, these being made at from a P-type substrate 14 in which are formed of N-type overdoped zones 15 obtained by diffusion or other (establishment) and constituting the sources, channel 20 (depletion transistor) formed by example by an N-type ion implantation, as well than a layer of grid insulation 16 made of silica obtained by surface oxidation or deposit.
  • the electrode pinch 17 is created at the same time as the column conductor 3 by metallization. The point is carried out in the usual way, but is based on the transistor pinch gate.
  • drains located under the microtips are not overdoped, as usual in MOS structures classics.
  • the constituting field effect transistor the dipole 13 can advantageously have a circular geometry, its conduction channel being located all around microtip 12 (Figure 5).
  • dipole 13 The operation of dipole 13 is then next: The extraction voltage is applied to electrode 6 (grid). When this voltage is low (low enough for the voltage peak / source is less than the threshold of the transistor at depletion), the dipole in series with the tip 12 is, at roughly equivalent to the resistance of channel 20 implanted, its value is quite low.
  • the gate pinch 17 does its job and "pinch" channel 20 limiting the current in the dipole to a value (saturation current of the depletion transistor) which is, in the first order, more function than geometric dimensions of the assembly and of the tension of the substrate 14 relative to the source 15.
  • the emissive cathode can be itself realized on silicon in integrated technology.
  • the column conductors 3, and possibly the line conductors (or grid 6) may be made up of diffused layers, buried or not, with as an alternative to double, in places, the layer diffused by a metallization (positioned in a uncluttered area for example or so minimize coupling capacities)

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  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Cold Cathode And The Manufacture (AREA)
  • Cathode-Ray Tubes And Fluorescent Screens For Display (AREA)

Abstract

A flat screen having individually dipole-protected microdots and consisting of a field-emission cathode comprising microdots (12) individually protected by means of a series electrical coupling with a dipole (13) consisting of a depletion mode field effect transistor, said dipoles being designed to enable the protection threshold and the emission current level to be altered on all dots at once solely by changing the biasing of the substrate (14) common to said dipoles. Application in general to the field of display screens.

Description

La présente invention a pour objet un écran plat à micropointes protégées individuellement par dipôle.The present invention relates to a screen microtip dish individually protected by dipole.

Elle concerne d'une façon générale le domaine des écrans d'affichage ou de visualisation plats à adressage matriciel de toutes dimensions, et peut s'appliquer à tous les secteurs industriels utilisant des écrans de ce type: télévision, informatique, télécommunications, appareils de contrôle, installations de surveillance, etc.It generally concerns the field flat display or viewing screens matrix addressing of all sizes, and can apply to all industrial sectors using screens of this type: television, computers, telecommunications, control devices, monitoring facilities, etc.

Les écrans à micropointes connus sont des tubes à vide constitués en général de deux plaques de verre mince scellées de façon étanche, la plaque arrière ou plaque cathode comportant un réseau matriciel d'émetteurs à effet de champ formé de micropointes, et la plaque avant ou plaque anode étant recouverte d'une couche conductrice transparente et de luminophores.Known microtip screens are vacuum tubes generally consisting of two plates of thin glass tightly sealed the plate rear or cathode plate comprising an array array of field effect transmitters formed by microtips, and the front plate or anode plate being covered with a transparent conductive layer and phosphors.

A chaque point lumineux (pixel), est associé une surface émissive cathodique située vis à vis et constituée d'un grand nombre de micropointes (environ 10 000 par mm2). Cette surface émissive est définie par l'intersection d'une ligne (grille) et d'une colonne (conducteur cathodique) de la matrice.At each light point (pixel), is associated with a cathodic emissive surface located opposite screw and made up of a large number of microtips (approximately 10,000 per mm2). This emissive surface is defined by the intersection of a line (grid) and a column (cathode conductor) of the matrix.

Grâce à la faible distance pointe-grille (≤ 1 µm) et à l'effet amplificateur de la pointe, une différence de potentiel de moins de 100 volts appliquée entre ligne et colonne permet d'obtenir au sommet de la pointe, un champ électrique suffisant pour provoquer l'émission d'électrons et une luminance élevée avec un luminophore basse tension.Thanks to the short tip-grid distance (≤ 1 µm) and with the amplifying effect of the tip, a potential difference of less than 100 volts applied between row and column allows to get to the top of the peak, an electric field sufficient to cause electron emission and high luminance with a low voltage phosphor.

La structure classique de la cathode d'un écran à micropointes comprend en particulier, déposés successivement sur un substrat de verre ou de silicium:

  • Une couche d'isolation.
  • Une couche résistive de silicium ou autre matériau.
  • Les "conducteurs colonne" constitués d'une couche métallique qui peut être déposée soit dessous soit dessus la couche résistive.
  • Une couche isolante (Si ou SiO2) qui constitue l'isolant de grille.
  • Une couche métallique qui constitue la grille ou conducteurs de ligne.
The conventional structure of the cathode of a microtip screen comprises in particular, deposited successively on a glass or silicon substrate:
  • A layer of insulation.
  • A resistive layer of silicon or other material.
  • The "column conductors" consist of a metal layer which can be deposited either below or above the resistive layer.
  • An insulating layer (Si or SiO2) which constitutes the gate insulator.
  • A metallic layer which constitutes the grid or line conductors.

Après dépôt des susdites couches, il est pratiqué dans la grille et la couche isolante, par des techniques de gravure connues, des trous dans lesquels sont ensuite réalisées les micropointes.After depositing the above layers, it is practiced in the grid and the insulating layer, by known engraving, holes in which are then made the microtips.

La couche résistive a pour but essentiel de limiter le courant dans chaque émetteur afin d'homogénéiser l'émission électronique, et de limiter le courant maximum qui passerait dans la pointe en cas de court-circuit pointe/grille.The main purpose of the resistive layer is to limit the current in each transmitter so to homogenize the electronic emission, and to limit the maximum current that would pass in the tip in case tip / grid short circuit.

La caractéristique de charge qui résulte de la mise en série, avec la pointe, d'une résistance est une droite. La chute de tension dans cette résistance est proportionnelle au courant qui la traverse et peut s'avérer assez importante si le courant émis par la pointe est important. La tension qui doit être appliquée au système pointe-résistance de protection est augmentée d'autant, ce qui a des conséquences importantes sur la consommation de l'écran notamment. The load characteristic which results from the placing in series, with the point, of a resistance is a line. The voltage drop in this resistance is proportional to the current flowing through it and can prove to be quite significant if the current emitted by the tip is important. The tension that must be applied to the tip-resistance protection system is increased by the same amount, which has consequences important on the consumption of the screen in particular.

Le dispositif selon la présente invention se propose de résoudre ces problèmes. Il permet en effet non seulement d'obtenir une limitation efficace du courant traversant chaque micropointe par autorégulation du courant d'émission au delà d'un seuil, même si la pointe est en contact direct avec la grille, mais également une meilleure homogénéité d'émission, ainsi qu'un contrôle efficace et simplifié de la luminance de l'écran.The device according to the present invention proposes to solve these problems. It allows effect not only of getting an effective limitation of current flowing through each microtip by self-regulation of the emission current beyond a threshold, even if the tip is in direct contact with the grid, but also better homogeneity and efficient and simplified control of the screen luminance.

Il est constitué d'une cathode émissive d'écran plat à émission de champ comportant des micropointes protégées chacune individuellement grâce à un couplage électrique en série avec un dipôle formé d'un transistor à effet de champ à déplétion. La caractéristique courant-tension d'un tel dipôle n'est pas linéaire. Ces dipôles pouvant être réalisés de telle façon que l'on puisse modifier de façon globale (sur toutes les pointes en même temps) le seuil de protection et le niveau du courant d'émission et donc la brillance de l'écran, en agissant uniquement sur la polarisation du substrat commun de ces dipôles, ou groupes de dipôles.It consists of an emissive cathode field emission flat screen with microtips each protected individually thanks to an electrical coupling in series with a formed dipole a depletion field effect transistor. The current-voltage characteristic of such a dipole is not linear. These dipoles can be made of so that we can modify globally (on all points at the same time) the threshold of protection and the level of the emission current and therefore screen brightness, acting only on the polarization of the common substrate of these dipoles, or dipole groups.

EP-A-0496572 décrit un écran plat à micropointes dans lequel le système d'adressage est intégré. Des composants tripôle tels que des transistors bipolaires ou MOS sont associés aux micropointes pour les commander.EP-A-0496572 describes a microtip flat screen in which the addressing system is integrated. Tripole components such as bipolar or MOS transistors are associated with microtips to order them.

L'article de U. Tietze et Ch. Schenk, Springer-Verlag 1980, pages 87-88, enseigne l'utilisation d'un transistor MOS comme source de courant.Article by U. Tietze and Ch. Schenk, Springer-Verlag 1980, pages 87-88, teaches the use of a MOS transistor as a power source.

Sur les dessins schématiques annexés, donnés à titre d'exemple non limitatif d'une des formes de réalisation de l'objet de l'invention:

  • la figure 1 est une coupe transversale illustrant le principe de fonctionnement d'un écran à micropointes connu,
  • la figure 2 est un schéma symbolique élémentaire d'une micropointe de la figure 1,
  • la figure 3 est un schéma symbolique élémentaire d'une micropointe protégée individuellement par un dipôle,
  • la figure 4 représente la coupe transversale d'une cathode émissive à micropointes utilisée dans l'invention,
  • et la figure 5 est une coupe partielle montrant en perspective le canal du transistor à effet de champ autour de la micropointe.
  • In the appended schematic drawings, given by way of nonlimiting example of one of the embodiments of the subject of the invention:
  • FIG. 1 is a cross section illustrating the operating principle of a known microtip screen,
  • FIG. 2 is an elementary symbolic diagram of a microtip of FIG. 1,
  • FIG. 3 is an elementary symbolic diagram of a microtip individually protected by a dipole,
  • FIG. 4 represents the cross section of an emissive cathode with microtips used in the invention,
  • and FIG. 5 is a partial section showing in perspective the channel of the field effect transistor around the microtip.
  • Le principe de base d'un écran à micropointes est schématisé sur la figure 1, sur laquelle on voit successivement de bas en haut (en pratique d'arrière en avant):The basic principle of a screen microtips is shown schematically in Figure 1, on which we see successively from bottom to top (in back to front practice):

    Une plaque 1 de verre ou de silicium, une sous-couche d'enrobage 2, les conducteurs cathodiques ou conducteurs colonnes 3, une couche résistive 4, une couche isolante 5, les conducteurs de ligne ou grille 6, un espace vide 7 et une couche de verre avant 8 recouverte sur sa face interne d'une couche conductrice transparente constituant l'anode 9, et de luminophores 10.A plate 1 of glass or silicon, a coating sublayer 2, the cathode conductors or column conductors 3, a resistive layer 4, a insulating layer 5, the line or grid conductors 6, an empty space 7 and a layer of front glass 8 covered on its inner face with a conductive layer transparent constituting the anode 9, and phosphors 10.

    Un faisceau d'électrons 11 émis sous vide par les micropointes 12 reliées électriquement aux conducteurs cathodiques et modulé par le potentiel de la grille 6 est accéléré en direction de l'anode 9 où il excite les luminophores 10 (fonctionnement type triode). Grâce à la faible distance pointe-anode, la focalisation est obtenue par effet de proximité sans aucune optique électronique.An electron beam 11 emitted under vacuum by microtips 12 electrically connected to cathodic conductors and modulated by the potential of the grid 6 is accelerated towards the anode 9 where it excites the phosphors 10 (typical operation triode). Thanks to the short tip-anode distance, the focusing is obtained by proximity effect without no electronic optics.

    Dans ce type de cathode, chaque micropointe 12 est protégée contre un excès de courant par la mise en série d'une résistance de charge (fig 2). Cette résistance est constituée en général par une couche résistive 3 de silicium amorphe (ou autre matériau résistant).In this type of cathode, each microtip 12 is protected against excess current by putting in series of a load resistor (fig 2). This resistance generally consists of a layer resistive 3 of amorphous silicon (or other material resistant).

    Dans un écran plat avec cathode émissive selon l'invention, la protection de chaque micropointe 12 est réalisée, non plus par la mise en série d'une résistance de charge, mais par la mise en série d'un dipôle 13 dont la caractéristique tension-courant n'est pas linéaire. Ce dipôle est constitué d'un transistor à effet de champ (FET), de préférence du type à grille isolée à déplétion, dont le drain D est connecté à la micropointe 12 et la source S au conducteur colonne 3 correspondant, la porte ou "gate" G (ou encore électrode de pincement) de chaque transistor étant directement reliée soit à la source S soit au drain D.In a flat screen with emissive cathode according to the invention, the protection of each microtip 12 is no longer by putting a series load resistance, but by the serialization of a dipole 13 whose voltage-current characteristic is not not linear. This dipole consists of a transistor with field effect (FET), preferably of the grid type depleted insulator, whose drain D is connected to the microtip 12 and source S to conductor column 3 corresponding, the door or "gate" G (or pinch electrode) of each transistor being directly connected either to the source S or to the drain D.

    Cette disposition permet de réaliser une protection complète de la micropointe 12 contre les court-circuits francs entre pointe et grille 6 par blocage complet du courant dans la pointe.This arrangement allows for a complete protection of microtip 12 against frank short circuits between tip and grid 6 by complete blockage of current in the tip.

    Les dipôles 13 seront avantageusement fabriqués en technologie intégrée, sur un substrat 14 unique de silicium (massif ou en couche mince), de manière à ce que l'on puisse, en polarisant ledit substrat, pouvant être commun à tous les dipôles 13, modifier de façon globale (sur toutes les pointes en même temps) le seuil de protection et le niveau du courant d'émission (modulation de la brillance de l'écran).The dipoles 13 will advantageously manufactured in integrated technology, on a substrate 14 single silicon (solid or thin layer), so that we can, by polarizing said substrate, which may be common to all the dipoles 13, modify globally (on all points in same time) the protection threshold and the level of emission current (modulation of the brightness of screen).

    A titre d'exemple, la figure 4 montre une coupe partielle d'une cathode émissive à micropointes protégées par dipôles 13, ceux-ci étant réalisés à partir d'un substrat 14 de type P dans lequel sont formées des zones surdopées 15 de type N obtenues par diffusion ou autre (implantation) et constituant les sources, le canal 20 (transistor à déplétion) formé par exemple par une implantaion ionique de type N, ainsi qu'une couche d'isolation de grille 16 en silice obtenue par oxydation de surface ou dépôt. L'électrode de pincement 17 est créée en même temps que le conducteur de colonne 3 par métallisation. La pointe est réalisée de façon habituelle, mais repose sur la grille de pincement du transistor. De préférence, les drains situés sous les micropointes ne sont pas surdopés, comme habituellement dans les structures MOS classiques.As an example, Figure 4 shows a partial section of a microtip emissive cathode protected by dipoles 13, these being made at from a P-type substrate 14 in which are formed of N-type overdoped zones 15 obtained by diffusion or other (establishment) and constituting the sources, channel 20 (depletion transistor) formed by example by an N-type ion implantation, as well than a layer of grid insulation 16 made of silica obtained by surface oxidation or deposit. The electrode pinch 17 is created at the same time as the column conductor 3 by metallization. The point is carried out in the usual way, but is based on the transistor pinch gate. Preferably, drains located under the microtips are not overdoped, as usual in MOS structures classics.

    Le transistor à effet de champ constituant le dipôle 13 peut avantageusement présenter une géométrie circulaire, son canal de conduction étant situé tout autour de la micropointe 12 (figure 5).The constituting field effect transistor the dipole 13 can advantageously have a circular geometry, its conduction channel being located all around microtip 12 (Figure 5).

    Le fonctionnement du dipôle 13 est alors le suivant: La tension d'extraction est appliquée sur l'électrode 6 (grille). Lorsque cette tension est faible (suffisamment faible pour que la tension pointe/source soit inférieure au seuil du transistor à déplétion), le dipôle en série avec la pointe 12 est, à peu près, équivalent à la résistance du canal 20 implanté, sa valeur est assez faible. Lorsque la tension d'extraction augmente de telle sorte que la tension pointe/source soit de l'ordre, ou supérieure, au seuil dudit transistor à déplétion, la grille de pincement 17 fait son office et "pince" le canal 20 limitant le courant dans le dipôle à une valeur (courant de saturation du transistor à déplétion) qui n'est, au premier ordre, plus fonction que des dimensions géométriques de l'ensemble et de la tension du substrat 14 par rapport à la source 15. La perte de tension dans le dipôle n'étant plus elle-même fonction du courant dans la pointe, mais uniquement de la tension de seuil dudit transistor à déplétion. En fait chaque pointe se verra traversée par le courant de saturation du transistor à déplétion qui la protège. Les géométries desdits transistors étant identiques, les courants dans les pointes (quelles que soient les caractéristiques propres d'émission des pointes) seront identiques.The operation of dipole 13 is then next: The extraction voltage is applied to electrode 6 (grid). When this voltage is low (low enough for the voltage peak / source is less than the threshold of the transistor at depletion), the dipole in series with the tip 12 is, at roughly equivalent to the resistance of channel 20 implanted, its value is quite low. When the extraction voltage increases so that the tip / source voltage either around, or higher, at the threshold of said depletion transistor, the gate pinch 17 does its job and "pinch" channel 20 limiting the current in the dipole to a value (saturation current of the depletion transistor) which is, in the first order, more function than geometric dimensions of the assembly and of the tension of the substrate 14 relative to the source 15. The loss of voltage in the dipole no longer itself a function current in the tip, but only threshold voltage of said depletion transistor. In fact each point will be crossed by the current of saturation of the depletion transistor which protects it. The geometries of said transistors being identical, the currents in the points (whatever the specific emission characteristics) identical.

    La cathode émissive peut être elle-même réalisée sur silicium en technologie intégrée. Dans ce cas, les conducteurs de colonnes 3, et éventuellement les conducteurs de lignes (ou grille 6) pourront être constitués de couches diffusées, enterrées ou non, avec comme alternative de doubler, par endroit, la couche diffusée par une métallisation (positionnée dans un secteur non encombré par exemple ou de telle sorte à minimiser les capacités de couplage)The emissive cathode can be itself realized on silicon in integrated technology. In this case, the column conductors 3, and possibly the line conductors (or grid 6) may be made up of diffused layers, buried or not, with as an alternative to double, in places, the layer diffused by a metallization (positioned in a uncluttered area for example or so minimize coupling capacities)

    Le positionnement des divers éléments constitutifs donne à l'objet de l'invention un maximum d'effets utiles qui n'avaient pas été, à ce jour, obtenus par des dispositifs similaires.The positioning of the various elements constitutive gives the object of the invention a maximum useful effects that had not been, to date, obtained by similar devices.

    Claims (5)

    1. A flat microtip screen, characterized in that each microtip (12) is connected with a column conductor (3) through a dipole (13) constituted of a depletion field effect transistor having a drain connected with the microtip, a source connected to the column conductor and an insulated gate directly connected to said source or drain.
    2. A flat microtip screen according to claim 1, characterized in that it comprises a silicon layer (14) of a first conductivity type and, in association with each microtip:
      a first region (15) of a second conductivity type having a high doping level formed in said layer (14) and connected with a cathode conductor (3);
      a second region (20) of the second conductivity type with a low doping level formed in said layer (14), adjacent to the first region (15) and coated with an insulating layer (16) provided with an aperture;
      a conductive layer (17) extending on said aperture and over said insulating layer (16) between said aperture and said first region; and
      a microtip (12) formed above said conductive layer.
    3. A flat microtip screen according to claim 2, characterized in that the aperture, the microtip, the conductive layer, the second and first regions of the second conductivity type are concentric.
    4. A flat microtip screen according to claim 2 or 3, characterized in that said column conductors are made of regions diffused in said silicon layer.
    5. A flat microtip screen according to any of claims 2 to 4, characterized in that it further comprises means for modifying the substrate biasing of said depletion field effect transistors.
    EP94900903A 1992-12-04 1993-12-03 Flat screen having individually dipole-protected microdots Expired - Lifetime EP0625277B1 (en)

    Applications Claiming Priority (3)

    Application Number Priority Date Filing Date Title
    FR9214893 1992-12-04
    FR9214893A FR2698992B1 (en) 1992-12-04 1992-12-04 Flat screen with microtips individually protected by dipole.
    PCT/FR1993/001190 WO1994014153A1 (en) 1992-12-04 1993-12-03 Flat screen having individually dipole-protected microdots

    Publications (2)

    Publication Number Publication Date
    EP0625277A1 EP0625277A1 (en) 1994-11-23
    EP0625277B1 true EP0625277B1 (en) 1998-06-17

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    EP (1) EP0625277B1 (en)
    JP (1) JP3486904B2 (en)
    DE (1) DE69319225T2 (en)
    FR (1) FR2698992B1 (en)
    WO (1) WO1994014153A1 (en)

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    US5514937A (en) * 1994-01-24 1996-05-07 Motorola Apparatus and method for compensating electron emission in a field emission device
    JP3026484B2 (en) * 1996-08-23 2000-03-27 日本電気株式会社 Field emission cold cathode
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    Also Published As

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    WO1994014153A1 (en) 1994-06-23
    FR2698992A1 (en) 1994-06-10
    EP0625277A1 (en) 1994-11-23
    FR2698992B1 (en) 1995-03-17
    DE69319225D1 (en) 1998-07-23
    DE69319225T2 (en) 1998-11-19
    JP3486904B2 (en) 2004-01-13
    JPH07506456A (en) 1995-07-13

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