EP0616710A1 - Signal handling system with a shared data memory - Google Patents

Signal handling system with a shared data memory

Info

Publication number
EP0616710A1
EP0616710A1 EP93923104A EP93923104A EP0616710A1 EP 0616710 A1 EP0616710 A1 EP 0616710A1 EP 93923104 A EP93923104 A EP 93923104A EP 93923104 A EP93923104 A EP 93923104A EP 0616710 A1 EP0616710 A1 EP 0616710A1
Authority
EP
European Patent Office
Prior art keywords
bus
processors
access
signal processors
data memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP93923104A
Other languages
German (de)
French (fr)
Inventor
Lars Svensson
Johan Zeberg
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefonaktiebolaget LM Ericsson AB
Original Assignee
Telefonaktiebolaget LM Ericsson AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget LM Ericsson AB filed Critical Telefonaktiebolaget LM Ericsson AB
Publication of EP0616710A1 publication Critical patent/EP0616710A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1663—Access to shared memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox

Definitions

  • Si ⁇ nal handling system with a shared data memory Si ⁇ nal handling system with a shared data memory.
  • the present invention relates to a signal processing system, including a superior control processor, a number of digital signal processors, which are controlled by the control processor and normally operate internally with real time applications, a shared data memory with a bus, on which the control processor normally is bus master, and to which the signal processors have access, and an arbitration logic, which controls the access of the processors to the shared data memory.
  • SE-B-442,352 a data processing system of essentially the kind indicated by way of introduction is known.
  • the system includes a central computer, a bus, a memory, a plurality of peripheral computers, and an arbitration logic controlling the access of the computers to the memory.
  • a central computer As appears from page 2, from line 14, in this document, has normally, however, in this system only the central computer access to the memory via the bus, whereas the peripheral computers are disconnected from the bus line.
  • a processor system including a superior control processor and a number of subordinate processors.
  • An arbitration circuit controls all access to a common memory from buses connecting together the subordinate processors and includes address lines and data lines.
  • a bus assigning function in the arbitration circuit provides sequencial bus access for the subordinate processors.
  • a bus access logic in each such processor controls request for access to the bus.
  • US-A-5,067,071 describes and shows a multiprocessor system with a memory shared by all processor modules.
  • a bus arbitration function is arranged in a system control module for controlling the access of the processors to the common memory.
  • the data buses and address buses of the processor modules are connected via tranceivers to the common system bus.
  • the system handles request and access.
  • ES-A-4,499,538 relates to access arbitration for a system with several processors and a common bus.
  • a common resource consists of a number of memories.
  • a plurality of processors can via a bus obtain access to the common resource.
  • Each one of the processors has assigned thereto an own arbitration function.
  • EP-Al-464,708 there is described a bus system with a number of processors and a common memory.
  • a central circuit includes arbitration logic for handling access of the processors to the common memory.
  • US-A-4,803,617 describes a multiprocessor system with a common mass memory. Each processor emits a request when it needs access to a position in the main memory via the bus. During the time data transaction is performed all other processors must wait for the bus being free. An arbitrator arranges access of the processors to the bus.
  • the object of the present invention is to minimize, in a signal processing system of the kind defined by way of introduction, the number of necessary components, and suggest a solution where access to the shared memory can be attained with short delay and without master-slave configuration and external buffers.
  • the system shown in Fig. 1 includes five microprocessors, viz. one superior control processor 2 and four digital signal processors 4, 6, 8 and 10.
  • the processors 2-10 have a common link 12, having as a first function to serve as a signalling channel, via which the control processor 2 performs operation and maintainance functions as well as certain real time operations.
  • the digital signal processors 4, 6, 8 and 10 perform real time operations and execute programs internally.
  • the control processor 2 has an external program memory in the form of a PROM 14.
  • This PROM 14 also includes application programs for the digital signal processors 4, 6, 8 and 10.
  • the link 12 also serves for transferring the application program from the processor 2 to the digital signal processors, one at a time.
  • a RAM 18 is a shared memory between the control processor 2 and the signal processors 4-10. To this RAM 18 a bus 20, indicated with dashed lines, leads, that includes data buses and address buses as well as read strobes and write strobes.
  • the control processor 2 is normally bus master for the bus 20 and the signal processors are directly connected to the bus 20 by means of their own buses 22.
  • the signal processors 4, 6, 8 and 10 have an inner RAM (not shown) for programs and data, as well as an inner ROM (not shown) for start up programs. This implies that each signal processor can operate internally with its own application program. This application program contains instructions for keeping the bus 22 of the corresponding signal processor on a high impedance level. No external data access occurs except when the signal processor desires to use the shared memory 18.
  • the signal processors 4-10 keep their buses 22 on a high impedance level and are directly connected to the bus 20 without mediation by any external buffer.
  • the four signal processors are designed to send, in case of desired access to the memory 18, an inquiry signal to an arbitration logic 28 for the bus 20 via each an inquiry line 30.1, 30.2, 30.3 and 30.4, respectively, and to receive a confirmation, if any, on the request from the arbitration logic via each a confirmation line 32.1, 32.2, 32.3 and 32.4, respectively.
  • One purpose of the arbitration logic 28 is to send, at receipt of a demand for bus access in the form of such an inquiry signal from any of the signal processors, a corresponding demand to the control processor via a line 34. If the bus 20 is available the control processor replies via a line 36 to the arbitration logic 28 with a signal implying that the demand has been accepted. The arbitration logic then informs this to the inquiring signal processor via the confirmation line of the latter. Thereby the ownership to the bus 20 is transferred to the signal processor in question.
  • the arbitration logic 28 will let the request wait until the bus becomes free. If more signal processors simultaneously have requested the bus it is assigned by rotating assignment.
  • the block diagram on the drawing also includes a time slot assignment logic 38 controlled from the control processor 2 and distributing the time slots of the PCM channels to the different signal processors 4-10.
  • the distribution is completely free which implies that a time slot can be taken care of by any of the four signal processors.
  • the logic 38 generates synchronization pulses, one for each time slot, both for the sending and for the receiving direction. The pulses are generated to all signal processors working in the configuration in question. If no time slot is active no pulses are generated by the logic 38.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)

Abstract

Un système de traitement de signaux comprend un processeur pilote (2) supérieur et un nombre de processeurs (4-10) de signaux numériques qui sont commandés par le processeur pilote et fonctionnent normalement en interne avec des applications en temps réel. Une mémoire de données partagée (18) est pourvue d'un bus (20) pour lequel le processeur pilote a normalement le rôle de maître de bus, et auquel ont accès les processeurs de signaux. Une logique d'arbitrage (28) commande l'accès des processeurs (4-10) à la mémoire de données partagée. Les processeurs de signaux (4-10) sont reliés directement au bus (20) et maintiennent normalement leurs données et bus d'adresses (22) à un niveau d'impédance élevé par rapport à celui-ci.A signal processing system includes an upper master processor (2) and a number of digital signal processors (4-10) which are controlled by the master processor and normally operate internally with real-time applications. A shared data memory (18) is provided with a bus (20) for which the master processor normally has the role of bus master, and to which the signal processors have access. Arbitration logic (28) controls access of the processors (4-10) to the shared data memory. The signal processors (4-10) are directly connected to the bus (20) and normally maintain their data and address buses (22) at a high impedance level relative thereto.

Description

Siσnal handling system with a shared data memory.
Technical field of the invention.
The present invention relates to a signal processing system, including a superior control processor, a number of digital signal processors, which are controlled by the control processor and normally operate internally with real time applications, a shared data memory with a bus, on which the control processor normally is bus master, and to which the signal processors have access, and an arbitration logic, which controls the access of the processors to the shared data memory.
Description of related art.
Common to known earlier circuits of the kind defined by way of introduction is that they require external buffers between each signal processor and the bus.
Through SE-B-442,352 a data processing system of essentially the kind indicated by way of introduction is known. The system includes a central computer, a bus, a memory, a plurality of peripheral computers, and an arbitration logic controlling the access of the computers to the memory. As appears from page 2, from line 14, in this document, has normally, however, in this system only the central computer access to the memory via the bus, whereas the peripheral computers are disconnected from the bus line.
Through GB-A-1,600,756 a processor system is known including a superior control processor and a number of subordinate processors. An arbitration circuit controls all access to a common memory from buses connecting together the subordinate processors and includes address lines and data lines. A bus assigning function in the arbitration circuit provides sequencial bus access for the subordinate processors. A bus access logic in each such processor controls request for access to the bus.
US-A-5,067,071 describes and shows a multiprocessor system with a memory shared by all processor modules. A bus arbitration function is arranged in a system control module for controlling the access of the processors to the common memory.
The data buses and address buses of the processor modules are connected via tranceivers to the common system bus. The system handles request and access.
ES-A-4,499,538 relates to access arbitration for a system with several processors and a common bus. A common resource consists of a number of memories. A plurality of processors can via a bus obtain access to the common resource.
Each one of the processors has assigned thereto an own arbitration function.
In EP-Al-464,708 there is described a bus system with a number of processors and a common memory. A central circuit includes arbitration logic for handling access of the processors to the common memory.
US-A-4,803,617 describes a multiprocessor system with a common mass memory. Each processor emits a request when it needs access to a position in the main memory via the bus. During the time data transaction is performed all other processors must wait for the bus being free. An arbitrator arranges access of the processors to the bus.
From US-A-4,924,380 a similar system as that just described is known. Beyond this, technique is described for providing a better bus effectivity by means of an arbitration system consisting of two rotating queues with a fixed priority between the queues.
Summary of the invention.
The object of the present invention is to minimize, in a signal processing system of the kind defined by way of introduction, the number of necessary components, and suggest a solution where access to the shared memory can be attained with short delay and without master-slave configuration and external buffers.
This object has been attained in that, in accordance with the invention, the signal processors are directly connected to the bus and normally keep their data and adress buses on a high impedance level with respect thereto.
Brief description of the drawing.
The invention will now be described more closely with reference to a schematic block diagram of a signal handling system shown on the attached drawing. Preferred embodiment.
The system shown in Fig. 1 includes five microprocessors, viz. one superior control processor 2 and four digital signal processors 4, 6, 8 and 10. The processors 2-10 have a common link 12, having as a first function to serve as a signalling channel, via which the control processor 2 performs operation and maintainance functions as well as certain real time operations. The digital signal processors 4, 6, 8 and 10 perform real time operations and execute programs internally.
The control processor 2 has an external program memory in the form of a PROM 14. This PROM 14 also includes application programs for the digital signal processors 4, 6, 8 and 10. The link 12 also serves for transferring the application program from the processor 2 to the digital signal processors, one at a time.
A RAM 18 is a shared memory between the control processor 2 and the signal processors 4-10. To this RAM 18 a bus 20, indicated with dashed lines, leads, that includes data buses and address buses as well as read strobes and write strobes. The control processor 2 is normally bus master for the bus 20 and the signal processors are directly connected to the bus 20 by means of their own buses 22.
The signal processors 4, 6, 8 and 10 have an inner RAM (not shown) for programs and data, as well as an inner ROM (not shown) for start up programs. This implies that each signal processor can operate internally with its own application program. This application program contains instructions for keeping the bus 22 of the corresponding signal processor on a high impedance level. No external data access occurs except when the signal processor desires to use the shared memory 18.
Data from/to a PCM channel 24 with an input PCMA and an output PCMB are clocked in/out via serial ports 26 of the signal processors.
As mentioned the signal processors 4-10 keep their buses 22 on a high impedance level and are directly connected to the bus 20 without mediation by any external buffer. The four signal processors are designed to send, in case of desired access to the memory 18, an inquiry signal to an arbitration logic 28 for the bus 20 via each an inquiry line 30.1, 30.2, 30.3 and 30.4, respectively, and to receive a confirmation, if any, on the request from the arbitration logic via each a confirmation line 32.1, 32.2, 32.3 and 32.4, respectively.
One purpose of the arbitration logic 28 is to send, at receipt of a demand for bus access in the form of such an inquiry signal from any of the signal processors, a corresponding demand to the control processor via a line 34. If the bus 20 is available the control processor replies via a line 36 to the arbitration logic 28 with a signal implying that the demand has been accepted. The arbitration logic then informs this to the inquiring signal processor via the confirmation line of the latter. Thereby the ownership to the bus 20 is transferred to the signal processor in question.
If the bus 20 is requested by any signal processor when it is owned by the control processor 2 and not available, i.e. the latter uses the bus, the arbitration logic 28 will let the request wait until the bus becomes free. If more signal processors simultaneously have requested the bus it is assigned by rotating assignment.
The block diagram on the drawing also includes a time slot assignment logic 38 controlled from the control processor 2 and distributing the time slots of the PCM channels to the different signal processors 4-10. The distribution is completely free which implies that a time slot can be taken care of by any of the four signal processors. The logic 38 generates synchronization pulses, one for each time slot, both for the sending and for the receiving direction. The pulses are generated to all signal processors working in the configuration in question. If no time slot is active no pulses are generated by the logic 38.
At 40 and 42 input and output signalling channels to the control processor are indicated.
Certain details and functions in the system shown and described have not been described in more detail above. In such cases it has been presumed that it is the question either of matter, about which the man of the art does not need any closer information for being able to practice the invention, or matter not having any relationship with the invention.

Claims

Claims.
1. A signal processing system, including a superior control processor (2) , a number of digital signal processors (4-10) , which are controlled by the control processor and normally operate internally with real time applications, a shared data memory (18) with a bus (20) , on which the control processor normally is bus master, and to which the signal processors have access, and an arbitration logic (28) , which controls the access of the processors (4-10) to the shared data memory, characterized in that the signal processors (4-10) are directly connected to the bus (20) and normally keep their data and address buses (22) on a high impedance level with respect thereto.
EP93923104A 1992-10-14 1993-10-14 Signal handling system with a shared data memory Withdrawn EP0616710A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
SE9203016A SE9203016L (en) 1992-10-14 1992-10-14 Signal processing system with shared data memory
SE9203016 1992-10-14
PCT/SE1993/000840 WO1994009437A1 (en) 1992-10-14 1993-10-14 Signal handling system with a shared data memory

Publications (1)

Publication Number Publication Date
EP0616710A1 true EP0616710A1 (en) 1994-09-28

Family

ID=20387474

Family Applications (1)

Application Number Title Priority Date Filing Date
EP93923104A Withdrawn EP0616710A1 (en) 1992-10-14 1993-10-14 Signal handling system with a shared data memory

Country Status (4)

Country Link
EP (1) EP0616710A1 (en)
AU (1) AU5290093A (en)
SE (1) SE9203016L (en)
WO (1) WO1994009437A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2283596B (en) * 1993-11-01 1998-07-01 Ericsson Ge Mobile Communicat Multiprocessor data memory sharing
GB9418753D0 (en) * 1994-09-16 1994-11-02 Ionica L3 Limited Process circuitry
US6691216B2 (en) * 2000-11-08 2004-02-10 Texas Instruments Incorporated Shared program memory for use in multicore DSP devices
GB0031763D0 (en) * 2000-12-29 2001-02-07 Mitel Semiconductor Ltd Arbiter for a queue management system

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2462745B1 (en) * 1979-07-30 1986-01-03 Jeumont Schneider DEVICE FOR TEMPORAL SHARING OF ACCESS TO A MEMORY CONNECTED TO A SINGLE BUS BETWEEN A CENTRAL COMPUTER AND A PLURALITY OF PERIPHERAL COMPUTERS
JPS56140459A (en) * 1980-04-04 1981-11-02 Hitachi Ltd Data processing system
US4504906A (en) * 1982-11-30 1985-03-12 Anritsu Electric Company Limited Multiprocessor system
US5067071A (en) * 1985-02-27 1991-11-19 Encore Computer Corporation Multiprocessor computer system employing a plurality of tightly coupled processors with interrupt vector bus

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9409437A1 *

Also Published As

Publication number Publication date
SE9203016D0 (en) 1992-10-14
WO1994009437A1 (en) 1994-04-28
AU5290093A (en) 1994-05-09
SE9203016L (en) 1994-04-15

Similar Documents

Publication Publication Date Title
US4985830A (en) Interprocessor bus switching system for simultaneous communication in plural bus parallel processing system
US4807184A (en) Modular multiple processor architecture using distributed cross-point switch
NL192228C (en) Interrupt system.
US5737757A (en) Cache tag system for use with multiple processors including the most recently requested processor identification
EP0317466A2 (en) Reverse flow control mechanism and method
EP0280251B1 (en) Shared memory controller arrangement
US5255372A (en) Apparatus for efficiently interconnecing channels of a multiprocessor system multiplexed via channel adapters
WO1982002442A1 (en) Interrupt coupling and monitoring system
US5204954A (en) Remote storage management mechanism and method
EP0317481A2 (en) Remote storage management mechanism and method
US5708784A (en) Dual bus computer architecture utilizing distributed arbitrators and method of using same
EP0059731A1 (en) Processor interconnection system
US6421756B1 (en) Buffer assignment for bridges
US5530904A (en) System for tranferring data from one communication line to another using a multiplexer for selecting the lines and transferring data without intervention of a main processor
EP0616710A1 (en) Signal handling system with a shared data memory
US4658353A (en) System control network for multiple processor modules
US5206936A (en) Apparatus for exchanging channel adapter status among multiple channel adapters
EP0577431B1 (en) Method of resetting coupled modules and a system using the method
EP0533429B1 (en) Computer bus control system
KR930005843B1 (en) Method for controlling subprocessor in multiprocessor system
KR100785586B1 (en) Method and apparatus for efficiently broadcasting transactions between a first address repeater and a second address repeater
JPH03176754A (en) Multiprocessor system
EP0284094B1 (en) Tandem priority resolver
JP2705955B2 (en) Parallel information processing device
JPS62168257A (en) Multiprocessor system sharing memory

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 19940517

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LI LU MC NL PT

17Q First examination report despatched

Effective date: 19970115

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 19970527