EP0614136B1 - Shunt régulateur pour source d'alimentation - Google Patents

Shunt régulateur pour source d'alimentation Download PDF

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Publication number
EP0614136B1
EP0614136B1 EP93103448A EP93103448A EP0614136B1 EP 0614136 B1 EP0614136 B1 EP 0614136B1 EP 93103448 A EP93103448 A EP 93103448A EP 93103448 A EP93103448 A EP 93103448A EP 0614136 B1 EP0614136 B1 EP 0614136B1
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EP
European Patent Office
Prior art keywords
current
power supply
coupled
fet
branch
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EP93103448A
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German (de)
English (en)
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EP0614136A1 (fr
Inventor
Christophe Delepaut
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Alcatel Lucent SAS
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Alcatel CIT SA
Alcatel SA
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Priority to DE69325569T priority Critical patent/DE69325569T2/de
Priority to ES93103448T priority patent/ES2133336T3/es
Priority to EP93103448A priority patent/EP0614136B1/fr
Priority to CA002116890A priority patent/CA2116890A1/fr
Priority to JP03435394A priority patent/JP3502145B2/ja
Priority to US08/206,061 priority patent/US5444358A/en
Publication of EP0614136A1 publication Critical patent/EP0614136A1/fr
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Publication of EP0614136B1 publication Critical patent/EP0614136B1/fr
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/613—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in parallel with the load as final control devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
    • H03K17/0822—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/165—Modifications for eliminating interference voltages or currents in field-effect transistor switches by feedback from the output circuit to the control circuit

Definitions

  • the present invention relates to a power supply shunt regulator as described in the preamble of claim 1.
  • Such a power supply shunt regulator is already known in the art, e.g. from the article "Design and development of a sequential switching shunt regulator", by I.R. White, Proc. of the 3d ESTEC Spacecraft Power Conditioning Seminar, Noordwijk (NL), 21-23 September 1977, pp. 133-136.
  • This regulator is used to control the power supplied to the load by the power supply which consists of solar cells.
  • a problem with such a shunt regulator is that, when the shunt switch is turned on, the parasitic capacitor across the power supply discharges abruptly due to the short circuit which is so established. The current peak caused by this discharge may damage the shunt switch and thus reduces the system reliability. This is all the more worrying when the frequency with which the shunt switch is turned on and off is relatively high and when the regulator is used in spacecrafts which require very high reliability.
  • the known regulator therefore limits this discharge current via the current limitation means which includes in particular a capacitor C1 shown in Figure 7 of the referenced article.
  • This capacitor artificially increases the Miller capacitance of the shunt switch, formed by T2 and T3, and thereby slows down the response of the regulator so limiting the current through the switch to a value which is dependent on the parasitic capacitance across the power supply and the power supplied by it.
  • this known regulator Since the power supplied and the value of the parasitic capacitance are nonlinear and time- and temperature dependent, this known regulator has to limit the current to a value which is substantially lower than the maximum current dictated by a specific application by taking into account the above variations. In this way less current is available for the discharge of the parasitic capacitance leading to a slower discharge and consequently also to a larger power dissipation in the shunt switch. This larger dissipation diminishes the reliability of the regulator.
  • a shunt regulator of the above type but which limits the current to a value independent of the power supply characteristics and which dissipates less energy when the shunt switch is turned on is already known in the art, e.g. from the European Patent Application EP-A-O 493 185.
  • the shunt switch is a field effect transistor and wherein the current limitation means comprises a negative feedback loop which is coupled between a current sensing resistor forming part of said series connection and said control electrode to regulate said analog control signal in such a way that the voltage drop across said current sensing resistor is lower than a maximum voltage drop and wherein the inductive means are coupled to the source electrode of said field effect transistor.
  • the shunt switch is configured as a Field Effect Transistor FET having a relatively low saturation voltage.
  • An object of the present invention is to provide a shunt regulator of the above type but which has not the above drawback of giving rise to instability of the system.
  • a further disadvantage of the known regulator leading to an unnecessary increase of the power dissipation is that the current through the shunt switch displays a significant current ripple. Indeed, due to this current ripple less current is effectively available to discharge the parasitic capacitor across the power supply than the maximum current allowed to flow through the switch would permit. This means, as already mentioned, that it takes longer to discharge the parasitic capacitance and that more energy is dissipated in the shunt switch then strictly needed.
  • said current limitation means includes an active negative feedback current controller deriving from a regulating input signal constituted by said voltage drop a regulating output signal (RO) on which said analog control signal is based and that the transfer function from said regulating input signal to said regulating output signal of said negative feedback current controller is determined in such a way that said voltage drop strives substantially critically damped to said maximum voltage drop.
  • RO regulating output signal
  • this advantageous transfer function can be achieved in a simple way because the active negative feedback loop as described above is used and because of the stabilization achieved by way of the inductive means. Indeed, without the latter the operation of a controller with a same transfer function could not give rise to the desired response of the voltage drop.
  • said load and said current sensing resistor are connected to a ground terminal and that said current limitation means includes drive means for generating said analog control signal based on said regulating output signal, said drive means consisting of a drive branch including a series connection of amplifier means and short circuit means, being coupled between the floating terminals of said current sensing resistor and said load and generating said analog control signal as the voltage appearing on the junction point of said amplifier and short circuit means, said regulating output signal being the input signal to said amplifier means, and that said current controller further includes:
  • the short circuit means included in the drive means ensures that the shunt switch is completely closed in the absence of an input signal to the amplifier means and in so doing it is avoided that the shunt switch is damaged by excessive dissipation due to continuous linear behaviour.
  • this short circuit means is such that the regulator is more robust with regard to threshold voltage lowering of the FET due to ageing and radiation and with regard to failures in the active controller, which is the reason for it being made redundant by providing two parallel transistors for it.
  • the active controller designed in a very simple way by providing two branches, i.e. feedback and polarization branch, performing the basic feedback operation using little hardware whilst the above mentioned desired transfer function of the active controller is determined by way of a separate third branch, i.e. the dynamic compensation branch.
  • This branch in providing a specific way out for the net current flowing from the junction point of the current feed and drain means, can be easily designed to yield the desired transfer function since it will determine the voltage on the latter junction point, this voltage being the regulating output signal, and hence the input to the Darlington pair which is in its turn coupled as a unity gain amplifier due to the short circuit means operating as a current source at FET turn on.
  • the design of the active controller is very simple since it solely consists in determining a proportional part of the desired transfer function through the resistive means and a dynamic part through the capacitive means.
  • said capacitive means comprises 4 compensation capacitors coupled in two parallel branches each of which comprises the series connection of 2 of said compensation capacitors, said 4 compensation capacitors being equivalent to one capacitor having a capacitance value equal to the capacitance value of each of said compensation capacitors.
  • This characteristic allows to reduce dramatically the probability that one of two damaging failure modes of the compensation branch occurs.
  • the parallel redundancy avoids that the response of the current controller degenerates to a non-optimal response due to the fact that the operation of the compensation branch is completely lost.
  • the desired response of the voltage drop across the current sensing resistor can no longer be obtained resulting in a higher maximum current in the shunt switch due to current overshoot.
  • the latter problem is particularly critical in high reliability applications where a redundant shunt switch, with corresponding duplicated regulator, is introduced in series with the first mentioned shunt switch. In that case, when the first mentioned shunt switch fails in short circuit the power supply is not lost due to the fact that the redundant shunt switch can take over.
  • the above parallel redundancy of the compensation capacitors diminishes the probability that the regulator of the first mentioned shunt switch operates without adequate current limitation in such a way that both shunt switches are lost due to excessive current peaks.
  • the parallel redundancy makes the capacitive means compatible with the series redundancy of the shunt switches.
  • Still another feature of the present invention is that said current controller is controlled by a binary control signal in such a way that said current controller is enabled/disabled dependent upon the actual value of said binary control signal, said control signal consisting of an open circuit/short circuit condition being applied to a first terminal of a control resistor whose second terminal is connected to said feedback branch on a point between said floating terminal of said load and said current feed means, and that said power supply is one of a plurality of similar solar array sections, said one section being able to be short circuited dependent on said binary control signal in order for the supply and demand of current to be matched in a spacecraft.
  • the power supply unit PSU shown in Fig. 1 can for instance be used in a spacecraft which electrical circuits constitute an electrical load EL which is powered by solar array sections such as the section SA. Since both the power supplied by SA as the power required by EL are fluctuating in time, means have to be provided to match the supply to the demand.
  • SA electrical load
  • This selective short circuiting can be done by a power supply shunt regulator PSSR which is controlled via a control input CTRL to either turn on/off a shunt switch embodied by a Field Effect Transistor FET so either avoiding/allowing the power of SA to be delivered to EL.
  • CTRL The derivation of CTRL is known from the above articles and will therefore not be described here, in fact will it be assumed throughout the following that this derivation is performed by way of the S 3 R technique known from the last mentioned article.
  • one of the solar array sections will be in a switching mode wherein it is continuously turned on and off in order to supply exactly the required amount of energy to the load EL and hence that the power supply shunt regulator has to be carefully designed due to this possible high switching strain.
  • the solar array section SA can be modelled as a current source CS in parallel with a parasitic section capacitor PSC and is connected between a symbolically represented ground terminal and a power supply line PSL having an equivalent so called “harness inductance" L H .
  • This power supply line PSL is in its turn connected to a junction point JP to which the like named terminal of a power bus PB is coupled via diodes BD1 and BD2.
  • the power bus PB has an equivalent bus capacitance BC which stands in parallel to the electrical load EL and which is, as EL, connected between the terminal PB and the ground terminal.
  • BC the integrating nature of BC is such that with one solar array section in switching mode it can be ensured that the power supplied to EL matches the sum of the amounts of power supplied by a number of solar array sections even when this sum is not exactly equal to the required power.
  • the power supply shunt regulator PSSR is also connected between the junction point JP and the ground terminal and has the control input CTRL.
  • the power supply shunt regulator PSSR consists in more detail of a branch in parallel to the load EL and the solar array section SA and including between JP and the ground terminal the series connection of a shunt switch constituted by the above n-channel Field Effect Transistor FET, a degenerative inductor L D and a current sensing resistor CSR.
  • the shunt switch FET determines the impedance, short or open circuit, of the mentioned branch and is therefore controlled by an analog control signal ACTRL which is derived from the control signal CTRL by the circuits COMP, FCC and DM as described hereafter.
  • the latter three circuits are connected to the terminal PB and thus receive a stable supply voltage from the power bus.
  • CTRL is coupled to COMP via a hysteresis resistor RH.
  • a symbolically represented comparator circuit COMP compares the signal provided by RH in response to the control signal CTRL with a reference signal REF, corresponding to the solar array section SA, and so derives the binary control signal BCTRL applied on a like named input terminal of an active negative feedback current controller FCC.
  • the signal BCTRL has two states: a first one which is such that the current controller FCC sees on its input terminal BCTRL a short circuit and a second one which is such that FCC sees an open circuit.
  • the active negative feedback current controller FCC which is enabled/disabled by the binary output signal BCTRL of COMP further has a regulating input signal RI provided on a like named terminal and consituted by the voltage drop across the current sensing resistor CSR with respect to the ground terminal.
  • FCC when enabled, derives from RI a regulating output signal RO applied on a like named terminal connected to a drive means DM and constituted by the voltage on this terminal RO with respect to ground.
  • DM is connected to the ground terminal via the current sensing resistor CSR, i.e. to RI.
  • the drive means DM then finally derives the analog control signal ACTRL from the regulating output signal RO.
  • the above building blocks L D , CSR, FCC and DM form a current limitation means CLM constituting an active negative feedback loop and forming together with the comparator means COMP and with the shunt switch FET the power supply shunt regulator PSSR.
  • the operation of the power supply unit PSU will be further described in detail with reference to the following figures.
  • Fig. 2 shows an equivalent electrical schematic of the power supply unit PSU with the FET included in the regulator PSSR at turn on.
  • This schematic includes the series connection of the harness inductor L H , a simplified FET model consisting of a parallel connection of a voltage controlled current source G with controlling voltage ACTRL, and the parasitic transistor capacitor PTC, and the degenerative inductor L D .
  • the respective inductance, capacitance and gain values will hereafter be indicated with like named reference signs. It is to be noted that the other parasitic capacitors associated to the FET are neither shown in Fig. 2 nor considered in the following discussion since these capacitors were shown, both in simulation and in experiment, to have a negligible influence on the transfer function derived below.
  • H ( s ) G 1+ G L D s + PTC L H s 2
  • the negative feedback current controller FCC in combination with the degenerative inductor L D avoids these problems thanks to the fact that its transfer function can be chosen in such a way that it reliably determines a desired response at turn on for the current through the FET and that the maximum current to which the latter current will be limited only depends on the resistance value of CSR and on the transfer function of FCC.
  • This negative feedback controller FCC and other parts of the current limitation means CLM will hereafter be described in detail with reference to Fig. 3.
  • Fig. 3 In this figure are more particularly represented those parts of CLM which derive the analog control signal ACTRL from both the binary control signal BCTRL and the regulating input signal RI, i.e. the voltage drop over CSR. These parts are fed from the terminal PB, on which the stable bus voltage is provided, and either the ground terminal or the floating terminal RI of CSR as will be described in detail below.
  • the feedback current controller FCC consists of three branches of which a feedback branch R1, T1, T2 and R2 is connected to the ground terminal and of which a polarization branch R3, R4, T3, and R5 and a dynamic compensation branch R6, R7 and C1/4 are connected to the floating terminal RI of CRS.
  • the feedback branch comprises the series connection of resistor R1, pnp-transistor T1, npn-transistor T2 and resistor R2 and receives the binary control signal BCTRL via a control resistor RCTRL, included to limit the reverse bias over T1 when BCTRL is in its short circuit state, on the junction point of R1 and T1.
  • the polarization branch comprises the series connection of the resistors R3, R4 and the npn-transistor T3 and finally the resistor R5.
  • the base electrode of T1 is connected to the junction point of the resistors R3 and R4 whilst the base electrode of T2 is connected to both the base and the collector electrode of T3 as well as to the resistor R4.
  • the dynamic compensation branch comprises the series connection of the resistor R6, the resistive means R7 and the capacitive means C1-4 which is itself constituted by the parallel connection of two branches each including the series connection of two capacitors, C1/2 and C3/4, the capacitors C1-4 having equal capacitance values.
  • the junction point of the resistors R6 and R7 is connected to the junction point of the transistors T1 and T2 and on this junction point RO the like named regulating output signal, constituted by the voltage on RO with respect to the ground, of FCC is provided.
  • the drive means R8-11, C5, T4-8 and D1 connected to the floating terminal RI of CSR comprises amplifier means including a Darlington pair formed with npn input and output transistors, T4 and T5 respectively.
  • the base electrode of T4 is connected to the aforementioned terminal RO and its collector electrode is connected via resistor R8 to the power bus PB and via resistor R9 to the collector electrode of T5.
  • the emitter electrode of T5 is in its turn connected to a short circuit means consisting of the series connection of npn-transistors T6/7 coupled in parallel and of a resistor R11.
  • the emitter electrodes of T6/7 are connected to one end of resistor R11 whose other end is connected to the floating terminal RI of CRS.
  • the emitter electrode of T5 is further connected via resistor R10 to a terminal ACTRL on which the like named analog control signal is provided.
  • the drive means DM further includes a diode D1 connected between the base electrode of T4 and the collector electrode of T5 and a capacitor C5 coupled between the latter collector electrode and the collector electrode of pnp-transistor T8 whose base electrode is connected to the base electrode of T4 and whose emitter electrode is connected to the emitter electrode of T5.
  • the junction point of C5 and T8 is connected to the floating terminal of CRS and two Zener diodes D2/3 are coupled in parallel between the junction point of the inductor L D and the shunt switch FET and the emitter electrode T5.
  • the binary control signal BCTRL can be considered as an enable/disable signal for the current controller FCC. Indeed in its high impedance state FCC sees on its terminal BCTRL an open circuit and a circuit via T1 in such a way that the current controller will be enabled since it is not influenced by BCTRL. If the signal BCTRL is such that FCC experiences a short circuit on its terminal BCTRL all current drawn from PB via R1 will be dumped through this short circuit and consequently T1 will be turned off, the regulating output signal on RO will then be shorted to the ground via T2, R2 and the amplifier means T4/5 will also be in an open circuit configuration.
  • the analog control signal ACTRL will therefore be short circuited to the ground via the short circuit means T6/7, R11 in such a way that the FET is turned off. It can be clearly appreciated from the above that in the latter case the operation of FCC is disabled and that consequently the FET is closed.
  • the Darlington pair is coupled as a unity gain voltage amplifier from the regulating output signal RO to the voltage at the emitter electrode of T5 which is achieved by the inclusion of R11 in the short circuit means. Indeed from the moment current starts to flow through the branch R8/9, T5/7, R11, the short circuit means will operate as a current source for the whole duration in which the controller FCC is enabled. Therefore also it is clear that a negligible amount of current will flow from RO to the Darlington pair due to the infinite gain of the Darlington pair coupled in this way. The above has the advantage that the exact response of the Darligton pair need not be known.
  • the present regulator PSSR requires the inclusion of the compensation branch in order to optimize the transfer function of FCC from RI to RO in view of an optimal turn on behaviour, i.e. in such a way that the current through the FET increases in a critically damped way to the maximum current, i.e. with least delay and without overshoot.
  • This desired transfer function can then be achieved in a very simply way once the dynamic compensation branch is introduced. Indeed, this branch will almost completely determine the transfer function of FCC due to the fact that the amplifier means is a unity gain amplifier.
  • a desired transfer function can be achieved through inclusion in the compensation branch of resistive means R7 giving a proportional response and through inclusion of capacitive means C1-4 giving an integrating response.
  • the compensation capacitors C1-4 determine the dynamic behaviour of the current controller FCC and in combination with L D the dynamic behaviour of CLM.
  • the transfer function of the current controller FCC can, thanks to the stabilization performed by the inductor L D , be so chosen that the voltage drop RI rises to a maximum voltage drop in a critically damped way. It is to be noted that the latter response is in particular obtained with the parameters for the PSSR listed in table 1 below.
  • Zener diodes D2/3 are included to avoid damage to the FET resulting from gate-to-source voltages exceeding 10V and to avoid too negative gate-to source voltages when the FET is turned off. Indeed, such excessive negative voltages are equally damaging to the FET and are clearly avoided through the inclusion of D2/3.
  • any delay, either in turning on or off the FET results in some voltage ripple on the power bus PB which is a well known side-effect in the S 3 R technique.
  • this voltage ripple may become such that two solar array sections are put by their control signals in switching mode as described above. This is very undesirable and therefore these delays are diminished in the way described below.
  • Further requirements are that the switching does not cause too large current changes which might lead to electro-magnetic interference and that the turn off is complete, i.e. that the FET is not controlled via ACTRL to operate constantly in linear mode dissipating excessive amounts of energy. The latter would be in conflict with the series redundancy of a redundant shunt switch as already higher. Indeed through such a linear failure both shunt switches could be simultaneously damaged through excessive dissipation making the redundancy useless.
  • the analog control signal ACTRL on the gate electrode of the FET is rapidly and securely brought to the voltage on the ground terminal so that it is ensured that, when in steady state, the FET is totally off without unnecessary power dissipation.
  • This is achieved rapidly due to the fact that diode D1 avoids that a large saturation voltage is present over the transistors T4/5 of the Darlington pair and due to transistor T8 which is perfectly coupled to short terminal ACTRL to the ground since it contributes, thanks to its coupling, to the discharge of the parasitic capacitors of the FET.
  • This is achieved securely by the redundant short circuit means T6/7 which have an extremely low collector-emitter voltage drop of 0.1V when not conducting any current.

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Claims (9)

  1. Régulateur shunt d'alimentation (PSSR) comportant une branche (FET, LD, CSR) qui comporte la connexion en série d'au moins un commutateur de shunt (FET) et de moyens inductifs (LD) et qui est couplé en parallèle à la fois à une charge (EL) et à une alimentation (SA), ledit régulateur comportant des moyens de limitation de courant (CLM) destinés à générer un signal de contrôle analogique (ACTRL) appliqué à une électrode de contrôle dudit commutateur de shunt de façon à limiter la quantité de courant s'écoulant à travers ledit commutateur de shunt, qui est un transistor à effet de champ (FET), lesdits moyens de limitation de courant (CLM) comprenant une boucle de réinjection négative (FCC, DM, FET, LD, CSR) couplée entre une résistance de détection de courant (CSR) faisant partie de ladite connexion en série (FET, LD, CSR) et ladite électrode de contrôle pour réguler ledit signal de contrôle analogique (ACTRL) d'une façon telle que la chute de tension (RI) aux bornes de ladite résistance de détection de courant soit inférieure à une chute de tension maximale, lesdits moyens inductifs (LD) étant couplés à l'électrode de source dudit transistor à effet de champ, caractérisé en ce que l'inductance desdits moyens inductifs (LD) est telle que les pôles de la fonction suivante se trouve dans le demi-plan de gauche : H(s) = G1+G LD s+PTC LH s2 où LD est ladite inductance, G est le gain tension-courant dudit commutateur de shunt et PTC est la capacité parasite drain-source (PTC) dudit transistor à effet de champ (FET), LH a est l'inductance équivalente des lignes d'alimentation (PSL) interconnectant ladite alimentation (SA) à ladite branche (FET, LD, CSR) et s est la variable de Laplace.
  2. Régulateur shunt d'alimentation (PSSR) selon la revendication 1, caractérisé en ce que lesdits moyens de limitation de courant comportent un contrôleur de courant de réinjection négative active déterminant d'après un signal d'entrée de régulation constitué par ladite chute de tension (RI), un signal de sortie de régulation (RO), sur lequel est basé ledit signal de contrôle analogique (ACTRL) et que la fonction de transfert entre ledit signal d'entrée de régulation (RI) et ledit signal de sortie de régulation (RO) dudit contrôleur de courant de réinjection négative (FCC) est déterminé d'une façon telle que ladite chute de tension (RI) s'efforce de façon sensiblement critique d'être amortie à ladite chute de tension maximale.
  3. Régulateur shunt d'alimentation (PSSR) selon l'une quelconque des revendications précédentes, caractérisé en ce que ladite charge (EL) et ladite résistance de détection de courant (CSR) sont connectées à une borne de masse et que lesdits moyens de limitation de courant (CLM) comportent des moyens de commande (DM) pour générer ledit signal de contrôle analogique (ACTRL) sur la base dudit signal de sortie de régulation, lesdits moyens de commande étant constitués d'une branche de commande (R8/9, T4/5, T6/7, R11) comportant une connexion en série de moyens amplificateurs (R8/9, T4/5) et de moyens de court-circuit (R11, T6/7), couplés entre les bornes flottantes de ladite résistance de détection de courant (CSR) et ladite charge (EL) et générant ledit signal de contrôle analogique (ACTRL) comme étant la tension apparaissant au point de jonction dudit amplificateur et des moyens de court-circuit, ledit signal de sortie de régulation (RO) étant le signal d'entrée vers lesdits moyens amplificateurs.
  4. Régulateur shunt d'alimentation (PSSR) selon la revendication 3, caractérisé en ce que ledit contrôleur de courant (FCC) comporte en outre :
    une branche de réinjection (R1, T1, R2, T2) comportant la connexion en série de moyens d'alimentation de courant (T1) et de moyens de drain de courant (T2) et couplée en parallèle avec ladite charge (EL), ledit signal de sortie de régulation (RO) étant généré au point de jonction desdits moyens d'alimentation de courant et de drain de courant,
    une branche de polarisation (R3, R4, T3, R5) à partir de laquelle sont contrôlés, à la fois lesdits moyens d'alimentation de courant et de drain de courant, et qui est couplée en parallèle avec ladite branche de commande (R8/9, T4/5, T6/7, R11),
    et qu'une augmentation dudit signal d'entrée de régulation (RI) conduit à une augmentation/diminution du courant s'écoulant à travers lesdits moyens de drain/alimentation de courant.
  5. Régulateur shunt d'alimentation (PSSR) selon les revendications 2 et 4, caractérisé en ce que ledit contrôleur de courant (FCC) comporte également une branche de compensation dynamique (R6, R7, C1-4) couplée en parallèle avec ladite branche de commande (R8/9, T4/5, T6/7, R11) et comportant la connexion en série de moyens résistifs (R7) et de moyens capacitifs (C1-4) couplés audit point de jonction (RO) de ladite branche de réinjection et que lesdits moyens amplificateurs (R8/9, T4/5) comportent une paire Darlington (T4/5) avec des résistances de charge associées (R8/9), couplée sous la forme d'un amplificateur de tension de gain unitaire et que lesdits moyens de court-circuit (R11, T6/7) sont constitués de la connexion en série de deux transistors couplés en parallèle et d'une résistance de dégénérescence (R11).
  6. Régulateur shunt d'alimentation selon la revendication 5, caractérisé en ce que lesdits moyens capacitifs (C1-4) comprennent 4 condensateurs de compensation (C1-4) couplés dans deux branches parallèles, chacune d'entre elles comprenant la connexion en série de 2 desdits condensateurs de compensation, lesdits 4 condensateurs de compensation étant équivalents à un condensateur ayant une valeur de capacité égale à la valeur de capacité de chacun desdits condensateurs de compensation.
  7. Régulateur shunt d'alimentation selon la revendication 5, caractérisé en ce qu'une diode (D1) est connectée entre l'électrode de base du transistor d'entrée (T4) de ladite paire et l'électrode de collecteur du transistor de sortie (T5) de ladite paire et que d'autres moyens de court-circuit (T8) sont prévus et sont constitués d'un transistor (T8) dont l'électrode de base est connectée à l'électrode de base dudit transistor d'entrée et dont l'électrode d'émetteur est couplée à l'électrode d'émetteur dudit transistor de sortie et dont l'électrode de collecteur est connectée à ladite borne flottante de ladite résistance de détection de courant (CRS).
  8. Régulateur shunt d'alimentation (PSSR) selon l'une quelconque des revendications 3 à 7, caractérisé en ce que ledit contrôleur de courant (FCC) est contrôlé par un signal de contrôle binaire (BCTRL) d'une manière telle que ledit contrôleur de courant est activé/désactivé en fonction de la valeur réelle dudit signal de contrôle binaire (BCTRL), ledit signal de contrôle étant constitué d'une condition de circuit ouvert/court-circuit appliquée à une première borne (BCTRL) d'une résistance de contrôle (RCTRL) dont la deuxième borne est connectée à ladite branche de réinjection (R1, T1, T2, R2) en un point situé entre ladite borne flottante de ladite charge (EL) et lesdits moyens d'alimentation de courant (T1).
  9. Régulateur shunt d'alimentation (PSSR) selon la revendication 8, caractérisé en ce que ladite alimentation (SA) est une section parmi une pluralité de sections de panneaux solaires similaires, ladite section étant capable d'être court-circuitée en fonction dudit signal de contrôle binaire (BCTRL) pour que l'alimentation et la demande de courant correspondent dans un véhicule spatial.
EP93103448A 1993-03-04 1993-03-04 Shunt régulateur pour source d'alimentation Expired - Lifetime EP0614136B1 (fr)

Priority Applications (6)

Application Number Priority Date Filing Date Title
DE69325569T DE69325569T2 (de) 1993-03-04 1993-03-04 Shuntregler für eine Stromversorgung
ES93103448T ES2133336T3 (es) 1993-03-04 1993-03-04 Regulador de derivacion de fuente de alimentacion.
EP93103448A EP0614136B1 (fr) 1993-03-04 1993-03-04 Shunt régulateur pour source d'alimentation
CA002116890A CA2116890A1 (fr) 1993-03-04 1994-03-03 Regulateur d'alimentation a derivation
JP03435394A JP3502145B2 (ja) 1993-03-04 1994-03-04 電源シャントレギュレ−タ
US08/206,061 US5444358A (en) 1993-03-04 1994-03-04 Power supply shunt regulator with current limitation circuit therein

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP93103448A EP0614136B1 (fr) 1993-03-04 1993-03-04 Shunt régulateur pour source d'alimentation

Publications (2)

Publication Number Publication Date
EP0614136A1 EP0614136A1 (fr) 1994-09-07
EP0614136B1 true EP0614136B1 (fr) 1999-07-07

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Application Number Title Priority Date Filing Date
EP93103448A Expired - Lifetime EP0614136B1 (fr) 1993-03-04 1993-03-04 Shunt régulateur pour source d'alimentation

Country Status (6)

Country Link
US (1) US5444358A (fr)
EP (1) EP0614136B1 (fr)
JP (1) JP3502145B2 (fr)
CA (1) CA2116890A1 (fr)
DE (1) DE69325569T2 (fr)
ES (1) ES2133336T3 (fr)

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US6347028B1 (en) 1999-06-21 2002-02-12 Lutron Electronics Co., Inc. Load control system having an overload protection circuit
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US6463672B1 (en) * 2000-07-03 2002-10-15 The United States Of America As Represented By The Secretary Of The Air Force Mitigation of spacecraft charging by means of ionized water vapor
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DE60127969T2 (de) 2001-11-19 2008-01-17 Dialog Semiconductor Gmbh Störunterdrückungsoptimierung der Stromversorgung während des Prüfens
US6690144B1 (en) * 2002-08-09 2004-02-10 Motorola, Inc. Open loop inductor current control system and method
EP1486845B1 (fr) * 2003-06-11 2006-05-31 Alcatel Régulateur à découpage en dérivation et dispositif d'alimentation l'utilisant en particulier pour des applications spatiales
US7339356B1 (en) * 2006-06-30 2008-03-04 Texas Instruments Incorporated Apparatus and method for controlling a power converter device
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JP5513778B2 (ja) * 2008-08-18 2014-06-04 パナソニック株式会社 スイッチング電源回路
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Also Published As

Publication number Publication date
EP0614136A1 (fr) 1994-09-07
JPH06348351A (ja) 1994-12-22
CA2116890A1 (fr) 1994-09-05
DE69325569D1 (de) 1999-08-12
US5444358A (en) 1995-08-22
DE69325569T2 (de) 1999-12-16
ES2133336T3 (es) 1999-09-16
JP3502145B2 (ja) 2004-03-02

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