EP0609097A2 - Kollektorstruktur eines Transistors zur verbesserten Anpassung und drossellosen Stromversorgungsverbindung - Google Patents
Kollektorstruktur eines Transistors zur verbesserten Anpassung und drossellosen Stromversorgungsverbindung Download PDFInfo
- Publication number
- EP0609097A2 EP0609097A2 EP94300653A EP94300653A EP0609097A2 EP 0609097 A2 EP0609097 A2 EP 0609097A2 EP 94300653 A EP94300653 A EP 94300653A EP 94300653 A EP94300653 A EP 94300653A EP 0609097 A2 EP0609097 A2 EP 0609097A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- collector
- external
- transistor
- matching circuitry
- output matching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
- H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
- H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
Definitions
- the present invention relates generally to transistors, and more specifically to a transistor collector structure for improved matching and power supply connection.
- the power supply has been applied to a transistor collector by a variety of means, depending on the particular circuit application and frequency of operation desired.
- Common means for supplying power to the transistor collector have included an RF choke, a section of transmission line, and an inductance of a resonance circuit.
- a transmission line or RF choke In the case where a transmission line or RF choke is used, their parameters must be chosen carefully, usually resulting in compromise. For in-band frequencies, the transmission line or RF choke should not load the collector or throw the transistor into oscillations. For out-of-band frequencies, the transistor must remain stable. In broadband applications, these requirements become even more critical and difficult to achieve. The use of an RF choke can adversely affect achievement of these design goals. For instance, at low frequencies where power gain is high, the inductance represented by the RF choke may contribute to circuit instability.
- a fixed shunt inductance typically internal to the transistor, is commonly used in transistor power designs as part of the transistor output matching circuit. It provides the benefit of tuning out the effective output capacitance of the transistor, thereby decreasing the transformation ratio required of matching circuitry and increasing transistor efficiency.
- the predetermined shunt inductance provides the designer very little flexibility.
- an additional, direct connection is made from the internal collector to the external collector of the transistor by a fixed shunt inductance.
- the external power supply V S is applied to the transistor collector through an adjustable external shunt element.
- the adjustable external shunt element allows the user to fine-tune the impedance matching circuit such that the transformation ratio of the output matching circuitry is minimized.
- Figure 1 shows a bipolar npn power transistor with output circuit according to the prior art.
- the common emitter transistor shown typically has a die transistor which rests on a highly heat conductive insulator, such as Beryllium Oxide, separating the transistor collector from the heat sink, the case of the device. Because the bottom of the die is a collector, the top of the BeO is also a collector, here noted as internal collector C. External collector C' represents the collector external to the transistor, commonly, the collector lead, outside the packaged transistor.
- a highly heat conductive insulator such as Beryllium Oxide
- Internal collector C is connected to external collector C' by collector bonding wire and transmission line inductance L C . Also, internal collector C is connected through shunt inductance L SHUNT and bypass capacitor CAP1 to ground, inside the transistor package. The emitter of transistor T is wire bonded to ground potential. External collector C' is connected through MATCH to R L load which is typically 50 ohms; MATCH circuitry provides impedance adjustment external to transistor T. L C , MATCH, and L SHUNT , together, form the matching network required to address the impedance mismatch between the required internal transistor load and R L , the external load. Power supply, V S , is applied to the transistor collector through RF choke, L CHOKE , and is bypassed by CAP2.
- L CHOKE represents the inductance of the RF choke or transmissions line by which power supply V S is applied to the collector of the transistor.
- the RF choke represents an ideal choke.
- the presence of even an ideal RF choke may affect transistor stability, especially at low frequencies where bipolar transistor gain is high.
- RF choke inductance may form resonant circuits with adjacent circuit capacitors at various frequencies.
- FIG. 2 is a transistor circuit schematic according to the present invention.
- the schematic is similar to the schematic shown in Figure 1, except that L CHOKE is absent and there is a second separate external collector, C".
- Internal collector C is seated on an insulator such as Beryllium Oxide (BeO) and is connected to external collector C" by L SHUNT1 .
- Both L C and L SHUNT1 are internal to the transistor as indicated by the dashed lines shown in Figure 2 .
- Power supply V S is applied through externally adjustable shunt element L SHUNT2 .
- external collector C and internal shunt element LS HUNT1 .
- Capacitor CAP2 is a bypass capacitor.
- L C , L SHUNT1 , L SHUNT2 , and MATCH make up the matching circuit which is responsible for transforming the impedance of external load R L so that at internal collector C, the transistor sees the proper impedance necessary to develop required power at certain frequencies and efficiencies.
- the invention shown in Figure 2 provides an additional, direct connection through L SHUNT1 from external collector C" to internal collector C. This connection allows for elimination of the RF choke of Figure 1 if shunt inductance is used as a first matching element.
- L CHOKE might be a cause of circuit instabiliity and/or effect impedance matching capabilities, so the removal of L CHOKE is a benefit.
- L C , L SHUNT1 + L SHUNT2 and MATCH together form the impedance matching circuitry. Since L SHUNT2 is adjustable, it may be used to fine-tune the impedance matching circuit.
- the transistor shown in Figure 2 is for a transistor die or a group of dice with a relatively short collector area.
- the use of two or more shunts is a better choice and assures more equal participation of all dice in power generation.
- An implementation of multiple adjustable shunts is more practical for a hybrid transistor than for a packaged transistor.
- FIG. 3 shows a common-emitter, four die transistor, with two adjustable shunts.
- the internal collector C which rests on top of an insulator such as Beryllium Oxide (BeO), is connected to external collector C' by bonding wires and transmission line inductance L C .
- internal collector C is connected to external collectors C1' and C2' through the combination of bondwires and transmission line inductances L SHUNT1 and L SHUNT2 , respectively.
- CAP1 serves as a bypassing capacitor; CAP2 is a decoupling capacitor.
- L' SHUNT1 and L' SHUNT2 provide adjustable shunt matching capability. Together, L C , L SHUNT1 , L SHUNT2 , L' SHUNT1 , L' SHUNT2 , and MATCH make up the transistor output matching circuitry.
- the alternate preferred embodiment of the invention shown in Figure 3 provides additional, direct connections from the external collector to the internal collector of a transistor.
- Such direct connections allow the RF choke of the prior art, with its inherent difficulties, to be eliminated.
- the L CHOKE of Figure 1 is often the cause of circuit instability and/or effect impedance matching problems. Without this RF choke inductance, transistor stability, especially at low frequencies where gain is high, may be improved.
- the described invention enables greater flexibility in matching the internal load of a transistor with the external load R L through externally adjustable shunt elements, such as L' SHUNT1 and L' SHUNT2 shown in Figure 3 .
- L C , L SHUNT1 , L' SHUNT1 , L SHUNT2 , L' SHUNT2 , and MATCH comprise the output matching circuitry for the transistor and transforms the impedance of external load R L so that the transistor sees the proper impedance to develop required power at required frequencies and efficiencies.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
- Microwave Amplifiers (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11386 | 1993-01-29 | ||
| US08/011,386 US5424676A (en) | 1993-01-29 | 1993-01-29 | Transistor collector structure for improved matching and chokeless power supply connection |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| EP0609097A2 true EP0609097A2 (de) | 1994-08-03 |
| EP0609097A3 EP0609097A3 (de) | 1995-07-26 |
| EP0609097B1 EP0609097B1 (de) | 1999-05-06 |
Family
ID=21750156
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP94300653A Expired - Lifetime EP0609097B1 (de) | 1993-01-29 | 1994-01-28 | Kollektorstruktur eines Transistors zur verbesserten Anpassung und drossellosen Stromversorgungsverbindung |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US5424676A (de) |
| EP (1) | EP0609097B1 (de) |
| DE (1) | DE69418224T2 (de) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9450283B2 (en) | 2004-12-21 | 2016-09-20 | Ampleon Netherlands B.V. | Power device and a method for controlling a power device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009146439A1 (en) * | 2008-05-30 | 2009-12-03 | Colorado State University Research Foundation | System, method and apparatus for generating plasma |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3566212A (en) * | 1969-02-24 | 1971-02-23 | Trw Semiconductors Inc | High temperature semiconductor package |
| FR2279255A1 (fr) * | 1973-03-02 | 1976-02-13 | Radiotechnique Compelec | Amplificateur fonctionnant dans la gamme des hyperfrequences |
| US3869677A (en) * | 1973-10-18 | 1975-03-04 | Rca Corp | Microwave transistor carrier for common base class a operation |
| US3869678A (en) * | 1973-12-18 | 1975-03-04 | Rca Corp | Multiple transistor microwave amplifier |
| US4119997A (en) * | 1974-08-13 | 1978-10-10 | Honeywell Inc. | DOT-AND logic gate device including multiemitter transistor |
| US4376287A (en) * | 1980-10-29 | 1983-03-08 | Rca Corporation | Microwave power circuit with an active device mounted on a heat dissipating substrate |
| US4525638A (en) * | 1984-01-16 | 1985-06-25 | Motorola, Inc. | Zener referenced threshold detector with hysteresis |
| IT1188335B (it) * | 1986-02-06 | 1988-01-07 | Sgs Microelettronica Spa | Dispositivo di controllo in retroazione per lo spegnimento di un transistore |
| US4849656A (en) * | 1987-06-11 | 1989-07-18 | Unitrode Corp. | Power-on detection circuit |
| JPH02130008A (ja) * | 1988-11-09 | 1990-05-18 | Toshiba Corp | 高周波電力増幅回路 |
| US5164683A (en) * | 1991-10-21 | 1992-11-17 | Motorola, Inc. | RF amplifier assembly |
-
1993
- 1993-01-29 US US08/011,386 patent/US5424676A/en not_active Expired - Lifetime
-
1994
- 1994-01-28 DE DE69418224T patent/DE69418224T2/de not_active Expired - Fee Related
- 1994-01-28 EP EP94300653A patent/EP0609097B1/de not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9450283B2 (en) | 2004-12-21 | 2016-09-20 | Ampleon Netherlands B.V. | Power device and a method for controlling a power device |
Also Published As
| Publication number | Publication date |
|---|---|
| DE69418224D1 (de) | 1999-06-10 |
| DE69418224T2 (de) | 1999-11-25 |
| US5424676A (en) | 1995-06-13 |
| EP0609097B1 (de) | 1999-05-06 |
| EP0609097A3 (de) | 1995-07-26 |
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