EP0571848B1 - Local paging receiver - Google Patents

Abstract

This receiver, commonly called "pager", is intended to receive radio broadcast message signals, comprising call signalling information and the message information. It comprises a receiver (3) intended for receiving and demodulating the coded message signals, a memory (5) for holding the said message information, a decoder (4) of the coded message signals for selectively supplying the message information to the memory (5) and means of function control (8) capable of supplying control signals to the memory and of receiving therefrom the message information which is held there. The memory (5) comprises internal processing means for controlling the reception of the message information originating from the said decoder (4). Hence, selected message information supplied by the decoder (4) can be held in the memory without it being necessary to make use of the command from a microcomputer or from a microprocessor external to this memory, which thus becomes, to some extent, "intelligent". Application especially to pagers built into a wristwatch.

Description

The present invention relates to call systems local and, more particularly, the memorization and manipulation of message information received by a local pager. In the rest of this description, we will designate by the word "pager" such local pagers because this term is now very widely accepted and used in French-speaking countries, both by specialists and by the general public who is the user.

The present invention can be used in portable pagers capable of receiving signals from high frequency message, the invention being described below in relation to this example application to which however, it is not limited.

Telecommunication systems in general, and local calling systems in particular, using broadcast message signals are currently widely used to ensure the appeal of pagers in a purpose of selectively sending them information to from a central station. This information is transmitted using coding schemes and formats specific messages, such as those known as POCSAG or GOLAY. Regarding the POGSAG scheme, we may refer in particular to CCIR recommendation 584-1, Dubrovnik, 1986.

The predominant coding schemes of transmission used for calling pagers have evolved from simple systems based on sequential acoustic signals to formats based on numerous code words bits, and the functions offered to the user have changed concomitantly with a single signal acoustic warning at a warning signal multifunctional complex involving reading on a display of numeric or alphanumeric data (see for example EP-A-232123).

To realize these multifunctional possibilities, local calling systems and pager receivers present include microprocessors or even microcomputers allowing them to react to information containing a wide variety of coded message signals broadcast. For this purpose, the already known pagers are capable of receiving these signals, demodulating them, extract the dedicated call signaling information and the actual message information, to memorize this information and finally to display certain elements chosen from the message transmitted.

The prior art pagers allow also the user to have possibilities special functions such as recall subsequent messages already received and display of the number received messages or current time.

The microcomputers used in known pagers are designed to control the operation of the receiver so that it can receive the message signals broadcast, and to perform decoding functions coded message signals, signal storage given messages, display control and manipulation of stored message signals, so that the various functional possibilities to order can be implemented.

One of the important requirements for a pager consists in that it must process the information received in real time, otherwise there is a risk of information loss, for example due to the fact that the decoding speed is too weak compared to that at which information is received. Therefore, operations carried out by the microcomputer relating to the reception, decoding, storage and manipulation of the encoded message information received must be fast enough for the results to be achieved useful for controlling the device without there being risk of information loss. We must therefore use particularly efficient microcomputers operating at high speed.

The clock frequency required to reach high real-time operating speeds can be 500 kHz, for example. These high clock frequencies increase supply voltage and energy consumed from the pager, while making it more expensive. Gold, the battery needed to power the microcomputers extensively determines the cost, dimensions and weight of pagers.

In addition, such high clock frequencies and the signals they induce in the pager's circuits at harmonic frequencies of the clock frequency, seriously disrupt the quality of treatment at which one should expect in a good pager. By elsewhere, high energy consumption and limits physical of these microcomputers also train a limitation of the functions that can be implemented and offered by existing pagers.

It is also common to repeat two or three times the broadcast of message signals to ensure that that of the pagers for which these signals are intended receives correctly. Known pagers thus include the memory space whose dimensions must be compatible with memorization not only of original message signals, but also their repetitions. The additional memory capacity that require these repetitions further increases the energy consumption and the cost of known pagers.

The object of the invention is to provide a pager which mitigates or even eliminates the disadvantages of pagers prior art.

The subject of the invention is therefore a pager intended for receive broadcast message signals, including call signaling information and message information, said message information comprising one or more messages, said pager comprising a receiver for receiving and demodulating coded message signals, a memory device, to store said message information, a decoder for decoding said coded message signals and for selectively providing said audit message information memory device, function control means capable of providing audit control signals memory device and receive information from it message stored therein, said pager being characterized in that said memory device comprises means processing interns to control receipt of message information from said decoder.

So selected message information provided by the decoder can be memorized by the memory device without the need to have the command of a microcomputer or a external microprocessor compared to this device memory, the latter thus becoming, in a way, "clever".

As a result, the message information selected can be stored directly and in time real in the "smart" memory device which allows the microcomputer or the external microprocessor with respect to the means of memorization, to accomplish other pager functions, without the frequencies clock speed or processing speed is as high than in known pagers.

According to another characteristic of the invention, the pager can also be adapted to ensure the manipulation of the message information stored in the memory device, so that deleting, copy and offset of the information thus memorized, can be performed inside the device memory, thereby removing the constraints imposed by these operations to the function control means, otherwise said to the pager's microcomputer.

According to yet another characteristic of invention, the pager can also be made capable of compare the message information received by the device memory with previously stored information. In this way, it suffices to memorize only message information that differs from information from previously stored message, which reduces capacity memorization required.

• la figure 1 est un schéma simplifié d'un mode de réalisation d'un pager suivant l'invention;
• les figures 2A et 2B montrent un diagramme représentant le schéma de codage POGSAG pouvant être utilisé pour la transmission de l'information de message destinée au pager de la figure 1;
• la figure 3 est un schéma plus détaillé du pager suivant l'invention;
• la figure 4 est un schéma simplifié d'un dispositif de mémoire utilisé dans le pager de la figure 1; et
• la figure 5 représente schématiquement une mémoire vive utilisée dans le dispositif de mémoire de la figure 4.

Other characteristics and advantages of the invention will become apparent during the description which follows, given solely by way of example and made with reference to the appended drawings in which:

• Figure 1 is a simplified diagram of an embodiment of a pager according to the invention;
• FIGS. 2A and 2B show a diagram representing the POGSAG coding scheme that can be used for the transmission of the message information intended for the pager of FIG. 1;
• Figure 3 is a more detailed diagram of the pager according to the invention;
• Figure 4 is a simplified diagram of a memory device used in the pager of Figure 1; and
• FIG. 5 schematically represents a random access memory used in the memory device of FIG. 4.

Referring now to Figure 1 of the drawings appended, a simplified diagram of a pager 1 is shown constructed, by way of example, according to the present invention. This pager 1 comprises an antenna 2 to which is connected a receiver 3 intended to receive the message signals coded broadcast by one central station or another source from which we wish to call pager user 1. Coded message signals disseminated may include, on the one hand, information selective call signaling to identify a pager particular among several or a large number of pagers in accordance with Figure 1 and, on the other hand, information specific message, signals can be coded in POGSAG format or any other coding format appropriate. The coded message signals transmitted received on antenna 2 are demodulated by receiver 3 and a packet of serial binary data representing these signals of coded message is supplied to an output 3a of the receiver 3.

Pager 1 also includes a connected decoder 4 at the output 3a of the receiver 3 by its input 4a. The decoder 4 comprises a memory area 4d intended for the storing predetermined address information at which will respond to pager 1 considered. The decoder 4 is suitable for making a comparison between the signals of coded messages received at entry 4a and information predetermined address stored in the memory area 4d. If the selective call signaling information corresponds to one of the stored addresses, the decoder provides the actual message information associated coded message signals, at output 4c of the decoder.

Pager 1 also includes a device for smart memory 5 connected to the decoder output 4c 4 by its input 5a. This device 5 includes a unit 6 data processing and a memory area 7 and it is suitable for receiving coded message signals on its input 5a and to memorize these message signals in the memory area 7. The data processing unit 6 is suitable for controlling the manner in which these message signals are stored in the memory area 7 and extracted therefrom; she can also accomplish manipulations on message signals, addresses, pointers and other internal variables. The detailed operation of the memory device intelligent 5 will be described later.

Pager 1 also includes a microcomputer 8 connected to output 5c of smart memory 5 by its entry 8a. The microcomputer 8 comprises, in a way known per se, a display interface 9, a microprocessor 10, a memory 11 with random access (RAM) and a read only memory (ROM) area 12. The interface display is designed to display information from message chosen by ordering a display 13 by through an input 13a and it includes a serial driver and serial drivers multiplexed for a crystal display cell liquids. This is adapted to display message information stored in the memory area 7 of smart memory 5 and it can also be suitable for displaying the time or other information.

The ROM zone 12 contains, by construction, instructions for controlling the operation of the microprocessor 10, for example a program for the display of signs corresponding to the information of message stored in memory area 7, for control the microcomputer input / output functions 8, to provide control signals for smart memory 5 and decoder 4, and to control the microcomputer time base 8. The RAM area 11 is used for temporary storage data in the microcomputer 8 and ensures, among other functions, a data buffer for message information provided by memory smart 5 and to be displayed.

Pager 1 also includes a circuit 14 of inputs command to apply data via output 14a at an input 8b of the microcomputer 8, this data representing input information provided by the user. User inputs 14b, c, d and e are connected to the control input circuit 14, these inputs can be in the form of push buttons, rotary knobs or other command allowing the user to order certain pager functions 1. The circuit 14 of control inputs can also be adapted to order other devices associated with pager 1. For example, a room clock can be combined with pager 1 and inputs 14b, c, d and e can be used to provide certain commands for such associated devices. In addition, the control input circuit 14 can directly control certain room functions timepieces associated with pager 1, such as that to supply the current to energize the motor 15 of a electronic watch movement. It should be noted that the pager combined with a timepiece can be present in the form of a wristwatch.

A portable power supply 16 such as a battery is also provided in pager 1 to provide by via output 16a, energy at the input 3b of receiver 3, at input 4b of decoder 4, at input 5b from smart memory 5 and at input 8c from the microcomputer 8. Another portable power supply 17 provided an outlet 17a is provided to supply energy to the control input circuit 14 through input 14f. The arrangement just described provides energy from separate sources respectively at pager and its associated devices, such as a coin of clockwork, so that if, for example, the stack of the pager is running out, the timepiece can continue to operate. However, we understand that the pager and its associated devices can just as well be powered by a single source of energy.

An example of message information and schema pager coding used to broadcast signals from messages such as those used by pager 1, are shown in Figures 2A and 2B. The POGSAG system, well known to specialists in this technique, uses a digital coding format (Figure 2A) composed of groups of code words 20, each composed of a synchronization word 21 and a group 22 of eight frames of two code words each, these groups of code words being transmitted in serial format at regular intervals. Each group 22 of eight frames is transmitted in succession of a synchronization word 21, the eight distinct frames which may contain either address information or message information. For the needs of the explanation, Figure 2B shows that each frame has an address code word, 23.1 to 23.8 respectively, and a message code word, 24.1 to 24.8 respectively.

So, in the example shown in Figure 2B, each pager of a group composed of pagers conforming to the one represented in figure 1, must operate on one of the eight address code words so that each of these words represent signaling information to using which each pager in the group is respectively identified.

The invention will be better understood with reference to the Figure 3 which shows a more detailed diagram of a mode of preferred embodiment of pager 1 according to the invention. As already described above, pager 1 essentially comprises an antenna (not shown in Figure 3), the receiver 3, decoder 4, smart memory 5 and the microcomputer 8. The circuit 14 of control inputs for controlling an associated timepiece 15 the pager is also shown in Figure 3.

The receiver 3 is connected by its terminal 3.1 to a 16.1 positive power supply conductor in portable energy 16 (not shown in FIG. 3), its terminal 3.2 being connected to a supply conductor negative 16.2 of the power supply 16. As is known in itself broadcast coded message signals are received and demodulated by receiver 3 and the antenna which one is connected, so that packets binary data such as those shown on the Figure 2A, are generated at the output 3.3 of the receiver 3 and transmitted to the input 4.1 of the decoder 4. The receiver 3 has in its internal circuit a mounting (not shown in the figures and known per se) of monitoring the voltage of the power source 16, this assembly providing an indication signal of exhaustion of this source on the output 3.4 of the receiver 3. The output 3.4 transmits, if necessary, the indication signal exhaustion at the other circuits of pager 1, so that a user-readable display can be assured on display 13.

Decoder 4 is connected to the conductor positive supply 16.1 via its terminal 4.4 and at negative supply conductor 16.2 via its terminal 4.5. A 4d voltage stabilizing capacitor is connected between terminals 4.4 and 4.5. The decoder can be of the PCA 5001 type manufactured by Philips and its purpose is task of separating call signaling information selective message information proper in coded message signals, and compare information signage with address information preset stored in the decoder and specific to the pager considered.

If the selective call signaling information corresponds to one of the addresses stored, any code word message following the address code considered until following address codeword is transmitted as serial data, from output 4.6 to input 5.1 of the smart memory 5

The output 4.7 of decoder 4 provides a signal data transfer to allow reading by the smart memory 5 of the data on the output 4.6, this signal can take a high level or a low level at entry 5.2 of memory 5. Information message provided at exit 4.6 is introduced in the memory area 7 of smart memory 5, when complete data byte has been transferred from the receiver 3 at decoder 4.

A resonator circuit 25 is connected to the decoder 4 via entries 4.8 and 4.9 of the latter. It essentially includes a 25a quartz resonator connected in parallel to a damping resistor 25b and entries 4.8 and 4.9. The power conductor positive 16.1 is connected to one of the terminals of the 25a quartz resonator via a resonance capacitor 25c. The resonator circuit 25 cooperates with the internal circuit of the decoder 4 to form an oscillator circuit that provides a waveform 32 kHz periodic, for example at decoder 4 for determine the transmission rate of the message from receiver 3 to decoder 4. Of course, other clock frequencies can be used in depending on the transmission rate of the signals message. The resonator circuit 25 is also used to supply a clock signal to the microcomputer 8 and to smart memory 5. This clock signal is supplied to microcomputer 8 via output 4.10 of decoder 4. The values of resistance 25b and of capacitor 25c can be 4.7 MΩ and 10 pF.

The decoder 4 includes a reprogrammable memory electrically erasable type EEPROM (not shown) in which the system parameters of the decoder 4. Control signals can be sent from microcomputer 8 to inputs 4.11, 4.12 and 4.13 to control the functions of the decoder 4. One of the functions of decoder 4 which can be controlled, is the bit transmission rate between decoder 4 and the smart memory 5, this rate can also be high than 5000 bits / sec. In this case, information from message is memorized by the circular buffer located in smart memory 5 without suffering any other processing (such as comparing the last two messages that have just been memorized).

Smart memory 5 input 5.3 is connected to the positive supply conductor 16.1, while input 5.13 is connected to the driver negative supply 16.2. The time base for the smart memory 5 is determined by the signal clock provided by output 8.8 of microcomputer 8 to entry 5.4.

The intelligent memory 5 has four terminals 5.5, 5.6, 5.7 and 5.8 connected respectively to the terminals 8.1, 8.2, 8.3 and 8.4 of the microcomputer 8, which ensures a simple parallel connection with this last allowing the sending of control signals from the microcomputer 8 to smart memory 5 and sending back message information stored in memory area 7 from smart memory 5 to the microcomputer 8 so that this message information can be displayed. Depending on the nature of the signal command sent, terminals 5.5 to 5.8 can also control smart memory 5 to provide microcomputer status information 8 relating to the receipt of message information by memory 5. Other control signals can control this to manipulate message information there is memorized, as it will appear later. A data transfer input 5.11 from memory 5 is also provided for the simultaneous transfer of data to terminals 5.5 to 5.8.

An entry 5.9 determines whether entries 5.5 to 5.8 carry data or enter signals control in smart memory 5. When a signal high level is present at input 5.9, the signals on entries 5.5 to 5.8 are interpreted as control signals from the microcomputer 8, while if a low level signal is present, the signals are interpreted as data.

A 5.10 terminal of smart memory 5 allows to indicate to the microcomputer 8 that it is ready to use it receive control signals. A level signal logic high on terminal 5.10 is interpreted by the microcomputer 8 as indicating that memory 5 is ready for a new communication with the microcomputer 8, while a low level logic signal is interpreted to mean that memory 5 is still in the process of performing a manipulation on data or other operation, either to transfer data to the microcomputer 8.

An output terminal 5.12 of memory 5 is used to provide an interrupt signal to the microcomputer 8 to indicate its functional state in response to message information received or to signals from ordered. A high logic level signal is sent to the microcomputer 8, if for example information from fresh or repeated message is received, or if a function unknown, prohibited or impracticable is requested by the microcomputer. This interrupt signal can thus be used to indicate to the microcomputer 8 that a new operation is required, such as for example, the announcement of the arrival of fresh message information or sending a new command to the smart memory 5. A low level signal indicates that no action news is not requested by the microcomputer 8.

This microcomputer 8 can be of any known type properly programmed. It is connected to the conductor positive supply 16.1 through its input 8.5 and at negative supply conductor through its input 8.6. A input 8.7 receives the clock pulse train from the output 4.10 from decoder 4. An output terminal 8.8 provides a clock signal at input 5.4 of the memory smart 5.

The microcomputer 8 also includes the terminals 8.9 and 8.11 to provide control signals and data transfer described above respectively to the entries 5.9 and 5.11 of the memory smart 5, while input terminals 8.10 and 8.12 are provided to receive respectively, acceptance and abort signals described above smart memory 5.

A liquid crystal display 13 is connected to the microcomputer 8. It includes numbered segments of 00 to 47 which are connected to the driver display (not shown in Figure 3) of the microcomputer 8 by a bus 13a so that each segment can be individually ordered and desired message information can be displayed by posting 13. Specialists will understand that various voltage values are required for the driver to control the various segments of display 13. The input terminals 8.13 to 8.16 are connected to the positive supply conductor 16.1 by through capacitors 8d to 8g to provide these various tensions. Capacitors 8d to 8g can have values of 220, 100, 100 and 100 nF respectively. The microcomputer 8 also includes output terminals 8.17, 8.18 and 8.19 to provide, in a manner known per se, control and time base signals on the display 13 from the attack circuit.

Input terminals 8.20, 8.21 and 8.22 are provided to stabilize and smooth internal tension levels to the microcomputer 8. One of the terminals of a capacitor 8h is connected to input 8.20, while one of the terminals of another capacitor 8i is connected to the input 8.21. The other terminals of capacitors 8h and 8i are connected together at terminal 8.22.

The microcomputer 8 is also provided with inputs 8.23 to 8.26 of user control, each of which is connected to the positive supply conductor 16.1 via switches 8j, 8k, 8l and 8m can be operated by the user. When this is the case, a high logic level signal is applied to user control inputs, for example when he wishes to turn on or off the pager 1, make it silent, protect the message displayed by display 13 or delete a displayed message, such as it will be explained later. It will be understood that various other user-controlled functions can be this way and that a separate entrance is not not necessary for each of these functions as well planned; for example, one or more switches or pushbuttons can be activated in a sequence particular to indicate to the microcomputer 8 that a certain function must be performed.

Circuit 14 for control and room inputs timepiece is connected to driver 17.1 portable power supply positive 17 (no represented in figure 3) by terminal 14.1 and at negative power supply 17.2 17 via terminal 14.2.

The circuit 14 also includes inputs 14.3, 14.4 and 14.5 which are used to constitute entries additional users to allow the performance by pager 1 of certain functions to user control, and also control of the operation of timepiece 14 which is controlled by circuit 14. A particular sequence of signals applied to inputs 14.3, 14.4 and 14.5, or signals initially sent to other inputs, may be used to determine if entries 14.3, 14.4 and 14.5 control the operation of the pager or the coin timepieces 15. The inputs 14.3, 14.4 and 14.5 are respectively connected to one of the terminals of the switches 14b, 14c and 14d, their other terminals being connected together at input 14.1. Switches can be made in any form usable by the user. Another 14th switch is connected between the positive supply conductor 17.1 and a input 8.27 of the microcomputer 8 in order to indicate to it whether it is the pager or the timepiece that is ordered.

Circuit 14 also has two outputs 14.6 and 14.8, connected respectively to one of the terminals of two coils 15a and 15b of timepiece 15. The others terminals of these coils are connected to a connection return commune 14.7. Specialists will understand that in the example chosen here, the coils 15a and 15b belong to a one-piece bidirectional motor analog quartz watchmaking, otherwise well known, but that a timepiece of any other type can be provided, including a timepiece digital, in which case, of course, a watch engine is not necessary. Various other entries can be provided for circuit 14 to order any other function of the timepiece.

Two other outputs 14.9 and 14.10 of circuit 14 are connected respectively to inputs 8.28 and 8.29 in order to provide the microcomputer 8 with data representing the signals applied to inputs 14.3, 14.4 and 14.5. A 14.9 quartz resonator is connected to input 14.11 and to the output 14.12 of circuit 14 in order to constitute a base of time for this one.

Pager 1 also includes an alarm 26 coupled to microcomputer 8 so that a new message information received by the decoder 4 can be announced. An electric sound transducer 26a or "buzzer" is connected by one of its terminals to collector of a switching transistor 26b and by its other terminal to the positive supply conductor 16.1. The collector of transistor 26b is also connected to the microcomputer 8 output 8.31 via of a bias resistor 26c which may have a 18 kΩ value. Normally this output is kept at a high logical level. The emitter of transistor 26b is connected to negative supply conductor 16.2 and to terminal 8.6 of the microcomputer 8. The base of the transistor 26b is connected to output 8.30 of it. A self 26d with a value of 45 mH, for example is connected in parallel to buzzer 26a. Finally, a 26th capacitor of voltage stabilization with a value of 4.7 µF, is connected between positive power leads 16.1 and negative 16.2. In normal operation, the output 8.30 is kept low and transistor 26b is non-conductive.

When pager 1 must announce the receipt of a call or the performance of another function, a signal which may have a variable waveform is sent by the output 8.31 which generates a voltage across the buzzer 26a, which will thus produce a first sound. A sound different can be produced by horn 26, when a signal is sent from output 8.30 to the base of transistor 26b which then starts to drive. A different voltage is then generated across the buzzer 26a and a second sound is produced. These different sounds can be used to announce completion of various functions by the pager 1.

Figure 4 shows a simplified memory diagram smart 5 which basically includes unit 6 of data processing, memory area 7, ROM 27, register stack 28, microprocessor interface 29 and the decoder interface 30. Terminals 5.5 to 5.12, already described, are connected to the microprocessor interface 29, while terminals 5.1 and 5.2, also already described, are connected to the decoder interface 30. The input providing the 32 kHz clock signal to the smart memory 5 is connected to unit 6 of data processing. In addition, the interface of microprocessor 29 includes a test input 5.13, a 5d capacitor which can have a value of 15 nF, being connected between negative supply conductor 16.2 and an entry 5.14 of memory area 7.

Smart memory 5 also includes buses 5th and 5k addresses and data connected between various internal elements of memory 5 in order to be able ensure communication and transfer between them data. ROM 27 contains the necessary programs to operate the memory 5. In the realization described here, memory area 7 is RAM with a capacity of 512 bytes and intended to memorize the message signals from decoder 4 and the internal system variables, the register stack 28 forming, on the one hand, a memory for memorization temporary data used to manipulate message information stored in the memory area 7, and, on the other hand, the stack pointer and the counter of program.

Specialists will understand that calls are normally transmitted more than once from a station central to a given pager to guarantee the security of a good reception by this pager. Therefore, before write the message information received from decoder 4 to memory area 7, smart memory 5 can advantageously compare this message information received in the two previous messages that the pager has just to receive. If the new message information matches to either of these two most recent messages, the new message is not written to the memory area 7.

As already indicated and as shown in the figure 5, it is envisaged, in the embodiment of the invention considered to give memory area 7 a capacity of 512 bytes. Such a capacity is sufficient for give pager 1 manipulation possibilities information that makes it comfortable to use.

A capacity of 512 bytes requires nine bits to allow addressing of bytes 0 to 511 of the memory 7. This means that for each operation write or read in this memory area, two transfers of eight bits each are necessary because the buses 5e to 5k have eight bit transfer capacity only at a time. The program stored in ROM 27 is suitable for working with such a double transfer to eight bits of which, in the present embodiment, only nine bits are used. In fact, we can therefore, without significantly changing the program contained in the ROM 27, easily increase the capacity of the memory area 7 up to a maximum of 65 kilobytes, which is a value far exceeding the capacity of 4 kilobytes which would already be a value giving great comfort of use. Such an extension of the capacity of memory would give the pager the ability to run more user-controlled functions and also a greater ability to retain message information received.

The memory area 7 includes address segments 7a, 7b and 7c (Figure 5), including segments 7a and 7b include addresses 0 to 489 and are available for storage of message information received from the decoder 4 and whose segment 7c includes the addresses 490 to 511 and contain internal memory variables smart 5.

Address segment 7a includes addresses 0 to 300 and it is used by data processing unit 6 as a circular buffer to store information from incoming message from decoder 4 so that the memory location assigned to the circular buffer is first sequentially filled with information from message received. After memorizing information from message to each available address of the circular buffer, oldest message information is transferred at the time the most recent message information is received by smart memory 5. By default, the address segment 7b occupying addresses 301 to 489 east used as a protective section in which is stored message information from buffer circular that the user does not wish to make to transfer.

The address segment 7c comprises the following addresses which are used by the data processing unit 6 to handle the data located in the memory area 7: Address Function 510 This memory location contains the address of the end of the last protected message located in the protection segment 7c. 508 Start address of circular buffer 7a or Top-Of-RAM (TOR). By changing the value stored in this memory location, it is possible to change the capacity of the circular buffer 7a. 503 This register contains a data value which determines the speed, in number of bytes per second, at which the data is transferred from the decoder 4 to the intelligent memory 5 without undergoing any processing or interpretation. 500 Contains the address of the last byte read, when the data processing unit 6 was executing the instruction "PFIN read decrement", described below. 499 The data stored at this address is used to determine which of the newly received message information will be compared with the previous two. This address is initialized with the data 01 Hex and can be transferred with the value 03 Hex when it is desirable to make such a comparison with the two most recent messages. In addition, the following codes which can be stored in the memory area 7 are interpreted by the data processing unit 6 as having a particular meaning: Coded Meaning 08 Hex Beginning and end of protection zone 7b. 04 Hex, 84 Hex Header of a newly received message. 05 Hex, 85 Hex Header of a message to be deleted in the circular buffer 7a. 06 Hex, 86 Hex Header of a message that has been processed by the user of pager 1. 02 Hex, 82 Hex Header of a protected message which has been transferred from the circular buffer 7a to the protection zone 7b.

We will now describe the operation of the data processing unit 6 and the functions which are successively performed by the intelligent memory 5 when the various control signals are received from the microcomputer 8. As described above, the latter is capable of 'indicate to the intelligent memory 5 that it wishes to send a control signal by bringing the output 8.9 to a high level. When the output 5.10 is at the high level, a control signal present at the outputs 8.1 to 8.4 is read by the intelligent memory 5, when a logical transition from bottom to top occurs at the output 8.11. Under these conditions, the following functions can be performed by the intelligent memory 5, each function code representing the logic state of the outputs 8.4 to 8.1 respectively: Coded Function 0000 The circuit of the memory area 7 is reset. This function is sent to the smart memory 5 when the pager is started. The size of the circular buffer is set to 300 bytes by default. The reset of the chip must be maintained for at least two clock periods. 0100 The total contents of RAM 7 are copied with "." or with another uniform character without new setting of the circular buffer 7a. The RAM is initialized as above, but without resetting the size of the buffer 7a. This can be advantageous if the buffer size is other than 300 bytes by replacing TOR. 1000 The intelligent memory 5 uses the outputs 5.5 to 5.8 as a status indicator in order to inform the microcomputer 8 about the message information received from the decoder 4. The outputs 5.5 to 5.8 have the following meaning: 5.5 Repeat message 1 5.6 Repeating message 2 5.7 New message 5.8 Error 0001 Write stack pointer (PTA) - The address of the RAM containing the PTA is copied with new data sent to RAM 7 in three packets of four bits each. A change in the actual PTA value will only occur if all four bit packets are entered correctly. 1001 Stack pointer (PTA) for reading - The stored value of the PTA is read by the data processing unit 6 in three consecutive packets of four bits each.

The following functions are used for reading and writing in memory area 7. The current address of the area memory 7 to which message information should be stored or read, must first be placed in the PTA register. With a high logic level at output 8.9 microcomputer 8, the data present at the inputs 5.5 to 5.8 are treated as control signals. Message information can then be forwarded to intelligent memory 5 or be extracted therefrom, when the logic level at output 8.9 again takes a level low.

When an entire byte (two packets of four bits each) has been completely transferred, the position of the PTA pointer remains unchanged. Therefore, it is possible to copy a byte already read in RAM 7 without having to change the position of the PTA. It is only during the transfer of the first packet of four bits which are the most significant bits of the data, namely during the appearance of the rising edge of the transition from bottom to top of the output 8.11, that the PTA will be increased or decreased and the address of the RAM 7 to which it points, changed. Coded Function 1010 Increment after reading in RAM - the content of the address on which the pointer points, is read, then the PTA is automatically incremented. 1011 Decrement after reading in RAM - the content of the address to which the pointer points is read, then the PTA is automatically decremented. 0010 Increment after writing to RAM - data is transferred to smart memory 5, then written to the address pointed to by the PTA pointer with an automatic increment. 0011 Decrement after writing to RAM - data is transferred to intelligent memory 5, then written to the address pointed to by the PTA pointer, with an automatic decrement. 1100 Decrement after reading in PFIN - PFIN is a stack pointer which indicates the end of the circular buffer in RAM 7. The command 1100 causes the reading of the contents of the memory having the address of PFIN. After reading each byte, PFIN is automatically decremented so that each byte is read only once. If PFIN has reached the last byte of the message information, as indicated by the header 04 H or 84 H, the logic level of output 5.12 is raised to a high level with an error indicated in the word state, when the least significant four-bit packet is read. It is therefore possible to read all the message information stored in the memory segment 7a until the end of the circular buffer.
PFIN is initialized to the TOR value.

The following functions relate to a single complete message, instead of separate bytes of message information comprising the message. To separate messages from each other, the 04 H or 84 H code is written with the data packet at the end of each message and at the start of the next message (header). The PTA must contain the address of the header of the message to be handled by the data processing unit 6 so that the following instructions can be executed. If the PTA does not contain this address, an interrupt signal is supplied by a high logic level at output 5.12, an error being found in the status word. Coded Function 0101 Change header - a message is marked as having already been processed, by changing the byte at the start of the message to 06H or 86H. This can advantageously avoid a conflict between old message information and message information just received. 0110 Message protection - a message can be protected against a write fault by copying it to the protected area of address segments 7b. The message header in the circular buffer is first changed to 05 H or 85 H, then copied, byte after byte in the protected area. Then, the message is automatically deleted in the circular buffer 7a (no new code is necessary). 0111 Deleting a message - a message can be deleted from the circular buffer or the protected area. First, a message is marked for deletion by changing the header to 05H or 85H. It is then checked whether this message should be compared with new messages received by pager 1, in order to avoid the memorization of a repeated message. When the message can be deleted, all of its bytes will be deleted. If deletion is not possible immediately, the message remains marked and is deleted as soon as possible (but this requires a new delete command).

From the above, we can see that the memory intelligent 5 according to the invention is suitable for receive real-time message information from decoder 4, to compare the message received with the messages previously received and to store information from message selected in the memory area. Memory intelligent 5 is also able to copy, delete, move or otherwise manipulate information from memorized message and to communicate and exchange information with the microcomputer 8 in a way such that it is freed from the constraints linked to the reception, storage and manipulation message information.

Claims (14)

1. Pager intended for receiving coded radio broadcast message signals comprising call signal information and message information comprising one or several messages, the pager comprising:

   a receiver (3) for receiving and demodulating said coded signals,

   a memory arrangement (5) intended to store said message information

   a decoder (4) intended to decode said coded message signals for selectively furnishing said message information to said memory arrangement (5), and

   function control means (8) including a microprocessor or a microcomputer intended to furnish control signals to said memory arrangement (5) and to receive therefrom stored message information,

   said pager being characterized in that

   said memory arrangement (5) comprises internal processing means (6) intended to control the reception of said message information from said decoder (4), said internal processing means being distinct from said control means.
2. Pager according to claim 1, characterized in that said internal processing means (6) are arranged to control the reception of said message information directly from said decoder (4), independently of control signals coming from said function control means (8).
3. Pager according to claim 1 or 2, characterized in that said internal processing means (6) are also arranged to manipulate said message information stored in said memory arrangement (5).
4. Pager according to any one of the preceding claims, characterized in that said memory arrangement (5) comprises memory locations forming a circular buffer (7a) in which said message information coming from the decoder (4) is stored.
5. Pager according to claim 4, characterized in that the number of memory locations within said circular buffer (7a) is adjustable.
6. Pager according to any one of the preceding claim, characterized in that said internal processing means (6) are also arranged to compare the messages received by said memory arrangement (5) and which come from said decoder (4) with previously stored messages.
7. Pager according to claim 6, characterized in that each of said messages received from said decoder (4) is stored in said memory arrangement (5) only if it differs from the one or several previously stored messages.
8. Pager according to any one of the preceding claims, characterized in that said memory arrangement (5) comprises a protection zone (7b) with memory locations intended for the protection of memory information which is stored therein in order to be protected against unauthorized replacement by subsequently received message information from said decoder (4), said internal processing means (6) being furthermore adapted to write selected stored message information into said protection zone (7b) of said memory arrangement (5).
9. Pager according to any one of the preceding claims, characterized in that said internal processing means (6) are further adapted to delete message information stored in said memory arrangement (5).
10. Pager according to claim 9, characterized in that said internal processing means (6) are further adapted to delete message information contained in either said protection zone (7b) or said circular buffer (7a).
11. Pager according to any one of the preceding claims, characterized in that said memory arrangement (5) is arranged to receive said control signals from said function control means (8) and to furnish message information thereto and in that said function control means (8) comprise, to such effect, a parallel input/output (5.5, 5.6, 5.7, 5.8).
12. Pager according to claim 11, characterized in that said parallel input/output (5.5, 5.6, 5.7, 5.8) is adapted to transfer four data bits at a time.
13. Pager according to any one of the preceding claims, characterized in that it further comprises at least one input (14b, 14c, 14d) adapted for actuation by a user in order to control the operation thereof, in that and a timepiece (14, 15) is housed in the pager, and in that said user actuable input (14b, 14c, 14d) is also adapted to control operation of said timepiece (14, 15).
14. Pager according to claim 13, characterized in that it assumes the form of a wristwatch.

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