EP0570983B1 - Hardware-Verschlüsselungsschaltung unter Verwendung von mehreren linearen Transformationsausführungen - Google Patents

Hardware-Verschlüsselungsschaltung unter Verwendung von mehreren linearen Transformationsausführungen Download PDF

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Publication number
EP0570983B1
EP0570983B1 EP93108296A EP93108296A EP0570983B1 EP 0570983 B1 EP0570983 B1 EP 0570983B1 EP 93108296 A EP93108296 A EP 93108296A EP 93108296 A EP93108296 A EP 93108296A EP 0570983 B1 EP0570983 B1 EP 0570983B1
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Prior art keywords
output
arithmetic operations
outputting
hardware arrangement
coupled
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Expired - Lifetime
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EP93108296A
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English (en)
French (fr)
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EP0570983A1 (de
Inventor
Michio Shimada
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NEC Corp
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NEC Corp
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
    • H04L9/0625—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation with splitting of the data block into left and right halves, e.g. Feistel based algorithms, DES, FEAL, IDEA or KASUMI
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/12—Details relating to cryptographic hardware or logic circuitry

Definitions

  • the present invention relates to an arrangement for transforming plaintext into the corresponding ciphertext in a digital data communications system.
  • the arrangement disclosed is also applicable to the reverse process of transforming ciphertext into the original plaintext.
  • a cipher is a secret method of writing whereby plaintext (or cleartext) is transformed into the corresponding ciphertext (sometimes called a cryptogram).
  • plaintext or cleartext
  • the process is called encipherment or encryption, while the reverse process of transforming ciphertext into the corresponding plaintext is called decipherment or decryption. Both encipherment and decipherment are controlled by a cryptographic key or keys.
  • a known encipherment which is currently used, is to linearly transform plaintext M into the corresponding ciphertext C as shown in equation (1):
  • C a•M + b mod N
  • a, b, and N each is a predetermined integer.
  • the plaintext M is a data word having a constant bit length.
  • "b mod N” implies a residue when "b" is divided by "N”.
  • the ciphertext C can be transformed into the corresponding plaintext using the following equation (2).
  • the keys a and b can be determined by solving the following linear equations (4A)-(4L). In this case, breaking the cipher is not difficult.
  • the cipher is particularly vulnerable if a cryptanalyst is able to input plaintext to an encipher and observe the changes in the resulting ciphertext.
  • DES Data Encryption Standard
  • ROM read-only-memory
  • the DES using non-linear transformation is able to render cryptayalysis difficult but it suffers from complicated hardware arrangement and low transmission rate.
  • WO-A-89/07375 discloses a cryptographic apparatus for encrypting and decrypting digital words including a mechanism that permits a cipher algorithm to be electronically stored after the manufacture of the apparatus.
  • the storing mechanism includes at least one electrically erasable, programmable gate array containing a portion of the cipher algorithm and at least one random access memory device coupled to the array for storing digital data generated by the algorithm.
  • a mechanism which is coupled to the gate array and memory device controls the execution of the algorithm for each digital word thereby decrypting encrypted digital words and encrypting non-encrypted digital words.
  • each operation of linear transformations is carried out using different moduli in order to render computationally infeasible to break the cipher.
  • the keys a and b are also changed at each linear transformations. That is, it is within the scope of the present invention that: (a) all the keys a, b, and N are changed at each linear transformation; and (b) only N is changed at each linear transformation.
  • equation (5) is rewritten into the following equations (7A), (7J) and (7K).
  • x 1 a 1 •M + b 1 mod N
  • C a k •x k-1 + b k mod N k
  • x(1) a•M(1) + b mod N 1
  • C(1) a•x(1) + b mod N 2
  • C(L) a•x(L) + b mod N 2 x(L) ⁇ N 1
  • x and y are congruent each other with a modulus z. If N 1 and N 2 are prime numbers with each other (viz., the minimum common number is 1), then simultaneous congruent equations for x(j) has always a solution.
  • these discussions are described on pages 47-48 of the above-mentioned book.
  • the key N should be selected such as to satisfy N 1 ⁇ N 2 ⁇ ••• ⁇ N k . This is because if N j+1 ⁇ N j in the operations of the j-th and (j+1)-th linear transformations, some integers are undesirably transformed into an identical integer and thus the plaintext is no longer deciphered uniquely.
  • Fig. 1 wherein a first embodiment of the present invention is schematically illustrated in block diagram form. It is assumed that the number of repetitive linear transformations is k.
  • a plurality of cryptographic keys (a 1 , ..., a k ), (b 1 , ..., b k ), and (N 1 , ..., N k ) are applied to a memory 14 via an input terminal 12 and then stored therein. Further, the number of repetitive operations of linear transformation (k) is applied to a controller 18 via an input terminal 20 and stored in a register 16 provided therein. It is assumed that the plaintext is formed of a plurality of data words each of which has a 64-bit length by way of example. The words are sequentially applied to the arrangement of Fig. 1, after which the word is subject to the k linear transformations.
  • the controller 18 allows the selector 22 to apply the word to a multiplier 26. Further, the controller 18 controls the memory 14 such as to apply a 1 , b 1 , and N 1 to the multiplier 26, an adder 28, and a divider 30, respectively.
  • the suffix "i” attached to "a", "b", and “N” takes sequentially the values cf is 1, 2, ..., k at each linear transformation.
  • the multiplier 26 multiplies the output of the selector 22 by the key a 1 , and applies the product to the adder 28. Subsequently, the adder 28 adds the key b 1 to the output of the multiplier 26, after which the divider 30 divides the output of the adder 28 by the key N 1 and outputs the residue of the dividing operation. The residue thus obtained is routed back to the selector 22 via a line 32 and also applied to an output controller 34.
  • the controller 18 allows the output controller 34 to pass therethrough the residue obtained from the divider 30 only if the number of the repetitive linear transformations reaches "k". In this case, the selector 22 applies, under the control of the controller 18, the output of the divider 30 to the multiplier 26.
  • the controller 18 instruct the output controller 34 to output the last residue (viz., ciphered word) to external circuitry (not shown) via an output terminal 36.
  • Fig. 1 The arrangement of Fig. 1 is applicable to decipherment by which the ciphertext is transformed into the corresponding plaintext.
  • (a 1 , ..., a k ), (b 1 , ..., b k ), and (N 1 , ..., N k ) stored in the memory 14 in the above-mentioned encipherment are respectively replaced by:
  • N j ⁇ N j+1 should be satisfied (viz., N 1 ⁇ N 2 ⁇ ••• ⁇ N k ) in the first embodiment.
  • N j ⁇ N j+1 N 1 ⁇ N k
  • N 1 ⁇ N k the number of digits of the ciphertext becomes larger than that of the plaintext. This means that the data transmission rate is undesirably lowered.
  • a second preferred embodiment is to overcome this difficulty of the first preferred embodiment.
  • each range of the definition and the values in the linear transformation including the residue calculation is ⁇ 0, ..., (N-1) ⁇ ; and (b) the bit length of the key N is n.
  • the value of a given word applied to the linear transformation arrangement is equal to or greater than the value of the key N, the given value is outputted without being subject to any linear transformation.
  • the value of the given word applied to the linear transformation arrangement does not reach the value of the key N, the given word is enciphered (viz., undergoes the linear transformation).
  • each range of the definition and the values in the linear transformation is extended to the maximum range of ⁇ 0, ..., 2 n -1 ⁇ .
  • a code converter is provided prior to the linear transformation arrangement wherein "multiplication”, “addition” and “division” are carried out.
  • the code converter converts each of the word's values applied thereto into a predetermined value. More specifically, the code converter is able to make smaller the value of the word, which is equal to or exceeds the value of the key N, than the value of the key N. Accordingly, if the word, which has bypassed the linear transformation arrangement, is applied to the code converter, the word in question is subject to the linear transformation without failure.
  • the arrangement of Fig. 2 differs from that of Fig. 1 in that the former arrangement further includes a code converter 40, a comparator 42, and a selector 44.
  • the arrangement of Fig. 2 is essentially identical to that of Fig. 1.
  • the memory 14 of Fig. 2 stores (a 1 , a 1 ), ..., (a k , a k ), (b 1 , b 1 ), ..., (b k , b k ), (N 1 , N 1 ), ..., and (N k , N k ) all of which are applied to the memory 14 via the input terminal 12.
  • the register 16 stores 2k which is applied thereto via the input terminal 20.
  • each of the words and the keys N 1 and N 2 has a bit length of 64. Further, it is assumed that the most significant bit (MSB) of the key N is a logic 1. Thus, if the code converter reverses the MSB of the word applied thereto, the word whose value is equal to or exceeds the value of the key N 1 or N 2 , is rendered less than the value of the key.
  • MSB most significant bit
  • a plurality of cryptographic keys (a 1 , a 1 ), ..., (a k ,a k ), (b 1 , b 1 )..., (b k , b k ), and (N 1 , N 1 )..., (N k , N k ) are applied to the memory 14 and then stored therein. Further, the number of repetitive operations of linear transformation (2k) is applied to the controller 18 and then stored in the register 16. The words are sequentially applied to the arrangement of Fig. 2.
  • the controller 18 allows the selector 22 to apply the word to the code converter 40. Further, the controller 18 controls the memory 14 such as to apply a 1 , b 1 , and N 1 to the multiplier 26, an adder 28, and a divider 30, respectively.
  • the multiplier 26 multiplies the output of the code converter 22 by the key a 1 , and applies the product to the adder 28. Subsequently, the adder 28 adds the key b 1 to the output of the multiplier 26, after which the divider 30 divides the output of the adder 28 by the key N 1 and outputs the residue of the dividing operation. The residue thus obtained is applied to the selector 44.
  • the output of the code converter 40 is applied to the comparator 42 and the selector 44. Further, the key N 1 is applied to the comparator 42. If the output of the code converter 40 is equal to or exceeds the key N 1 , the selector 44 selects the output of the code converter 40 which is fed back to the converter 40. Otherwise, the selector 44 selects the residue from the divider 30 and applies same to the code converter 40 via the selector 22 as mentioned above with respect to the first embodiment.
  • selector 44 selects the output of the code converter 40, then the next time the selector 44 selects the output of the divider 30.
  • the controller 18 allows the output controller 34 to pass therethrough the output of the selector 44 only if the number of the repetitive linear transformations reaches 2(k-1) or 2k and simultaneously if the selector 44 selects the output of the divider 30.
  • the controller 18 Upon completion of the last linear transformation, the controller 18 instruct the output controller 34 to output the last residue (viz., ciphered word) to external circuitry (not shown) via an output terminal 36.
  • the last residue viz., ciphered word
  • Fig. 3 is a block diagram schematically showing the third embodiment of the present invention.
  • the code converter 40 is provided between the two selectors 22 and 44.
  • the third embodiment is such as to implement the code conversion after the operations of comparator 42.
  • the operations of the third embodiment will be understood from the descriptions of the second embodiment, and hence further discussion will not be given merely for the sake of brevity.

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  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Storage Device Security (AREA)
  • Complex Calculations (AREA)

Claims (4)

  1. Vorrichtung zum Umwandeln von Klartext in einen entsprechenden verschlüsselten Text, wobei der Klartext mehrere Wörter mit jeweils einer vorgegebenen Bitlänge aufweist, die Vorrichtung die Wörter sequentiell erfaßt und eine vorgegebene Anzahl arithmetischer Operationen bezüglich eines erfaßten Wortes ausführt, jede arithmetische Operation mehrere arithmetische Prozesse umfaßt, und wobei die Vorrichtung ein verschlüsseltes Wort ausgibt, wenn die vorgegebene Anzahl arithmetischer Operationen abgeschlossen ist;
       gekennzeichnet durch:
    eine erste Einrichtung (22) zum Empfangen eines ersten und eines zweiten Eingangssignals und zum selektiven Ausgeben des ersten oder des zweiten Eingangssignals, wobei das erste Eingangssignal dem erfaßten Wort entspricht;
    eine zweite Einrichtung (26) zum Empfangen des Ausgangssignals der ersten Einrichtung, wobei die zweite Einrichtung das Ausgangssignal der ersten Einrichtung mit einem Multiplikationswert multipliziert und ein Produkt ausgibt;
    eine dritte Einrichtung (28) zum Empfangen des Produktes, wobei die dritte Einrichtung das Produkt und einen Summanden addiert und anschließend eine Summe ausgibt; und
    eine vierte Einrichtung (30) zum Empfangen der Summe, wobei die vierte Einrichtung die Summe durch einen Modul teilt und einen Rest ausgibt, wobei während jeder der arithmetischen Operationen ein anderer Modul verwendet wird, wobei der Rest der ersten Einrichtung (22) als zweites Eingangssignal zugeführt wird und von der Vorrichtung als verschlüsseltes Wort ausgegeben wird, wenn die vorgegebene Anzahl arithmetischer Operationen abgeschlossen sind.
  2. Vorrichtung nach Anspruch 1, wobei der Multiplikationswert sich bei jeder der arithmetischen Operationen ändert.
  3. Vorrichtung nach Anspruch 1 oder 2, wobei der Wert des Summanden sich bei jeder der arithmetischen Operationen ändert.
  4. Vorrichtung nach Anspruch 1, 2 oder 3,
       gekennzeichnet durch:
    eine fünfte Einrichtung (40) zum Empfangen des Ausgangssignals der ersten Einrichtung, wobei die fünfte Einrichtung einen Wert des Ausgangssignals der ersten Einrichtung (22) ändert, wobei die Änderung eine Operation umfaßt, durch die der Wert des Ausgangssignals der ersten Einrichtung kleiner wird als ein bei der Divisionsoperation verwendeter Modul, und die fünfte Einrichtung ein Ausgangssignal des geänderten Wertes an die zweite Einrichtung (26) ausgibt;
    eine sechste Einrichtung (42) zum Vergleichen des Ausgangssignals der fünften Einrichtung (40) mit dem Modul, wobei die sechste Einrichtung ein Steuersignal ausgibt, dessen Inhalt sich in Abhängigkeit vom Ergebnis des Vergleichs ändert; und
    eine siebente Einrichtung (44) zum Empfangen der Ausgangssignale der vierten, der fünften und der sechsten Einrichtung (30, 40 bzw. 42), wobei die siebente Einrichtung (44) angeordnet ist, um das Ausgangssignal der vierten (30) oder der fünften (40) Einrichtung gemäß dem Steuersignal auszuwählen, und die siebente Einrichtung (44) das ausgewählte Ausgangssignal der ersten Einrichtung (22) zuführt.
EP93108296A 1992-05-21 1993-05-21 Hardware-Verschlüsselungsschaltung unter Verwendung von mehreren linearen Transformationsausführungen Expired - Lifetime EP0570983B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP12840992A JP3180836B2 (ja) 1992-05-21 1992-05-21 暗号通信装置
JP128409/92 1992-05-21

Publications (2)

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EP0570983A1 EP0570983A1 (de) 1993-11-24
EP0570983B1 true EP0570983B1 (de) 1998-08-12

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US (1) US5301235A (de)
EP (1) EP0570983B1 (de)
JP (1) JP3180836B2 (de)
AU (1) AU654797B2 (de)
CA (1) CA2096818C (de)
DE (1) DE69320246T2 (de)

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Publication number Priority date Publication date Assignee Title
FR2677200B1 (fr) * 1991-05-30 1993-09-17 Besnard Christian Dispositif de securisation de donnees numeriques.
JP2727955B2 (ja) * 1994-02-14 1998-03-18 日本電気株式会社 公開鍵暗号装置
JP2725610B2 (ja) * 1994-09-27 1998-03-11 日本電気株式会社 秘密鍵暗号方法及び装置
JPH08179690A (ja) * 1994-12-22 1996-07-12 Nec Corp プロダクト暗号装置
KR100250803B1 (ko) 1995-09-05 2000-04-01 다니구찌 이찌로오 데이타 변환장치 및 데이타 변환방법
US6041123A (en) * 1996-07-01 2000-03-21 Allsoft Distributing Incorporated Centralized secure communications system
US5841872A (en) * 1996-07-01 1998-11-24 Allsoft Distributing Incorporated Encryption enhancement system
JPH1153173A (ja) * 1997-08-07 1999-02-26 Nec Corp 擬似乱数発生方法及び装置
US6061821A (en) * 1998-01-09 2000-05-09 The United States Of America As Represented By The Secretary Of The Navy Context based error detection and correction for binary encoded text messages
TW419925B (en) 1998-01-27 2001-01-21 Mitsubishi Electric Corp Method and apparatus for arithmetic operation and recording medium thereof
US20020116624A1 (en) * 2001-02-16 2002-08-22 International Business Machines Corporation Embedded cryptographic system
JP2003098959A (ja) * 2001-09-21 2003-04-04 Toshiba Corp 暗号処理装置
US7260217B1 (en) * 2002-03-01 2007-08-21 Cavium Networks, Inc. Speculative execution for data ciphering operations
US8811606B2 (en) * 2007-04-20 2014-08-19 Unoweb Inc. Asymmetric cryptography using shadow numbers
US20080260153A1 (en) * 2007-04-20 2008-10-23 John Almeida Symmetric and asymmetric cryptography using shadow numbers
JP2009239435A (ja) * 2008-03-26 2009-10-15 Oki Semiconductor Co Ltd パケット中継装置
IL256640A (en) 2017-12-28 2018-04-30 Elta Systems Ltd Supplementary apparatus, methods and computer program products, for cdma encapsulation

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US4134071A (en) * 1971-07-19 1979-01-09 Licentia Patent-Verwaltungs-G.M.B.H. SSMA Data transmission system
DE2756637C2 (de) * 1977-12-16 1979-12-13 Gretag Ag, Regensdorf, Zuerich (Schweiz) Kryptogrammwandler
US4375579A (en) * 1980-01-30 1983-03-01 Wisconsin Alumni Research Foundation Database encryption and decryption circuit and method using subkeys
JPH0727325B2 (ja) * 1987-02-13 1995-03-29 沖電気工業株式会社 暗号化装置
US4914697A (en) * 1988-02-01 1990-04-03 Motorola, Inc. Cryptographic method and apparatus with electronically redefinable algorithm
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SE468730B (sv) * 1991-07-01 1993-03-08 Securicrypto Ab Krypteringsanordning och dekrypteringsanordning

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Publication number Publication date
JP3180836B2 (ja) 2001-06-25
AU654797B2 (en) 1994-11-17
JPH0675525A (ja) 1994-03-18
CA2096818A1 (en) 1993-11-22
CA2096818C (en) 1995-10-10
DE69320246T2 (de) 1998-12-17
DE69320246D1 (de) 1998-09-17
EP0570983A1 (de) 1993-11-24
AU3873693A (en) 1993-11-25
US5301235A (en) 1994-04-05

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