EP0554265B1 - Zweistufiger analog-digital-wandler - Google Patents

Zweistufiger analog-digital-wandler Download PDF

Info

Publication number
EP0554265B1
EP0554265B1 EP91916191A EP91916191A EP0554265B1 EP 0554265 B1 EP0554265 B1 EP 0554265B1 EP 91916191 A EP91916191 A EP 91916191A EP 91916191 A EP91916191 A EP 91916191A EP 0554265 B1 EP0554265 B1 EP 0554265B1
Authority
EP
European Patent Office
Prior art keywords
analog
voltage
comparators
vin
sample
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP91916191A
Other languages
English (en)
French (fr)
Other versions
EP0554265A1 (de
Inventor
Barbara Baggini
Luciana Coppero
Franco Maloberti
Giuseppe Palmisano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Italtel SpA
Original Assignee
Italtel SpA
Italtel Societa Italiana Telecomunicazioni SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Italtel SpA, Italtel Societa Italiana Telecomunicazioni SpA filed Critical Italtel SpA
Publication of EP0554265A1 publication Critical patent/EP0554265A1/de
Application granted granted Critical
Publication of EP0554265B1 publication Critical patent/EP0554265B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
    • H03M1/144—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit the steps being performed sequentially in a single stage, i.e. recirculation type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type
    • H03M1/361—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type
    • H03M1/362—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type the reference values being generated by a resistive voltage divider
    • H03M1/365—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type the reference values being generated by a resistive voltage divider the voltage divider being a single resistor string

Definitions

  • the present invention refers to a two-step analog-to-digital converter for the conversion of an analog electric signal into a digital electric signal. In the first step the most significant bits (MSBs) are coded and in the second step the last significant bits (LSBs) of the digital code are determined.
  • MSBs most significant bits
  • LSBs last significant bits
  • This converter relies on flash technique, where the input to be coded is simultaneously compared to a plurality of reference voltages.
  • Some known implementations of the two-step flash conversion require two resistive ladders, one for the MSBs and the other one for the LSBs.
  • the comparators employed in the two subsequent conversion steps are the same.
  • some known solutions propose a conversion scheme where the LSBs are determined by using the same resistive ladder of the MSBs coarse conversion, introducing an amplifier circuit with gain equal to 2 N/2 .
  • This amplifier has a loop gain-bandwidth product equal to the product between the open loop cut off frequency and the feedback factor, which is close to 1/2 N/2 .
  • This prior art converter requires a subtractor to carry out the difference between the analog input value to be converted and its coarse approximation, and an additional shortcoming resides in the large number of switches on the resistive ladder.
  • the object of the present invention is to realize the analog-to-digital converter of the above type using a single resistive ladder, which overcomes such drawbacks.
  • the converter forming the object of the present invention gets to obtain good operation speed, low power dissipation and limited silicon die size while preserving the monotonic nature of potentiometric converters.
  • an analog-to-digital converter for the conversion of an analog input signal to a N bit digital code
  • a sample and hold circuit receiving at its input terminal the analog signal to be converted, the sample and hold circuit comprising a capacitor, the upper plate of which is connected to the input terminal; a ladder of resistances connected in series between two reference voltage sources for the generation of intermediate comparison voltages, said ladder consisting of 2 N elementary resistances clustered in 2 N/2 segments, each one comprising 2 N/2 elementary resistances; a set of 2 N/2 -1 comparators connectable for the comparison between the input signal and said intermediate reference thresholds; a plurality of latches connected to the outputs of said comparators; a coder to associate a digital code to the output configuration of said comparators, according to preset rules; a storage buffer to store the digital code produced; characterized by the inclusion of a switch block able to connect the reference inputs of said comparators to the elementary resistances of a predetermined segment, and whereby the sample and hold circuit receives
  • the converter in accordance with the prior art teaching includes a resistive ladder labelled SR, a set of comparators or comparing elements (2 N/2 - 1 in number), clustered in the COMP block.
  • each comparator can selectively be connected to the taps of segments GR (case A), to the taps of the single elementary resistances Rei of a chosen segment GR (case B) and to the output of the sample and hold circuit S/H (case C).
  • the connection is made through a plurality of switches SWG; in case B it is made by a controlled switch block (SWF) selected by a combinatorial circuit (LCC) whose inputs matches the outputs of said latches LT; finally in case C, through a plurality of switches SWI.
  • SWF controlled switch block
  • LCC combinatorial circuit
  • the 2 N/2 -1 outputs of comparators are connected to the same number of latches or hold circuits forming the LT block, and from these ones to the encoder COD whose generated code is stored in the output latches LTU. It is also provided a combinatorial logic circuitry LCC between the block LT and switch blocks SWF.
  • the resistive ladder SR is made of 2N elementary resistances Re of equal value, where N is the number of bits by which the analog signal shall be coded, clustered in 2 N/2 segments, each one consisting of 2 N/2 elementary resistances (see Fig. 2).
  • the terminals of the ladder SR are connected to two reference voltages Vref1 and Vref2 defining the dynamic range of the input signal.
  • Voltage values available at the taps of the main segments GR represent the decisional thresholds for the conversion of the MSBs and are forced at the comparators COMP through the closing of the 2 N/2 -1 switches forming SWG.
  • Voltages available at the taps of the elementary resistances Re inside each segment GR represent the reference levels for the determination of the LSBs. In this case the connection to comparators is assured by SWF blocks, each one consisting of 2 N/2 -1 switches, under the control of the logic LCC.
  • comparators of the COMP block are preferably of the type disclosed in WO 91/19355 filed on May 16th, 1991 on behalf of the same applicant under the title: "Low power dissipation autozeroed comparator circuit" reference to which has to be made for further details.
  • comparing circuits of the known type can be employed.
  • the S/H circuit essentially includes a capacitance referred to an analog ground voltage, followed by a unit gain de-coupling element.
  • the middle point of the resistive ladder RS, labelled Vref in Fig. 1, is selected as reference analog ground.
  • comparators COMP are autozeroed, and their reference inputs are connected to the 2 N/2 -1 reference voltages available at the taps of segments GR, indicated also as coarse reference voltages.
  • the input signal Vin is sampled and stored in the S/H circuit.
  • each comparator makes the comparison between the sample of the input signal to be coded and one of the reference levels generated by the resistive ladder SR.
  • the output of each comparator assumes, for instance, the high level when the input signal sample is higher than the reference threshold present at the other input.
  • the digital encoder COD determines the N/2 MSBs, according to the selected coding system.
  • This coding system can be of different type and is not described here in detail.
  • the outputs of comparators are also feed to the LCC selection combinatorial logic and used to identify one of the main resistive segments GR, and more in detail the one whose upper tap corresponds to a reference voltage immediately higher than the value of the input voltage Vin.
  • the LCC logic generates 2 N/2 -1 control signals, controlling in parallel the switch blocks SWF, connected to the taps of the elementary resistances Re of each main resistive segment GR.
  • phase ⁇ 3 second autozero phase of the converter, only one of the aforesaid control signal is activated, and it determines the connection of the 2 N/2 -1 comparators COMP already used, to the new fine reference values internal to the segment GR identified by the LCC logic.
  • phase ⁇ 4 the inputs of comparators are switched again to S/H output to determine the remaining N/2 LABS referring to the voltage Vin stored on the capacitance Ci.
  • the illustrated converter requires a number of switches on the resistive ladder equal to the sum of 2 N/2 -1 (for the MSBs determination) and of 2 N/2 *(2 N/2 -1) (for LSBs determination). These switches conduct current only during a brief transient, therefore they do not affect the voltage value of the point where references for comparison are withdrawn.
  • the converter of the invention provides for a single switch block SWF connected to the resistances of the middle GR segment of the resistive ladder, whose lower tap is referred to the analog ground voltage (Vref).
  • the capacitance Ci of the sample and hold circuit has a plate which can be connected to the input voltage to be converted (Vin), and the other plate selectively connectable to a pedestal voltage (Vlow) chosen by a combinatorial logic LCA, and to the analog ground voltage (Vref).
  • the conversion of the difference between the input voltage Vin and the reference one resulting immediately lower than Vin is performed.
  • phase ⁇ 1 the operation is alike that of the converter of Fig. 1.
  • phase ⁇ 2 coding of the MSBs takes place as before. Furthermore, the selection of an appropriate voltage Vlow takes place in this phase, maintaining the voltage to convert during the second conversion step, within the same predetermined voltage interval ⁇ v, for any input voltage.
  • the pedestal voltage Vlow is selected among a finished set of possible values made of the voltages at the taps of GR segments, including Vref1.
  • Vx at the S/H output is equal to (Vin + Vlow - Vref), where Vref corresponds to the middle point of the resistive ladder.
  • Vref corresponds to the middle point of the resistive ladder.
  • comparator inputs are switched to the voltages of fine reference. These thresholds are obtained at the taps of the elementary resistances Re of the GR resistive segment, referred at the bottom to 2.5 V (Vref) and at the top to (2.5 + ⁇ v) V. At the same time, the bottom plate of the hold capacitance Ci of S/H is connected to the Vlow voltage previously identified.
  • phase ⁇ 4 the operation is similar to the one previously described referring to Fig. 1.
  • the capacitance Ci of S/H is referred to Vlow.
  • the number of switches which persist on the ladder is equal to the sum of 2 N/2 -1 (for the MSBs determination) and of 2 N/2 -1 + 2 N/2 (for the LSBs determination).

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Claims (4)

  1. Analog-digital Wandler zur Umwandlung eines analogen Eingangssignals (Vin) in einen digital Code von N Bits, der folgendes einschließt:
       einen Abtast-Halte-Schaltkreis (S/H), der an seinem Eingang das umzuwandelnde analoge Signal (Vin) empfängt, dieser Abtast-Halte-Schaltkreis schließt einen Kondensator (Ci) ein, dessen obere Elektrode mit dem Eingang verbunden ist;
       einer Kette von Widerständen (SR), die in Serie zwischen zwei Referenzspannungsquellen (Vref1, Vref2) zur Erzeugung von Zwischenvergleichsspannungen eingebunden ist, wobei die genannte Kette aus 2N Elementarwiderständen (Re) besteht, die in 2N/2 Segmenten (GR), von denen jedes 2N/2 Elementarwiderstände umfaßt, gebündelt sind;
       einen Satz von 2N/2 -1 Komparatoren, die zum Vergleich zwischen dem Eingangssignal und den genannten Zwischenreferenzschwellenwerten verbunden werden können;
       eine Mehrzahl von Sperren (LT), die mit den Ausgängen der genannten Koparatoren verbunden sind;
       ein Codierer (COD) zur Verbindung eines Digitalcodes mit der Ausgangskonfiguration der genannten Koparatoren entsprechend vorbestimmter Regeln;
       einen Speicherpuffer (LTU) zur Speicherung der produzierten Codes,
       gekennzeichnet durch das Einschließen einer Schalteinheit (SWF), die geeignet ist, die Referenzeingänge der Koparatoren mit den Elemetarwiderständen (Re) eines vorbestimmten Segments (GR) zu verbinden, und wobei der Abtast-Halte-Schaltkreis (S/H) als Referenz einer Basisspannung (Vlow) und die analoge Massespannung (Vref), die der Spannung des Mittelpunktes der genannten Widerstandskette (SR) entspricht, empfängt, wobei die genannte Basisspannung (Vlow) durch ein logisches Schaltnetz (LCA) ausgewählt wird, das durch einen der Schalter einer anderen Schaltereinheit (SW) mit den Ausgängen der genannten Sperren (LT) verbunden ist, wobei die genannten Schalter der Verbindung der Anschlüsse zwischen den genannten Segmenten (GR) oder einer der Referenzspannungsquellen (Vref1) mit der unteren Elektrode des Kondensators (Ci) des Abtast-Halte-Schaltkreises (S/H) dient.
  2. Analog-digital Wandler nach Anspruch 1, dadurch gekennzeichnet, daß das genante vorbestimmte ohmsche Segment (GR) das ist, welches sich unten auf die analoge Masse (Vref) bezieht.
  3. Analog-digital Wandler nach Anspruch 1, dadurch gekennzeichnet, daß der Abtast-Halte-Schaltkreis (S/H) einen Speicherkondensator einschließt, dessen untere Elektrode mit der genannten Basisspannung (Vlow) und mit einer analogen Massespannung (Vref) verbunden werden kann.
  4. Analog-digital Wandler nach Anspruch 1, 2 oder 3, dadurch gekennzeichnet, daß die genannte Basisspannung (Vlow) unter 2N/2 möglichen Werten, die vom Wert des analogen umzuwandelnden Signals (Vin) abhängen, ausgewählt wird, und zwar auf eine Weise, daß der zweite Umwandlungsschritt auf das selbe vorbestimmte ohmsche Segment (GR) reduziert wird, ungeachtet des Wertes des genannten analogen umzuwandelnden Signals (Vin).
EP91916191A 1990-10-24 1991-09-20 Zweistufiger analog-digital-wandler Expired - Lifetime EP0554265B1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
IT02186390A IT1244078B (it) 1990-10-24 1990-10-24 Convertitore analogico/digitale a due passi di conversione.
IT2186390 1990-10-24
PCT/EP1991/001809 WO1992008287A1 (en) 1990-10-24 1991-09-20 Two-step analog-to-digital converter

Publications (2)

Publication Number Publication Date
EP0554265A1 EP0554265A1 (de) 1993-08-11
EP0554265B1 true EP0554265B1 (de) 1994-05-25

Family

ID=11187926

Family Applications (1)

Application Number Title Priority Date Filing Date
EP91916191A Expired - Lifetime EP0554265B1 (de) 1990-10-24 1991-09-20 Zweistufiger analog-digital-wandler

Country Status (4)

Country Link
EP (1) EP0554265B1 (de)
DE (1) DE69102141T2 (de)
IT (1) IT1244078B (de)
WO (1) WO1992008287A1 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6504499B1 (en) 2000-11-01 2003-01-07 International Business Machines Corporation Analog-to-digital converter having positively biased differential reference inputs

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 24, No. 6, 6 December 1989, New York US, pages 1492-1497, N.K. MAYES et Al.: "A Multistep A/D Converter Family with Efficient Architecture" *
PATENT ABSTRACTS OF JAPAN, Vol. 10, No. 61 (E-387)(2118) 11 March 1986 & JP-A-60 214 120 *
PATENT ABSTRACTS OF JAPAN, Vol. 8, No. 107 (E-245)(1544) 19 May 1984 & JP-A-59 022 440 *

Also Published As

Publication number Publication date
IT1244078B (it) 1994-07-05
WO1992008287A1 (en) 1992-05-14
EP0554265A1 (de) 1993-08-11
DE69102141D1 (de) 1994-06-30
DE69102141T2 (de) 1995-01-05
IT9021863A1 (it) 1992-04-24
IT9021863A0 (it) 1990-10-24

Similar Documents

Publication Publication Date Title
US4200863A (en) Weighted capacitor analog/digital converting apparatus and method
US4542370A (en) Cascade-comparator A/D converter
US5936566A (en) Auto-reference pseudo-flash analog to digital converter
US5231398A (en) Method and apparatus for self-tracking multiple analog to digital conversion
US5914682A (en) Segmentwise operating digital-to-analog converter
JP2768715B2 (ja) 積分直線性エラーを補償したアナログ・ディジタル変換器およびその動作方法
JPS6161578B2 (de)
US4857931A (en) Dual flash analog-to-digital converter
JP2995599B2 (ja) アナログデジタル変換方法
US4381496A (en) Analog to digital converter
US4571574A (en) Analogue to digital converter
EP0554265B1 (de) Zweistufiger analog-digital-wandler
US6154165A (en) Variable clock rate, variable bit-depth analog-to-digital converter
EP0681372B1 (de) Schaltung zur Digital-/Analogumsetzung und die Schaltung benutzender A/D-Wandler
US6154164A (en) Variable clock rate analog-to-digital converter
US5160930A (en) Reference voltage generating circuit, and A/D and D/A converters using the same
US5206649A (en) Dual flash analog-to-digital converter
JP3130007B2 (ja) 逐次比較型ａ／ｄコンバータ回路
US4864304A (en) Analog voltage signal comparator circuit
US5805097A (en) Current-integrating successive-approximation analog-to-digital converter
JPS60216630A (ja) ステツプ発生器
JPS6161577B2 (de)
JPH05167449A (ja) 逐次比較型アナログデジタル変換器
US5568148A (en) Analog/digital conversion circuit
US6222475B1 (en) Three-step converter

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 19930225

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE DK ES FR GB GR NL SE

17Q First examination report despatched

Effective date: 19931007

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE DK ES FR GB GR NL SE

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: ES

Free format text: THE PATENT HAS BEEN ANNULLED BY A DECISION OF A NATIONAL AUTHORITY

Effective date: 19940525

Ref country code: DK

Effective date: 19940525

REF Corresponds to:

Ref document number: 69102141

Country of ref document: DE

Date of ref document: 19940630

ET Fr: translation filed
REG Reference to a national code

Ref country code: GR

Ref legal event code: FG4A

Free format text: 3012701

EAL Se: european patent in force in sweden

Ref document number: 91916191.9

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: SE

Payment date: 19980904

Year of fee payment: 8

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 19980909

Year of fee payment: 8

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 19980914

Year of fee payment: 8

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GR

Payment date: 19980923

Year of fee payment: 8

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 19980925

Year of fee payment: 8

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: NL

Payment date: 19980929

Year of fee payment: 8

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 19990920

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SE

Free format text: THE PATENT HAS BEEN ANNULLED BY A DECISION OF A NATIONAL AUTHORITY

Effective date: 19990929

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 19990930

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20000401

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 19990920

EUG Se: european patent has lapsed

Ref document number: 91916191.9

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20000531

NLV4 Nl: lapsed or anulled due to non-payment of the annual fee

Effective date: 20000401

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20000701

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST