EP0549122A2 - Commutateur extensible de paquets ayant un concentrateur - Google Patents

Commutateur extensible de paquets ayant un concentrateur Download PDF

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Publication number
EP0549122A2
EP0549122A2 EP92310490A EP92310490A EP0549122A2 EP 0549122 A2 EP0549122 A2 EP 0549122A2 EP 92310490 A EP92310490 A EP 92310490A EP 92310490 A EP92310490 A EP 92310490A EP 0549122 A2 EP0549122 A2 EP 0549122A2
Authority
EP
European Patent Office
Prior art keywords
packet
concentrator
outputs
cells
packet switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP92310490A
Other languages
German (de)
English (en)
Other versions
EP0549122A3 (en
Inventor
Kai Y. Eng
Mark J. Karol
Mark Allen Pashan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc, AT&T Corp filed Critical American Telephone and Telegraph Co Inc
Publication of EP0549122A2 publication Critical patent/EP0549122A2/fr
Publication of EP0549122A3 publication Critical patent/EP0549122A3/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/15—Interconnection of switching modules
    • H04L49/1553—Interconnection of ATM switching modules, e.g. ATM switching fabrics
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/15—Interconnection of switching modules
    • H04L49/1553—Interconnection of ATM switching modules, e.g. ATM switching fabrics
    • H04L49/1576—Crossbar or matrix
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478—Provisions for broadband connections
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5603—Access techniques
    • H04L2012/5609—Topology
    • H04L2012/561—Star, e.g. cross-connect, concentrator, subscriber group equipment, remote electronics
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5681—Buffer or queue management

Definitions

  • This invention relates to packet switching and, more particularly, to a growable packet switch architecture.
  • Growable packet switch architectures are known in the art. These prior known architectures, however, were implemented by employing a plurality of mxn (m > n) Packet Switch Units. Although the use of mxn Packet Switch Units has heretofore made sense for growth to a larger packet switch, the individual Packet Switch Units still have to meet the requirement of being stand-alone Packet Switch Modules upon initial deployment.
  • a prior growable packet switch architecture is disclosed in United States patent 4,955,017 issued to K.Y. Eng, M.J. Karol and Y.S. Yeh on September 4, 1990. As such, the Packet Switch Unit would only have to have an equal number of inputs and outputs.
  • an mxn Packet Switch Unit can only be used as an nxn Packet Switch Module upon initial installation. Deploying a full mxn Packet Switch Unit to be used as an nxn Packet Switch Module is wasteful and expensive. Indeed, such a development would incur unnecessary technical and financial risk. Thus, although the prior known mxn Packet Switch Units are satisfactory for certain applications, they are not satisfactory for use as stand-alone nxn Packet Switch Modules.
  • the m:n Concentrator concentrates all arriving packet cells on the m inputs in a prescribed repetitive sequence to the n outputs. This is realized by temporarily buffering any arriving packet cells in excess of available packet cell positions in the n concentrator outputs and by supplying the packet cells arriving on the m inputs to the n outputs in the prescribed repetitive sequence.
  • the prescribed sequence is, in accordance with an aspect of the invention, a "first-in first-out" (FIFO) sequence.
  • a plurality of the resulting Concentrator-Based mxn Packet Switch Units can readily be employed to realize a larger packet switch, as desired.
  • a technical advantage of this invention is that a stand-alone nxn Packet Switch Module can be initially deployed and, then, the m:n Concentrator can be later deployed to grow into a packet switch having a larger number of m inputs.
  • FIG. 1 shows, in simplified block diagram form, an embodiment of the invention employing m:n Concentrator 101 in combination with nxn Packet Switch Module 102 to form mxn Packet Switch Unit 100.
  • nxn Packet Switch Module 102 is advantageous to be able to deploy nxn Packet Switch Module 102 as a stand-alone module and later grow, it in accordance with the invention, to mxn Packet Switch Unit 100.
  • this is realized, in accordance with the invention, by the unique utilization of a prior known nxn Packet Switch Module 102 and, then, employing m:n Concentrator 101 with it at a later date.
  • the nxn Packet Switch Module 102 interrogates each arriving packet cell for its destination address and then routes it to the appropriate one of outputs 105-1 through 105-n. Multiple arriving packet cells destined for the same one of outputs 105 are allowed, and queuing is provided in Packet Switch Module 102 to buffer the multiple arriving packet cells properly so that they can be appropriately read out at the destination output one (1) packet cell at a time. Many techniques are known for implementing Packet Switch Module 102. However, employing a shared memory technique is preferred. As indicated, Packet Switch Module 102 may be one of known such modules (see for example, United States Patent 4,603,416).
  • Concentrator 101 has inputs 103-1 through 103-m and outputs 104-1 through 104-n which are supplied as inputs to Packet Switch Module 102.
  • Packet Switch Module 102 has outputs 105-1 through 105-n.
  • FIG. 2 shows, in simplified form, details of one implementation of Concentrator 101 of FIG. 1. Specifically, shown is random access memory (RAM) 201 and control unit 202.
  • a multiplexer (not shown) is typically used to supply packet cells from inputs 103 to RAM 201 and that a demultiplexer (not shown) is typically used to supply packet cells from RAM 201 to outputs 104.
  • Control unit 202 effects the writing of arriving packet cells from inputs 103 into RAM 201 and the reading of packet cells from RAM 201 to outputs 104 in the FIFO sequence.
  • FIG. 3 graphically illustrates the first-in first-out (FIFO) operation of RAM 201 under control of control unit 202 in realizing Concentrator 101 of FIG. 1.
  • FIFO first-in first-out
  • the predetermined sequence in a particular time slot starts with any packet cell arriving on input 301-1 through any packet cell arriving on 302-4 and is repeated for each successive time slot.
  • packets are shown as arriving on inputs 301-1 through 301-4 in time slots 0 through 3 and are labeled accordingly.
  • packet cells 0 arrive on inputs 301-1, 301-2 and 301-4 in input time slot 0.
  • the arriving packet cell 0 on input 301-1 is immediately supplied to output 302-1 in output time slot 0 and the arriving packet cell 0 on input 301-2 is immediately supplied to output 302-2 in output time slot 0.
  • the arriving packet cell 0 on input 301-4 must be temporarily stored in RAM 201 (FIG.
  • the packet cells arriving in input time slot 1 on inputs 301-2 through 301-4 are accordingly labeled 1.
  • the packet cell 1 arriving on input 301-2 is immediately supplied to output 302-2 to be output in time slot 1.
  • the packet cells 1 arriving on inputs 301-3 and 301-4 are temporarily stored in RAM 201 to be supplied to outputs 302-1 and 302-2, respectively, in output time slot 2.
  • the arriving packet cells on inputs 301-1 through 301-3 in input time slot 2 are temporarily stored in RAM 201 to be supplied to outputs 302-1 and 302-2 in time slots 3 and 4.
  • packet cell 2 arriving on input 301-1 is supplied to output 302-2 in output time slot 3 and arriving packet cell on input 301-2 is supplied to output 302-2 in output time slot 3.
  • the packet cell 2 arriving on input 301-3 is supplied to output 302-1 in output time slot 4.
  • the packet cells arriving on inputs 301-3 and 301-4 in input time slot 3 are appropriately labeled and are temporarily stored in RAM 201 to be supplied to outputs 302-1 and 302-2 in output time slots 4 and 5.
  • packet cell 3 arriving on input 301-3 is supplied to output 302-2 in output time slot 4 and packet cell 3 arriving on input 301-4 is supplied to output 302-1 in output time slot 5.
  • the arriving packet cells are supplied from inputs 301-1 through 301-4 to outputs 301-1 and 301-2 in the predetermined repetitive sequence, i.e., in a "first-in first-out" (FIFO) basis.
  • FIFO first-in first-out
  • FIG. 4 shows, in simplified block diagram form, an mxm Packet Switch matrix employing a plurality of Packet Switch Units 100, each including Concentrator 101 and Packet Switch Module 102 in accordance with the invention.
  • address filter bank 401 including a plurality of address filters.
  • Inputs 402-1 through 402-32 are supplied via broadcast unit 404 to each group of 32 address filters in address filter bank 401.
  • Address filters 1 to 32 in address filter bank 401 are associated with and supply packet cells from inputs 402 to output Packet Switch Unit 100-1 and, therein, with Concentrator 101.
  • Address filters 33 through 64 in address filter bank 401 are associated with and supply packet cells from inputs 402 to output Packet Switch Unit 100-2.
  • Address filters 65 through 96 in address filter bank 401 are associated with and supply packet cells from inputs 402 to output Packet Switch Unit 100-3.
  • Address filters 97 through 128 in address filter bank 401 are associated with and supply packet cells from inputs 402 to output Packet Switch Unit 100-4.
  • Such address filters employed in address filter bank 401 are known in the art and are employed to interrogate the destination address in arriving packet cells on inputs 402-1 through 402-32 to determine if they are destined for one of the outputs 403 from a Packet Switch Module 102 in the associated one of output Packet Switch Units 100. If so, the packet cell is accepted, otherwise it is discarded immediately.
  • each of output Packet Switch Units 100 only has to process "valid" packet cells destined for their associated ones of outputs 403.
  • outputs 403-1 through 403-8 are associated with output Packet Switch Unit 100-1
  • outputs 403-9 through 403-16 are associated with output Packet Switch Unit 100-2
  • outputs 403-17 through 403-24 are associated with output Packet Switch Unit 100-3
  • outputs 403-25 through 403-32 are associated with output Packet Switch Unit 100-4.
  • FIG. 5 shows, in simplified block diagram form, another possible packet switch arrangement utilizing the principles of the invention.
  • a 64x64 packet switch matrix is shown. It is assumed that a 32x32 Packet Switch Module has already been implemented according to the aforementioned description.
  • a bank of address filters 501 is shown, including address filters 1 through 64 which supply arriving packet cells from inputs 506-1 through 506-64 to Concentrator 502.
  • address filters 65 through 128 in address filter bank 501 supply arriving packet cells from inputs 506-1 through 506-64 to Concentrator 503.
  • Address filters 1 through 128 in address filter bank 501 operate as described above to interrogate the output addresses in the arriving packet cells to determine if they are destined for outputs 507-1 through 507-32 of Packet Switch Module 504 or for outputs 507-33 through 507-64 of Packet Switch Module 505. Again, only those arriving packet cells destined for Packet Switch Module 504 are supplied to Concentrator 502 and only those arriving packet cells destined for Packet Switch Module 505 are supplied to Concentrator 503.
  • each of Concentrators 502 and 503 is a 64:32 concentrator and each operates in a "first-in first-out" manner as described above regarding Concentrator 101.
  • Packet Switch Module 504 is associated with Concentrator 502 and, in this example, is a 32x32 packet switch.
  • Packet Switch Module 505 is associated with Concentrator 503 and also provides a 32x32 packet switch.
  • FIG. 6 shows, in simplified block diagram form, a N:N packet switch matrix based on the principles of the invention by employing a plurality of Nxn output Packet Switch Units 600-1 through 600-K.
  • Each of output Packet Switch Units 600 includes N:n Concentrators 601 and associated nxn Packet Switch Modules 602.
  • Address filter bank 603 includes in this example address filters 1 through KN.
  • a plurality of N address filters in address filter bank 603 is associated with each of output Packet Switch Units 600 and, therein, Concentrator 601. Specifically, address filters 1 through N in address filter bank 603 are associated with output Packet Switch Unit 600-1.
  • a similar plurality of N address filters in address filter bank 603 are associated with Concentrators 601 in each of output Packet Switch Units 600-2 through 600-K.
  • the address filters in address filter bank 603 operate as described above to only supply those packet cells having output addresses destined to the associated output group of Packet Switch Module 602 associated with the particular Concentrator 601, in the associated one of output Packet Switch Units 600, in essentially the same manner as described above.
  • FIG. 7 shows, in simplified block diagram form, a "larger" concentrator arrangement which is implemented by employing a plurality of "smaller” concentrators.
  • a 128:32 concentrator is formed by employing 64:32 Concentrators 702, 703 and 704.
  • input 701-1 through 701-64 are supplied to Concentrator 702 and inputs 701-65 through 701-128 are supplied to Concentrator 703.
  • the 32 outputs from each of Concentrators 702 and 703 are supplied as the 64 inputs to Concentrator 704 which yields outputs 705-1 through 705-32.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
EP92310490A 1991-11-26 1992-11-18 A concentrator-based growable packet switch Withdrawn EP0549122A3 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/797,849 US5256958A (en) 1991-11-26 1991-11-26 Concentrator-based growable packet switch
US797849 1991-11-26

Publications (2)

Publication Number Publication Date
EP0549122A2 true EP0549122A2 (fr) 1993-06-30
EP0549122A3 EP0549122A3 (en) 1995-12-13

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EP92310490A Withdrawn EP0549122A3 (en) 1991-11-26 1992-11-18 A concentrator-based growable packet switch

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US (1) US5256958A (fr)
EP (1) EP0549122A3 (fr)
JP (1) JP2679924B2 (fr)
CA (1) CA2075027C (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2721416A1 (fr) * 1994-06-20 1995-12-22 Met Dispositif d'acheminement de cellules de données à mode de transfert asynchrone.
EP0718997A2 (fr) * 1994-12-22 1996-06-26 AT&T Corp. Concentrateur de données numériques
WO1997012487A2 (fr) * 1995-09-29 1997-04-03 Siemens Aktiengesellschaft Interface pour dispositifs de telecommunications
ES2101636A1 (es) * 1993-09-13 1997-07-01 Ouest Standard Telematique Sa Dispositivo de conmutacion de unidades de protocolo de caudal elevado, y procedimiento de conmutacion correspondiente.
EP0915593A2 (fr) * 1997-11-04 1999-05-12 Nec Corporation Commutateur ATM de type concentrateur pour une système de commutation ATM

Families Citing this family (16)

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US5541914A (en) * 1994-01-19 1996-07-30 Krishnamoorthy; Ashok V. Packet-switched self-routing multistage interconnection network having contention-free fanout, low-loss routing, and fanin buffering to efficiently realize arbitrarily low packet loss
US5412646A (en) * 1994-05-13 1995-05-02 At&T Corp. Asynchronous transfer mode switch architecture
US5493565A (en) * 1994-08-10 1996-02-20 Dsc Communications Corporation Grooming device for streamlining a plurality of input signal lines into a grouped set of output signals
US5687172A (en) * 1994-12-30 1997-11-11 Lucent Technologies Inc. Terabit per second distribution network
US5875190A (en) * 1996-09-27 1999-02-23 Law; Ka Lun Asynchronous transfer mode switching system
JPH10150446A (ja) * 1996-11-19 1998-06-02 Fujitsu Ltd Ａｔｍ交換システム
US6175902B1 (en) * 1997-12-18 2001-01-16 Advanced Micro Devices, Inc. Method and apparatus for maintaining a time order by physical ordering in a memory
US6894972B1 (en) 1999-11-12 2005-05-17 Inmon Corporation Intelligent collaboration across network system
US6667954B1 (en) 2000-02-10 2003-12-23 Tellabs Operations, Inc. Methods and apparatus for selecting the better cell from redundant streams within a cell-oriented environment
US6731645B1 (en) * 2000-02-29 2004-05-04 International Business Machines Corporation Methods, switches, systems, and computer program products for fair transmission of data received at multiple inputs in the order received in a queued memory switch
US7245587B2 (en) * 2000-12-20 2007-07-17 Inmon Corporation Method to associate input and output interfaces with packets read from a mirror port
US6966009B1 (en) 2001-08-28 2005-11-15 Tellabs Operations, Inc. System and method for aligning data in a network environment
WO2003020810A1 (fr) 2001-08-30 2003-03-13 Tellabs Operations, Inc. Systeme et procede de communication de donnees au moyen d'une matrice de commutation habituelle
JP5861371B2 (ja) 2011-10-12 2016-02-16 富士通株式会社 回線切替装置
US9509583B2 (en) 2013-01-24 2016-11-29 InMon Corp. Method for asynchronous calculation of network traffic rates based on randomly sampled packets
US9722926B2 (en) 2014-01-23 2017-08-01 InMon Corp. Method and system of large flow control in communication networks

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EP0256702A2 (fr) * 1986-08-06 1988-02-24 AT&T Corp. Commutateur N fois N à élimination pour un système de commutation par paquets à grande performance
EP0408061A2 (fr) * 1989-07-14 1991-01-16 Hitachi, Ltd. Concentrateur et commutateur de paquets

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EP0256702A2 (fr) * 1986-08-06 1988-02-24 AT&T Corp. Commutateur N fois N à élimination pour un système de commutation par paquets à grande performance
EP0408061A2 (fr) * 1989-07-14 1991-01-16 Hitachi, Ltd. Concentrateur et commutateur de paquets

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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ES2101636A1 (es) * 1993-09-13 1997-07-01 Ouest Standard Telematique Sa Dispositivo de conmutacion de unidades de protocolo de caudal elevado, y procedimiento de conmutacion correspondiente.
FR2721416A1 (fr) * 1994-06-20 1995-12-22 Met Dispositif d'acheminement de cellules de données à mode de transfert asynchrone.
EP0689319A1 (fr) * 1994-06-20 1995-12-27 Fihem Dispositif d'acheminement de cellules de données ATM
US5546393A (en) * 1994-06-20 1996-08-13 M E T Asynchronous transfer mode data cell routing device for a reverse omega network
EP0718997A2 (fr) * 1994-12-22 1996-06-26 AT&T Corp. Concentrateur de données numériques
EP0718997A3 (fr) * 1994-12-22 1999-01-13 AT&T Corp. Concentrateur de données numériques
WO1997012487A2 (fr) * 1995-09-29 1997-04-03 Siemens Aktiengesellschaft Interface pour dispositifs de telecommunications
WO1997012487A3 (fr) * 1995-09-29 2001-09-13 Siemens Ag Interface pour dispositifs de telecommunications
EP0915593A2 (fr) * 1997-11-04 1999-05-12 Nec Corporation Commutateur ATM de type concentrateur pour une système de commutation ATM
EP0915593A3 (fr) * 1997-11-04 1999-07-28 Nec Corporation Commutateur ATM de type concentrateur pour une système de commutation ATM
US6580714B1 (en) 1997-11-04 2003-06-17 Nec Corporation Concentrator type ATM switch for an ATM switching system

Also Published As

Publication number Publication date
JP2679924B2 (ja) 1997-11-19
CA2075027C (fr) 1996-11-12
US5256958A (en) 1993-10-26
EP0549122A3 (en) 1995-12-13
JPH06112977A (ja) 1994-04-22
CA2075027A1 (fr) 1993-05-27

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