EP0536114A1 - Systemes de rendu graphique - Google Patents

Systemes de rendu graphique

Info

Publication number
EP0536114A1
EP0536114A1 EP19900909471 EP90909471A EP0536114A1 EP 0536114 A1 EP0536114 A1 EP 0536114A1 EP 19900909471 EP19900909471 EP 19900909471 EP 90909471 A EP90909471 A EP 90909471A EP 0536114 A1 EP0536114 A1 EP 0536114A1
Authority
EP
European Patent Office
Prior art keywords
framestore
pixel
ordering
instructions
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19900909471
Other languages
German (de)
English (en)
Inventor
Neil Francis 16 Manorgate Road Trevett
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
3Dlabs Ltd
Original Assignee
DuPont Pixel Systems Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by DuPont Pixel Systems Ltd filed Critical DuPont Pixel Systems Ltd
Publication of EP0536114A1 publication Critical patent/EP0536114A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/10—Geometric effects
    • G06T15/40—Hidden part removal

Definitions

  • This invention relates to graphics rendering systems.
  • a simple 2-D graphics rendering system may comprise a graphics processor which receives a stream of rendering instructions from a host computer, and renders the graphical shapes or polygons defined by the instructions one-by-one in a framestore.
  • a video processor reads out the data from the framestore and displays it on a monitor. If it is desired to display, say, a small red triangle on a large green triangle, this can be simply accomplished by supplying the instruction to render the large green triangle before the instruction to render the small red triangle.
  • the large green triangle is rendered in the framestore first, and then when the red triangle is rendered, it partially overwrites the large green triangle, producing the desired effect.
  • Each processor would then be operable to determine, before rendering a polygon, whether that polygon overlaps with any other polygon which has an earlier order code and which is still to be rendered, and if so, the processor would wait until rendering of the polygon with the earlier order code was complete.
  • the processor which is to render the small red triangle would wait until the ot K _;r processor had completed rendering the large green triangle.
  • the present invention aims to overcome the above problem by providing a memory in parallel with the framestore which stores, for each pixel location in the framestore, the order code of the graphical shape or polygon to which the pixel currently rendered at that pixel location belongs.
  • each processor can check whether the order code of the shape it is rendering is later than the stored order code in the memory (in which case it writes that pixel), or not (in which case it does not write that pixel). Accordingly, there is no limitation on the order in which the processors can render the polygons, and the problem of erroneous overwriting is overcome.
  • Figure 1 is a schematic circuit diagram of the rendering system
  • Figure 2 illustrates an example content of the framestore
  • Figure 3 is a flow diagram of the operation of each of the processors of Figure 1 in executing a rendering instruction
  • Figure 4 is a table of steps carried out in rendering a series of instructions to produce the framestore content as shown in Figure 2;
  • Figure 5A to 5C show the contents of the framestore and ordering buffer before the series of instructions is commenced at two occasions part-way through the series of instructions.
  • a host computer HC supplies a set of rendering instructions to an instruction register IR.
  • the instructions take the form of: (i) an opcode representing instructions such as draw a rectangle (represented hereinafter by the mnemonic "rec"); draw a triangle or clear the screen; (ii) parameters associated with the opcode, such as the coordinates of two opposite corners (xl, yl), (x2, y2) of the rectangle, or the coordinates of the vertices (xl, yl), (x2, y2) and (x3, y3) .of the triangle, together with a colour code indicating the colour of, for example, the rectangle or triangle or the colour to which the screen is to be cleared; and (iii) the order of the instruction.
  • an opcode representing instructions such as draw a rectangle (represented hereinafter by the mnemonic "rec"); draw a triangle or clear the screen
  • parameters associated with the opcode such as the coordinates of two opposite corners (xl, y
  • the rendering system further comprises four processors PROC 0 to PROC 3, a framestore F5 with associated output register OR, an ordering buffer OB, a video processor VP and a monitor MON.
  • the processors can read instructions from the instruction register IR asynchronously, so that, for example, processor PROC 0 can read and perform more than one simple instruction, while processor PROC 1 is performing a single more complex instruction.
  • the processors PROC 0 to PROC 3 are each operable to address the framestore FS and the ordering buffer OB with the same address on an address bus AB.
  • the processors PROC 0 to PROC 3 are also each operable to read and write data to the framestore FS and the ordering buffer OB via a pixel data bus PDB and an ordering data bus ODB, respectively.
  • the framestore FS and ordering buffer OB have the same capacity, which is shown in Figure 1 for simplicity as merely 8 x 8 words, and by virtue of the common addressing of the framestore FS and the ordering buffer OB by the address bus AB, each location in the framestore FS is associated with a respective location in the ordering buffer.
  • the output register OR of the framestore FS is loaded row-by-row in parallel with pixel data from the framestore FS, and the pixel data for each row is output serially from the output register OR to the video processor VP for display on the monitor MON.
  • the processors PROC 0 to PROC 3 each perform the sequence of steps shown in Figure 3.
  • an exclusion lock is provided so that only one processor at a time may read an instruction from the instruction register.
  • the processor determines, in a known manner, the location o first pixel to be rendered, such as, in this example, (1, 1).
  • step S3 the processor addresses the ordering buffer OB (and the framestore FS) with the location (x, y), and sets a current order variable CO equal to the order number OB (x, y) at that location.
  • step S4 the processor determines whether the polygon order PO for the polygon of the instruction being processed is greater than the current order CO read from the order buffer OB. If so, then in step S5, the processor writes the polygon colour PC of the instruction being processed to the framestore FS at the addressed location (x, y), and in step 6 writes the polygon order PO of the instruction being processed to the ordering buffer OB at the addressed location (x, y). Thus, the pixel is written, and the ordering buffer OB is updated. Step S7 then follows.
  • step S4 it is determined that the polygon order PO is not greater than the stored current order CO, then steps S5 and S6 are skipped, and accordingly the pixel is not written and the ordering buffer is not updated.
  • an exclusion lock is provided so that only one processor at a time can be addressing the framestore FS and the ordering buffer OB in step S3, S5 or S6. Also, once a processor has addressed the framestore FS and ordering buffer OB in step S3, it places a scan line lock on the framestore and ordering buffer until either it has completed step 56 or it has been determined in step S4 not to write to the framestore and ordering buffer.
  • the scan line lock prevents any other processor accessing a location in the framestore and ordering buffer with the same "y" address, and thus prevents any other processor changing the content of OB (x,y) which has been read by the processor in question at step S3, whilst still enabling the other processors to access addresses with different "y" addresses.
  • the processor determines in a known manner, whether any more pixels need to be rendered to complete the polygon, and if so, the sequence loops back to step S2, where the next pixel is considered. If, however, rendering of the polygon is complete, then the sequence is finished, and the processor is ready to read another instruction from the instruction register IR.
  • a table of example steps performed by the four processors PROC 0 to PROC 3 in carrying out the exemplary instructions "a" to "e” mentioned above is set out in Figure 4, based on the assumption that, initially all of the pixels in the framestore FS are set to white colour, and a zero order number is stored in all of the locations in the ordering buffer OB, as shown in Figure 5A.
  • the table of Figure 4 is self-explanatory. Points to note are that step 12 in the table is the first step where a processor (PROC 3, in this case) compares the order of the polygon it is executing with a current order CO (3) of the pixel (4, 2) under consideration which is not the cleared screen order of zero, because the pixel was previously written in step 11.
  • step 12 the order of the polygon PO is 4, which is greater than the current order of 3, and therefore the pixel is written, as shown in Figures 5B and 5C.
  • step 13 the order of the polygon PO of 1 is not greater than the current order of 4 (produced in step 12), and therefore the pixel is not written in step 13.
  • the processors PROC 1 and PROC 3 have completed rendering their current instructions b and d. Therefore, in step 18, processor PROC 1 commences performing the next instruction "e", and processor PROC 3 falls idle because there are no further instructions to be executed in the simple 5- instruction example which is given above.
  • the system has been described above as having an 8 x 8 word framestore F5 and an 8 x 8 word ordering buffer OB.
  • the framestore FS would have a far greater capacity than this, for example, 2k x 2k words, and the output register OR would correspondingly have a capacity of 2k words.
  • the framestore FS may conveniently be implemented using, for example, a conventional Hitachi video RAM.
  • the ordering buffer OB has a word capacity equal to that of the framestore, and may be implemented by, for example, a conventional Hitachi D-RAM.
  • Each word of the ordering buffer OB may consist of, for example, 16, 24 or 32 bits, which enable 65,535, 16,777,215 or 4,294,967,295 polygons, respectively, to be rendered before any overflow occurs in the ordering buffer.
  • the following procedure may be adopted in the preferred embodiment.
  • the sequence of instructions to the instruction register IR is halted after the instruction having the maximum order number, for example order number 65535 in the 16-bit case.
  • the processors stop rendering.
  • the ordering buffer OB is cleared to zero, and then a further sequence of instructions is supplied to the instruction register, with the first instruction having an order number of 1. Accordingly, the processors recommence rendering, with the new sequence of instructions causing objects to be rendered which overwrite the previous contents of the framestore FS before the temporary halt in execution.
  • any plural number of processors may be employed.
  • increasing significance of the rendering instructions may be denoted by decreasing, rather than increasing order numbers.
  • the framestore FS and ordering buffer OB could be combined into a single device. For example, with a 32-bit framestore, 16 bits could be used to store the pixel data and 16 bits could be used to store the ordering data.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Computer Graphics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Image Generation (AREA)

Abstract

Système de rendu graphique bidimensionnel possédant une pluralité de processeurs (PROC 0 à PROC 3) recevant des instructions à partir d'un registre d'instructions commun (IR) et restituant des polygones dans une mémoire d'images (FS), afin de permettre une mise en oeuvre asynchrone des instructions tout en assurant une bonne restitution des polygones qui se chevauchent. Chaque instruction comprend un code de classement prioritaire et, avant d'introduire un pixel dans la mémoire d'images (FS), chaque processeur vérifie que le code de classement du polygone qu'il restitue est plus significatif qu'un code de classement prioritaire pour le pixel stocké dans un tampon de classement prioritaire. Si tel est le cas, ledit processeur introduit le pixel dans la mémoire d'images (FS) et actualise le tampon de classement prioritaire (OB), sinon le pixel n'est pas introduit.
EP19900909471 1990-06-26 1990-06-26 Systemes de rendu graphique Withdrawn EP0536114A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/GB1990/000987 WO1992000570A1 (fr) 1990-06-26 1990-06-26 Systemes de rendu graphique

Publications (1)

Publication Number Publication Date
EP0536114A1 true EP0536114A1 (fr) 1993-04-14

Family

ID=10669395

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19900909471 Withdrawn EP0536114A1 (fr) 1990-06-26 1990-06-26 Systemes de rendu graphique

Country Status (3)

Country Link
EP (1) EP0536114A1 (fr)
JP (1) JPH06500871A (fr)
WO (1) WO1992000570A1 (fr)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999064990A2 (fr) 1998-06-12 1999-12-16 Intergraph Corporation Systeme permettant de reduire le crenelage sur un dispositif d'affichage
US6476816B1 (en) 1998-07-17 2002-11-05 3Dlabs Inc. Ltd. Multi-processor graphics accelerator
US6480913B1 (en) 1998-07-17 2002-11-12 3Dlabs Inc. Led. Data sequencer with MUX select input for converting input data stream and to specific output data stream using two exclusive-or logic gates and counter
WO2000004527A1 (fr) * 1998-07-17 2000-01-27 Intergraph Corporation Appareil et procede permettant de diriger des donnees graphiques sur un dispositif d'affichage
US6459453B1 (en) 1998-07-17 2002-10-01 3Dlabs Inc. Ltd. System for displaying a television signal on a computer monitor
US6518971B1 (en) 1998-07-17 2003-02-11 3Dlabs Inc. Ltd. Graphics processing system with multiple strip breakers
WO2000004495A1 (fr) * 1998-07-17 2000-01-27 Intergraph Corporation Systeme de traitement de sommets a partir d'une suite de demandes graphiques
WO2000004436A1 (fr) 1998-07-17 2000-01-27 Intergraph Corporation Traitement graphique avec generateur de fonction transcendante
WO2000004484A2 (fr) 1998-07-17 2000-01-27 Intergraph Corporation Processeur graphique a mot instruction long
WO2000004496A1 (fr) 1998-07-17 2000-01-27 Intergraph Corporation Processeur graphique avec systeme d'affectation de memoire de texture
US6410519B1 (en) 1999-03-04 2002-06-25 United States Surgical Corporation Scar reduction
US6674440B1 (en) 1999-04-05 2004-01-06 3Dlabs, Inc., Inc. Ltd. Graphics processor for stereoscopically displaying a graphical image

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4209832A (en) * 1978-06-13 1980-06-24 Chrysler Corporation Computer-generated display for a fire control combat simulator
GB2210540A (en) * 1987-09-30 1989-06-07 Philips Electronic Associated Method of and arrangement for modifying stored data,and method of and arrangement for generating two-dimensional images
US4918626A (en) * 1987-12-09 1990-04-17 Evans & Sutherland Computer Corp. Computer graphics priority system with antialiasing

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9200570A1 *

Also Published As

Publication number Publication date
JPH06500871A (ja) 1994-01-27
WO1992000570A1 (fr) 1992-01-09

Similar Documents

Publication Publication Date Title
US5459835A (en) Graphics rendering systems
US5774133A (en) Computer system with improved pixel processing capabilities
US4967375A (en) Fast architecture for graphics processor
KR100325902B1 (ko) 고성능3차원그래픽가속기를위한부동소숫점처리기및그처리기능수행방법
US5675773A (en) Graphics display system with a low level hardware dependent graphics library
EP0548586A2 (fr) Tampon multiple extensible d'image pour des systèmes graphiques
EP0240246A2 (fr) Appareil et procédé de remplissage de polygones complexes
JPH0683970A (ja) 三角形描画装置及び方法
JPH0683969A (ja) グラフィックス・プロセッサ及びグラフィックス・データ処理方法
JPH03139777A (ja) グラフイツク表示システム及び方法
EP0536114A1 (fr) Systemes de rendu graphique
JPH03241480A (ja) 並列多角形／画素描出用エンジン
US6342883B1 (en) Image display method and image display apparatus
JPH06175646A (ja) グラフィックス・システム用フレーム・バッファおよびラスタ・プロセッサならびにピクセル変数のバッファリング方法
JPH0355832B2 (fr)
EP0887768A2 (fr) Processeur graphique et méthode de traitement graphique
US5946005A (en) Computer graphics memory architecture having a graphics processor and a buffer
JPH0714029A (ja) 線描画装置及び方法
CA2055784C (fr) Controleur de memoire hierarchique
KR19990008388A (ko) 연산기능을 갖는 반도체메모리 및 그것을 사용한 처리장치
JPH0651937A (ja) データ処理システム及びデータ制御方法
CA2085588A1 (fr) Systemes de restitution graphiques
JP2899838B2 (ja) 記憶装置
US6489967B1 (en) Image formation apparatus and image formation method
JPS6334658A (ja) 画像処理用ｄｍａコントロ−ラ

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 19930125

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FR GB IT LI LU NL SE

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 19940104