EP0515519A1 - Appareil a interconnexion de reseaux - Google Patents

Appareil a interconnexion de reseaux

Info

Publication number
EP0515519A1
EP0515519A1 EP19910904842 EP91904842A EP0515519A1 EP 0515519 A1 EP0515519 A1 EP 0515519A1 EP 19910904842 EP19910904842 EP 19910904842 EP 91904842 A EP91904842 A EP 91904842A EP 0515519 A1 EP0515519 A1 EP 0515519A1
Authority
EP
European Patent Office
Prior art keywords
segments
segment
network
control signal
detecting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19910904842
Other languages
German (de)
English (en)
Inventor
David Pritty
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Strathclyde
Original Assignee
University of Strathclyde
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of Strathclyde filed Critical University of Strathclyde
Publication of EP0515519A1 publication Critical patent/EP0515519A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/46—Interconnection of networks

Definitions

  • the present invention relates to a method of providing a discretionary connection between segments of a network.
  • the invention also relates to apparatus for allowing independent operation of se ents when disconnected, or allowing operation of a common access protocol over the segments when they are connected.
  • t! invention relates to the field of Local Area Netwoxks (LANs) which are based on the use of the bus topology.
  • the invention has particular application in the following areas of providing an improved method of supporting different classes (priorities) of traffic over a shared communication medium, and providing integrity, eg to allow one (or more) segment(s) to continue to operate when failures occur on one (or more) other segments(s) .
  • TDM time division multiplexing
  • the network access mechanisms can include prioritisation features, for example the IEEE 802.5 token ring and the IEEE 802.4 token bus mechanisms.
  • prioritisation features for example the IEEE 802.5 token ring and the IEEE 802.4 token bus mechanisms.
  • the point to point i.e. station to station nature of the communication paths in the ring topology allow for implementation of efficient prioritisation mechanisms this is not the case for the bus topology where the broadcast nature of the bus limits the efficiency of prioritisation mechanisms such as those used in the case of the IEEE 802.4 token bus which are based on token rotation timers.
  • token rotation timers One particular limitation of prioritisation mechanisms based on token rotation timers is the need to match the timer values to the loads imposed by different priorities (classes) of traffic.
  • a bridge or gateway is connected to both networks with one side of the bridge or gateway acting as a node on one network and the other side acting as a node on the other network. Both networks run their own access protocols independently and thus, in the case of a gateway one side can run one protocol (eg token passing) and the other side runs another protocol (eg CSMA/CD) .
  • one protocol eg token passing
  • CSMA/CD another protocol
  • the higher priority access mechanism can be implemented over a logically separate control channel, the priority interrupt control channel (PICC) as disclosed in UK Patent No. 2187917B and in another described system a more efficient method of prioritised deterministic bus access (eg than token passing) which operates over the bus (without the need for a separate channel) and is the aforementioned Timed Bus Access Method, can conveniently be used.
  • PICC priority interrupt control channel
  • the operation of the Timed Bus Access Method for both prioritised and non prioritised operation for the case of linear bus, a tree and a hub star is disclosed in WO 90/09068.
  • each separate network requires the installation of its own separate media each incurring its own installation cost, ie twisted pair, coaxial cable or fibre optics to handle the traffic from nodes of different priorities even although the nodes of the different priorities are so physically located that it would be convenient to connect them all to the same medium.
  • bridges or gateways must be provided in order to provide communications between the networks so that messages (packets) can be passed from one network to the other through the bridge or gateway. This involves processing delays in passing the messages in addition to the delays caused by the network access mechanisms.
  • An object of the present invention is to obviate or mitigate at least one of the aforementioned disadvantages.
  • Another object of the invention is to provide a discretionary connection between different segments of a network.
  • Another object of this invention is to mitigate the costs associated with the installation of the separate network cables and bridges and gateways connecting separate networks and to allow immediate access to a shared communication medium supporting different traffic priorities.
  • a further object of the invention is to reduce the overall cost of a system having a single communications medium but requiring multiple IAUs by obviating the need for multiple IAUs on certain parts (or segments) of the overall shared communications medium.
  • a yet further object of the invention is to allow different access mechanisms to be time division multiplexed (ie used at different times) on the same shared medium (eg CSMA/CD) and token passing to be used or CSMA/CD and the timed Bus Access method to be used as described in WO 90/09068.
  • shared medium eg CSMA/CD
  • token passing to be used or CSMA/CD
  • timed Bus Access method to be used as described in WO 90/09068.
  • the solution provides a performance advantage in that higher priority traffic can use a (prioritised) deterministic method of access and lower priority traffic a non deterministic method of access.
  • network interconnection apparatus for connecting at least two segments of a network for allowing independent operation of the segments when disconnected, or providing sufficiently close physical coupling to allow operation of a common access protocol over the segments when they are connected, said apparatus comprising:- a) first and second interface means for connecting the apparatus to a first and a second network segment, and for converting signalling standards of said segments into digital logic levels, b) bidirectional switch means connected between said interface means for connecting and disconnecting said first and said second network segments in response to a control signal from at least one of said segments; c) digital signal processing means coupled to said first interface means and to said bidirectional switch means, said digital signal processing means comprising first detecting means for detecting said control signal from a segment and for generating a first switch control signal to said bidirectional switch means to disconnect said first and said second network segments, and second detecting means for detecting the end of said segment control signal for generating a second switch control signal to said bidirectional switch means to connect said first and second segments.
  • said first network segment is a high priority segment and said second network segment is a low priority segment, said first and said second interface means being coupled to said high and low priority segments respectively, said bidirectional switch means connecting and disconnecting said high and low priority segments in response to a control signal which is a demand from said high priority node to transmit in the high priority segment, said first detecting means detecting when said high priority node desires to transmit, and said first detecting means generating said first switch control signal to said bidirectional switch means to disconnect said high and low priority segments, and said second detecting means detecting the end of said high priority activities and generating the second switch control signal to said bidirectional switch.
  • said apparatus includes low priority node transmission prevention means for preventing said low priority nodes from transmitting during the transmission of a message from a higher priority node.
  • this is achieved by incorporating a dummy carrier generator within said apparatus for generating a dummy carrier (data) signal to said low priority segment when said segments are disconnected by said bidirectional switch means.
  • a uniquely distinguished signal pattern generated by one or more of the high priority nodes is used to inform the apparatus to disconnect the high and low priority segments.
  • the digital logic levels are TTL logic levels.
  • the segments use Ethernet cabling and signal standards and can use Ethernet transceiver and access unit integrated circuits.
  • the apparatus is used to interconnect a high priority segment selected from a suitable number of bus structures which are capable of supporting a random access protocol, such bus structures being in the group of a bidirectional linear bus, a unidirectional linear (folded) bus, a tree or a hub (star) and the low priority segment can be selected from the same group of bus structures.
  • One high priority segment may be connected to a multiplicity of low priority segments which may be the same or different types, using multiple interconnection devices.
  • Fig. 1 is a block diagram of a low priority and high priority segment physically connected by a network interconnection unit in accordance with an embodiment of the invention
  • Fig. 2 is a schematic block diagram of the network interconnection unit shown in Fig. 1;
  • Figs. 3a to 3g are waveform timing diagrams of signals used to control the operation of the network interconnection unit
  • Fig. 4 depicts an alternative network arrangement in which one high priority segment is connected to several low priority segments of different types
  • Fig. 5 depicts an alternative network arrangement with a unidirectional bus high priority segment connected to two low priority segments by two network connection units, and
  • Fig. 6 is a schematic block of an arrangement of a network interconnection suitable for use in application where it is desirable to maximise the overall integrity of the network.
  • FIG. 1 of the drawings depicts a low priority network serial bus segment 10 connected to a higher priority network serial bus segment 12 via a network interconnection unit (NCU) 14 such that a single serial bus 15 is effectively formed at the physical level when segments 10,12 are connected.
  • NCU network interconnection unit
  • NRT non real-time
  • RT nodes 16 are coupled to the low priority segment 10 although only two are shown in the interests of clarity.
  • the NRT nodes employ only a random access protocol (eg CSMA/CD) to access the network.
  • a plurality of real-time (RT) nodes 18 and NRT nodes 20 can be coupled to the high priority segment 12 although only one of each type are shown in -li ⁇
  • each NRT node 20 is coupled to the segment 12, through an interface access unit (IAU) 22.
  • IAU interface access unit
  • the NCU 14 selectively connects and disconnects the low priority segment 10 and high priority segment 12 in accordancewith a demand from a high priority RT node 18 to access the network (shared communication medium) as will be later described in detail.
  • Fig. 2 of the drawings is a block diagram of the NCU 14 coupled to the segments 10,12 forming the serial bus 15 which, in this embodiment, uses Ethernet signalling standards.
  • the NCU 14 is connected to the serial bus segments 10,12 by Ethernet transceivers (not shown in the interests of clarity) and two Serial Interface Adapter Chips 24,26 (Advanced Micro Devices (AMD, type 7992B) .
  • Ethernet transceivers not shown in the interests of clarity
  • AMD Advanced Micro Devices
  • the SIA chips which are driven by a common (20Mhz) clock input, convert the signalling standards on each of the segments 10,12 respectively to TTL digital logic levels.
  • each SIA extracts separate clock (RCLK) and serial data signals (RX) and a receive enable signal (RENA) from the signal on the bus and on the transmission side each SIA provides a transmit clock (TCLK) which acts as a timing reference for transmit data signals (TX) presented to the SIAs.
  • a transmit enable input (TENA) is used which when set high enables the SIA's to encode these transmitted signals and convert them to the bus signalling standards, all as is well known in the art.
  • the SIA circuits 24,26 are each connected to a TTL logic circuit 28 which includes a bidirectional changeover switch implemented using a multiplexer 30, a FIFO storage register 32 and an output clock delay buffer 34, and gates 42, 44 and 46 which control the switch data flow as will be described.
  • the switch when closed, takes data received from the low priority segment 10 and transmits it to the high priority segment 12 or vice versa.
  • the logic circuit 28 includes an elasticity storage buffer consisting of the FIFO 30 and the clock delay buffer 34 to cater for the variations in data rate which can occur between the two segments of the network.
  • the logic circuit 28 also includes 3-state gating means (42) to allow it to pass a jamburst of dummy data, generated by dumming data generator circuit 38, to be passed both to the segment on which the collision occurred and to the other segment.
  • the timing of the jam burst is controlled by the Jamburst timer 40 (which is triggered by control logic 36) , and which uses the TENA signals on the SIAs 26 and 28 to control the length of the jam burst.
  • a dummy data signal produced by the dummy data (carrier) generator 38, can be passed through gate 42 onto the lower priority segment 10.
  • TTL digital logic disconnect/connect control logic circuit generally indicated by reference numeral 36 as will be described. It will be appreciated that because the signals to be connected/disconnected consist of TTL level "Is" and "Os" the logic circuits 34, 38 and 40 can be realised using standard logic circuit elements such as AND, C*? , NOT and three(3)-state gates and Flip-Flops and shift register and counter circuits.
  • the operation of the bidirectional switch 28 will now be decribed in more detail with reference to Figure 2.
  • the TCLK inputs from the SIA's 24 and 26 are fed to the B4 and A4 inputs respectively.
  • the select input (A/B) of the multiplexer is set to accept one set of signals or the other by the switch control circuit 36.
  • the selected RX data and receive enable RENA outputs from the multiplexer 30, are then clocked by the selected receive clock RCLK into the (input) memory of a two data channel first-in-first-out (FIFO) 32 which acts as an elasticity buffer.
  • the selected receive clock (RCLK) clocks the selected received data (RX) into the first channel of the (input) memory of the FIFO 32 and receive enable (RENA) into the second channel.
  • the first channel of the (output) memory 32 which is unloaded using the oppositely selected TCLK, is the transmit data output TX and the second channel is used as the transmit enable signal TENA which is passed to both SIA's 24,26.
  • the TENA signals applied to the SIA's 24,26 are passed through gates 44,46 controlled by the control logic 36 so that only one TENA is asserted, and thus only one SIA passes an encoded T x signal to the bus.
  • the output clock delay buffer 34 is provided, which can conveniently be realised using a shift register equipped with suitable logic gating (not shown in the interest of clarity) .
  • the shift register provides a delay between the time a packet arrives to be clocked into the FIFO 32 indicated by RENA going high at the input to the shift register and the time this event is propagated down the shift register to provide a "1" signal at its output.
  • the delay buffer 34 allows an appropriate number of received data bits to be clocked into the FIFO 32 before output clocking begins. This mechanism allows for faster unloading than loading of the FIFO 32 for the period of a maximum length data packet.
  • FIFOs such as the AMD 67C4013 supported by time synchronising D flip-flops
  • FIFOs which are constructed from dual ported RAM with separate input and output clocks are more suitable for this application since they have much shorter fall through times than those FIFOs constructed from shift registers.
  • Three state gates 42 are provided on the output of the FIFO 32 and the dummy data generator 38 to allow either the FIFO 32 or the dummy data generator output 38 to feed the TX inputs of the SIAs 24,26 under the control of the Control Logic circuit 36.
  • the control logic circuit 36 is activated by a real-time (RT) request detect circuit 48 constructed using logic gates, shift register and counter elements and de-activated by end of real time (RT) activity detect circuit 49 both of which input signals to the control logic circuit 36.
  • the RT request detect circuit 48 detects RT request signals from the high priority segment 12 which indicate that a high priority node eg node 18, wishes to transmit.
  • Circuit 49 detects the end of high priority activity, that is, once all queued RT messages have been transmitted eg by detecting a period of silence on bus segment 12.
  • the low priority segment 10 is connected to the higher priority segment 12 through the signal standards conversion circuits 24,26 and the bidirectional digital switch 28. It is an essential feature of the NCU 14 that it provides sufficiently close physical layer coupling of the two segments 10,12 to allow one access protocol to operate at the physical level over both segments virtually simultaneously (eg CSMA/CD) .
  • a high priority RT node 18 When a high priority RT node 18 wishes to access the network for transfer of a high priority message it first listens for silence on the network which occurs at the end of a low priority packet 50 as seen in Fig. 3a. The high priority RT node 18 then issues an RT request signal 52 as shown in Fig. 3b.
  • this signal can be an extended collision signal or a signal containing a special pattern in the first few bits.
  • the RT Request signal lasts continuously for a sufficient time to be identified unambiguously by request circuit 48 (rather than by issuing a jamburst and backing off) .
  • This signal is transmitted over the high priority segment 12 where it is detected by the high priority detect circuit (not shown in the interests of clarity) in the IAUs 22. It is also detected (almost simultaneously) by the RT request detection circuitry 48 in NCU 14.
  • the IAUs 22 detect the RT request signal after a time 53, and then inject a dummy data signal 54 into the connected NRT node 20 shown in Fig. 3c and set the RT request detect output signal in the IAU 22 causing any connected NRT nodes 20 which may have just started transmission to back-off. It will be understood that two or more RT nodes 18 can transmit RT request signals 52 more or less simultaneously and this will also activate the circuitry as described above.
  • RT request detect circuitry 48 in the NCU 14 detects the RT request signal, it then instructs the control logic circuit 36 to generate a control signal 56 shown in Fig. 3d to the bidirectional switch 28 to cause the switch to operate so that the two segments 10,12 of the network are now disconnected from each other and so that the output of the dummy carrier transmission circuit 38 is connected to the lower priority segment 10 thus allowing the transmission of a dummy carrier signal 58 onto the low priority segment as shown in Fig. 3e.
  • This sequence of operation leaves the high priority segments silent so that high priority packets 51 (only one of which is shown) can be transmitted over the high priority segment 12 under the control of the high priority access protocol.
  • the network interconnection apparatus may conveniently include gateway functions such as packet reception and transmission components and associated microcomputer components to allow the network interconnection apparatus to hold packets addressed to nodes in the higher priority segment for onward transmission to that segment when the high priority activity has terminated.
  • This high priority method is based on the timed bus access method whose operation over bidirectional linear bus is described in the published PCT Application No. WO 90/09068.
  • the polling node issues a slot pulse 60 as shown in Fig. 3f and RT nodes 18 access the bus under the control of the timed bus access method. Once the queue of messages from the RT nodes has been serviced no response will be received either to the first slot pulse 62 or the second slot pulse 64, which also acts as a cycle start pulse as shown in Fig. 3g.
  • the high priority activity detection circuitry (not shown in the interests of clarity) in the IAUs 22 connected to the NRT nodes 20 and in the NCU 14 detects the absence of a response to the slot pulse within a predetermined period 66. This causes the IAUs to cease to transmit the dummy data signal 54 as shown in Fig. 3c.
  • the end of RT activity circuit 59 in the NCU 14 also detects that the predetermined period 56 has elapsed and activates the control logic 36 to reconnect the two network segments 10,12 and disconnect the dummy carrier transmitter 38 from the lower priority part as described above.
  • the network then resumes normal low priority (CSMA/CD) operation.
  • the cycle is repeated each time a high priority node wishes to send a message.
  • the high priority segment 12 can be selected from one of a set of suitable bus structures which can support a random access protocol such as CSMA/CD or, more suitably, a prioritised deterministic access protocol such as token passing or the timed bus access method.
  • the set of suitable structures includes a bidirectional linear bus a unidirectional linear (folded) bus, a tree or a hub (star) .
  • the low priority segment 10 can also be selected from the same set of bus structures.
  • one high priority segment can be connected to a multiplicity of low priority segments and that these low priority segments may be of different types.
  • the high priority segment 70 is a bus (or tree) with a plurality of NCUs 72 attached, although only three are shown in the interests of clarity.
  • a plurality of high priority NRT nodes 74 (only one shown) and low priority nodes 76 (each connected to the high priority segment 70 through an associated IAU 78) can be attached although one example of a high priority node and one example of a low priority node is shown in the interests of clarity.
  • each NCU 72 To each NCU 72 is attached respective single segments 73, 75 and 77 containing only NRT nodes.
  • One segment 73 is a bidirectional tree structure
  • another segment 75 is a hub (star)
  • a third structure 77 is a unidirectional bus with unidirectional NRT nodes 78 attached.
  • a high priority node 74 When a high priority node 74 has a message it conveniently transmits an RT request detect signal to the IAUs 78 and NCU's 72. Each NCU then operates as described above for the case where a single NCU is attached to the high priority segment.
  • Figure 5 shows an arrangement with a unidirectional bus high priority segment 80. This is connected to a plurality of NCU's 82 which are configured to operate on a unidirectional bus, although only two are shown in the interests of clarity. A plurality of high priority nodes 84 and low priority nodes 86, each with associated IAU 88 (also configured to operate on a unidirectional bus) can be connected to the high priority segment 80, although only one of each type of node is shown in the interests of clarity. Each of the NCU's 82 is connected to a low priority NRT segment 90.
  • Control logic module 130 also contains a dummy data generator and jam burst generators (omitted for the sake of clairity) .
  • the NCU 114 is equipped with segment failure detecting means 116 for detecting failure or node misbehaviour in the connected segments. Failures which can be detected include jabbering transmissions, an excessive number of runt or oversize packets, badly formatted packets or errors in packet checksums and an excessive number of collisions (in the case of a CSMA/CD protocol) .
  • the segment failure detecting means 116 is realised using hardwired and processor based logic and packet formatting chips appropriate to the protocol as is well known in the art (such as the AMD 7990 LANCE for Ethernet) .
  • the failure detection means 116 Upon detection of a failure, the failure detection means 116 outputs a disconnect signal to the control logic module 130, which activates the bidirectional switch 128 to disconnect the two segments 110 and 112. Depending on the configuration of the failure detection means 116 the segments 110 and 112 are either reconnected automatically or by human intervention once the fault has been cleared.
  • the invention may also have application in other areas; for example, to provide data security, that is, to prevent unauthorised access to information on one (or more) segment(s) ; to cope with overload, eg during periods of high activity, and to provide a spanning tree bridge to link networks together.
  • segment means any part of a single shared communication medium which can use a single access medium to control transmission, over the shared medium, from a number of active stations. Therefore a segment can consist of a network involving a number of cables or fibre optic connectors interconnected by repeaters.
  • the control circuit 36 can be implemented using a microprocessor-based system instead of hard-wired logic and. the TTL logic components can be replaced by components using different logic, e.g. NMOS, PMOS and CMOS and optical logic. Operation of the system is as described above and in the attached document for prioritised operation of the timed bus access method.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer And Data Communications (AREA)
  • Small-Scale Networks (AREA)

Abstract

Un appareil à interconnexion de réseaux (14), particulièrement adapté aux réseaux locaux à base de bus, est décrit. Cet appareil permet aux segments de réseaux (10, 12) de fonctionner indépendamment lorsqu'ils sont déconnectés, ou permet le fonctionnement d'un protocole commun d'accès sur les segments (10, 12) lorsqu'ils sont connectés. L'appareil (14) comprend des première et seconde interfaces (24, 26) qui le connectent aux segments (10, 12) et un commutateur bi-directionnel (30, 32, 34) connecté entre les interfaces (24, 26), répondant à un signal de commande provenant de l'un des segments (10, 12) pour connecter et déconnecter les segments (10, 12). L'invention peut servir particulièrement à soutenir différentes priorités de circulation sur un support de communication partagé et à procurer l'intégrité, c'est-à-dire, à permettre à un ou plusieurs segments de fonctionner lorsque des défaillances ont lieu dans un ou plusieurs segments. Un mode de réalisation de chacune de ces applications est décrit.
EP19910904842 1990-02-21 1991-02-21 Appareil a interconnexion de reseaux Withdrawn EP0515519A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB909003880A GB9003880D0 (en) 1990-02-21 1990-02-21 Network interconnection apparatus
GB9003880 1990-02-21

Publications (1)

Publication Number Publication Date
EP0515519A1 true EP0515519A1 (fr) 1992-12-02

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WO (1) WO1991013504A1 (fr)

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DE4426094C2 (de) * 1994-07-22 1998-04-16 Siemens Nixdorf Inf Syst Datenreduktion für Buskoppler
SE9902577L (sv) * 1999-07-06 2000-10-30 Daimler Chrysler Ag Kommunikations- och styrsystem med flera segment för rälsbundna fordon
DE10026124A1 (de) 2000-05-26 2001-11-29 Bayerische Motoren Werke Ag Schaltungsanordnung für ein Kraftfahrzeug
DE10028830A1 (de) * 2000-06-10 2001-12-13 Merten Gmbh & Co Kg Einrichtung für ein Datenleitungsnetz zum Anschluß eines Gerätes

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JPS5875351A (ja) * 1981-10-30 1983-05-07 Fuji Xerox Co Ltd デイジタル信号中継方式
US4617423A (en) * 1984-09-04 1986-10-14 Agile Systems Data communication system
JP2660422B2 (ja) * 1988-05-31 1997-10-08 株式会社日立製作所 動作モード設定可能なｌａｎ間結合装置

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WO1991013504A1 (fr) 1991-09-05
GB9003880D0 (en) 1990-04-18

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