Classifications

• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/2007—Display of intermediate tones
  • G09G3/2011—Display of intermediate tones by amplitude modulation
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
  • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
  • G09G3/3611—Control of matrices with row and column drivers
  • G09G3/3685—Details of drivers for data electrodes
  • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2310/00—Command of the display device
  • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
  • G09G2310/0243—Details of the generation of driving signals
  • G09G2310/0259—Details of the generation of driving signals with use of an analog or digital ramp generator in the column driver or in the pixel circuit
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2310/00—Command of the display device
  • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
  • G09G2310/0264—Details of driving circuits
  • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters

Definitions

• Variable pulse width generator including time vernier
• 25 bits only need to be at 1.25 MHz, i.e. the reverse of 50/64 ⁇ s.
• amorphous silicon (aSi) is inexpensive compared to polycrystalline silicon, it is desirable to use aSI for a liquid crystal display for
• H. REPLACEMENT LEAD approximately 5MHz is necessary to be able to process the 256 levels of gray (8 bits) brought into play by television with TSC standards.
• the capacity of each line of the liquid crystal display, which constitutes the charge of each stage of the line scanner is very large and requires a relatively powerful transistor to fully charge the selected line for the short relative time. (not exceeding 13 ⁇ s) of non-activity of each horizontal line video signal.
• amorphous silicon transistors normally prevents such transistors from being used in a line selection scanner in a high definition liquid crystal display (e.g. a television screen). 'around 250,000 pixels per image).
• the present invention relates to logic circuits which overcome one or more of the problems just discussed. While these logic circuits differ from each other in detail, they all include interconnected boot stages arranged in numerical order P (where P is an integer), each stage comprising a node charge transistor having a charge of capacitance in series, intended, in addition, to direct the charge current of a synchronization pulse applied to the capacitance charge at a node by passing said transistor which charges the node when this transistor charging the node of this stage is open .
• the transistor which charges the node of each stage has significant capacities distributed between its gate and its source, as well as between its gate and its drain.
• the first measure is to selectively apply a priming pulse
• the first measurement also keeps the transistor, which charges the node of each of the stages closed.
• the second measure consists first of all (1) in applying the first synchronization pulses which occur in the first phase of a predetermined set of different phases to the load capacity of one or more given stages of the interconnected stages and (2 ) applying the second synchronization pulses which occur in a second phase of a predetermined set of different phases to the load capacity of one or more stages of the interconnected stages other than the given stages.
• Preloading a gate of a transistor intended to charge an activated node decreases its response time when applying a synchronization pulse and thus improves the maximum speed at which the pulse logic circuit can operate, despite the large distributed capacities which exist respectively between the gate and the source, as well as between the gate and the drain of the transistor intended to charge the node of each stage.
• FIG. 1 shows a system, comprising a time vernier circuit, rapidly responding to digital gray level data to control the duration of application of a ramp-shaped voltage signal to a data line of a display liquid crystal display, comprising M columns and N rows, in accordance with the gray scale data.
• FIG. 2 shows an output pulse from the vernier of FIG. 1 and the voltage signal in the form of a ramp during each 63 ⁇ s interval of the column.
• FIG. 3 represents a schematic view of a single-input device of the time vernier circuit of FIG. 1, comprising 4 stages with different phases.
• Figure 4 shows the data inputs to the 4 stages of what is described in Figure 3.
• Figure 5 is a synchronization diagram of the vernier and the final phase of the comparator as shown in Figure 1
• FIG. 6 represents an equivalent circuit of part of the time vernier circuit of FIG. 1.
• FIG. 7 represents the voltages as a function of time at different points of the equivalent circuit of FIG. 5 according to the first operating conditions.
• FIG. 8 represents the voltages as a function of time at different points of the equivalent circuit of FIG. 5 according to the second operating conditions.
• Figure 9 gives a schematic representation of a device with two inputs to the time vernier circuit of Figure 1, consisting of 4 stages with different phases.
• Figure 10 shows the data inputs to the 4 stages of the device presented in Figure 9.
• Figure 11 gives a schematic representation of a single input device of the time vernier circuit of Figure 1, comprising 8 stages with different phases.
• FIG. 12 shows the data inputs applied to the 4 stages of the device relating to the time vernier circuit presented in FIG. 9.
• FIG. 13 gives a schematic representation of a device with two inputs of the time vernier circuit of FIG. 1, comprising 8 stages with different phases.
• Figure 14 shows the data inputs applied to the 8 stages of the device presented in Figure 9.
• the time vernier circuit 100 receives data from control inputs of the comparator or counter circuits connected in cascade 101-1 to 101-P and provides an output pulse Mo which is individually associated, by the pixel column control transistor 102, with column J of the liquid crystal display comprising columns M and lines N. Additional time vernier circuits , similar to the time vernier circuit 100, are individually associated, by means of the pixel column control transistors 102, with each of the columns J to J + M. Comparators 101-1 to 101-P receive the data bits and provide an output pulse having a width determined by the most significant bit (MSB for "Most Significant Bit" in English).
• MSB most significant bit
• the two least significant bits are applied to the vernier circuit 100, which divides the last period into any of the 4 intervals.
• a ramp-shaped voltage signal ( v R ar >) shown in FIG. 2 is applied to the respective drains of the transistors 102 of the pixel control lines, transistors associated with all of the columns J.
• the liquid crystal pixels P (eg P jç ⁇ and p k + li • * 'Q- 44 - constitute capacitors, are located at the intersection of each row and each column.
• a row scanning device (shown in the patent, of Gillette et al. mentioned above) makes all the transistors 103 associated with the selected igneous conductor (eg, the transistors 103-1 to 103-2 associated with the line K).
• the voltage V Ramp to charge all the pixels P (for example, P k ⁇ and ⁇ + ⁇ j ) associated with the transistor passing control of the column 102 and the line K of activated.
• the voltage V Ramp occupies an active phase of each horizontal scanning period of 63 ⁇ s of the video signal.
• the line scanning device passes from one line to the next, as from line K to line K + 1.
• the level of V Ramp is at the beginning of the active phase.
• FIG. 2 also shows how the number of possible widths of the output pulse can be modified by the comparator circuits 101-1 to 101-P and the vernier circuit 100. The number of possible pulse widths is determined by the particular device of the comparator 101 of the vernier circuit 100 used as explained below.
• each pixel column control transistor 102 must load a complete line of data, which has a high capacity and therefore a power transistor is necessary.
• the pixel column control transistor 102 which is preferably a thin film type (TFT) field effect transistor (FET)
• TFT thin film type field effect transistor
• FET field effect transistor
• the switching time required for the pixel line control transistor 102 must be shorter.
• the implementation of the present invention in the time vernier circuit 100 makes it possible to switch the pixel column control transistor 102 fast enough for liquid crystal display operations, even when at the same time the transistor 102 for controlling the pixel column and the transistors used by the time vernier circuit 100 are all made of materials with low mobility such as amorphous silicon.
• FIG. 3 shows a time vernier circuit 100 for switching the pixel column control transistor 102 at a time determined by the control inputs applied to it.
• These control inputs include a signal precharge voltage 0 pc which is simultaneously applied to the gates of TFT 104 to TFT-A 104- E, and binary data inputs DV, D1V, D2V and D2V, which are applied to circuit time vernier 100 during the inactive phase of each horizontal line scan.
• the control inputs also include an arming pulse Mi which is the output pulse Mo of the comparator circuit 101-P.
• the 4 phase synchronization pulses 0Av , 0Bv , 0Cv , 0Dv are applied through capacitors 105A to 105D, respectively to the drains of the TFT thin film transistors 106A to 106D.
• the arming pulse Mi is applied to the gate of the arming thin film transistor (TFT) 107, the drain of which is connected to node A and the source of which is grounded.
• the node A is also connected to the gate of a falling TFT 108, the source / drain connection of which transmits the output pulse Mo to the gate of the column control TFT 102.
• the connections between the source and the drain of the pairs of TFT 109-1 and 109-2 to 109-7 and 109-8 are respectively connected between the sources of TFT 104A to 104-D and the ground. TFT 110A to 110D locked
• PLACEMENT are connected to each of the capacitors 105A to 105D to prevent the capacitors from charging a value greater than + V C.
• the source of TFT 108 is biased towards a slightly positive voltage + VB (eg +2 volts) which. can be useful in order to prevent the TFT from responding to parasitic voltages at its gate.
• time vernier circuit 100 uses one or two of the least significant bits (LSB) in order to extend the possible pulse widths to 256.
• the fact that one or two of the least significant bits (LSB) is (are) used in the time vernier 100 is determined by the configuration of the comparators 101-1 to 101-P.
• the application referenced RCA 85,678 in its figure 4 shows a comparator which provides a single output pulse Mo (input Mi towards the vernier). With this type of comparator, only a least significant bit is used by the vernier circuit 100 and the data pulse of the most significant bit (D1V) of the vernier pulses is provided by the regeneration of the pulse (of the bit ) least significant of the comparator data signal. This is the type of operation used by the comparator 100 in Figure 3.
• Figure 6 of the mentioned application RCA 85,678 shows a comparator which gives two output pulses
• FIG. 4 shows the combinations of the pulses D1V, D1V, D2V and D2V which are applied to the gates of the thin film transistors (TFT) 109-1 to TFT 109-8 of the
• the pulses D1V and D1V are the same as the data pulses of the least significant bit supplied to the stage of the comparator 101-P (FIG. 1).
• the pulses D2V and D2V are the data pulses 5 for the vernier circuit 100.
• the vernier circuit 100 has 4 identical interconnected stages 100-A, 100-B, 100-C and 100-D.
• Stage 100-A consists of a thin film transistor 106-A having: (1) its gate connected to the
• drains of all transistors from 104-A to 104-D are all connected to a point of operating potential (eg +15 volts) and the sources of all transistors 109-1 to 109-8 are
• the precharge voltage pulse 0 C is applied to the gates of all the transistors, from transistor 104A to transistor 104E.
• the combinations of data inputs D1V, D1V, D2V and D2V applied to the gates of transistors 109-1 to 109-8 determine the width
• TFT thin film transistors
• stages 100-A to 100-D are small low power transistors having channel widths of only 10 to 15 micrometers ( ⁇ m) approximately, the transistor 106 of each stage is a larger and higher power transistor having a channel width of approximately 100 ⁇ m.
• 35 transistors 107 and 108 of each stage are even larger and more powerful transistors having channel widths of around 200 ⁇ m and the pixel column control transistor 102 is a
• REPLACEMENT SHEET much larger transistor and much higher power with a channel width of about 750 microns.
• FIG. 6 shows the equivalent circuit for stages 100A to 100D of Figure 3.
• the distributed capacity C 1 is significantly smaller than the distributed capacities C 2 and C3, the distributed capacities C 2 and C3 are significantly smaller than the capacities distributed C 4, c 5 e ⁇ - ⁇ 6 ' ⁇ and "es ca P ac ities spread C 4, C 5 and Cg are substantially smaller than the distributed capacitance C Q.
• the operation of the time vernier circuit 100 of FIG. 3 is described with the aid of FIG. 2, the synchronization diagram of FIG. 5, the equivalent circuit of FIG. 6, and diagrams 7 and 8 representing the diagrams of voltage as a function of time.
• the Mi arming pulse remains high (+15 volts) from approximately the start of each horizontal scan line of 63 ⁇ s until the occurrence of the time selected by the 2 least significant bits of the scale of grayscale to stop the power supply to the pixel column control transistor 102.
• the arming pulse Mi is large, the transistor 107 is made active.
• the precharge voltage pulse p C and the data inputs D1V, D1V, D2V and D2V are applied. With transistor 107 open, node A and the gate of transistor 108 are connected to ground, which closes transistor 108.
• the precharge voltage pulse p C applied to the gate of the thin film transistor 104 opens the transistor, and the gate of the transistor 102 of control of the column of pixels is loaded at + 15 volts, in order to make the transistor 102 of control of the column of pixels passing.
• the voltage V Ramp is then applied to the pixel associated with the liquid crystal display.
• each of the transistors 109 receiving a logic pulse UNE DIV, DTV, D2V and D2V on its gate is turned on during the application of the precharge voltage signal 0 p C on the gate of the TFT 104, thus locking the gate of its transistor 106 to ground and closing the transistor
• the UNE logic data inputs are short pulses and of low power, they can fully open the transistors 109 and allow any residual charge present on the gate of transistor 106 to be quickly discharged at
• the transistor 109 of any stage which has a ZERO logic data input applied to its gate remains non-conducting. So therefore, the transistor
• the data inputs DIV, DIV, D2V and D2V and the precharge voltage pulse p ⁇ are all completed before the start of the active phase of the horizontal scanning line. This leaves the respective gates of the transistors 106 of all four
• the gates of the transistors 106 of the stages which are associated with the logic data inputs UN remain at ground potential
• the gate of transistor 106 of any stage associated with two ZERO logic data inputs and the gate of transistor 102 for controlling the pixel column remains at a potential of + 15 volts, keeping transistor 106 open and transistor 102 command of the passing pixel column.
• the conducting transistor 107 keeps the node A and the gate of the transistor 108 locked to ground, thus allowing the transistor 102 to control the pixel column stay on and continue to transfer the voltage V Ramp to the pixel associated with the liquid crystal display.
• the Mi arming pulse drops from a potential of + 15 volts to + VB volts at the time determined by the highest 6 bits of the 8-bit gray scale.
• the device of the least significant bit of the comparator data bits and the vernier data bits determine which of the 4 data inputs DIV, DIV, D2V and D2V are a logical ZERO.
• the two DV signals which are of ZERO logic determine when the output pulse Mo of the vernier circuit 100 drops and starts to supply the thin film transistor (TFT) 102 to make it stop applying V Ramp to the pixel associated with the liquid crystal display.
• TFT thin film transistor
• FIG. 5 shows the relative synchronization of the control signals from the vernier to the vernier 100
• the pulses 0AC to 0DC are the clock pulses of the last stage of the comparator 101-P (FIG. 1).
• the pulses z ⁇ ⁇ to 0 DV are the clock pulses on the vernier stage 100.
• the signals DIV, DIV, D2V and D2V are applied from stage 100A to stage 100D and only one of the 4 stages receives two ZERO logic signals to control the Mo output signal.
• Clock pulses of 0 A V - 1 0 D V OIlt - ⁇ & s ramp up and the Mo output of vernier 100 goes to the lower half of the ramp.
• TFT thin film transistors
• FIG. 7 helps to identify the voltages V 0 (the synchronization pulses), V j _, V 2 , V 3 and V 4 which exist at various points in the equivalent circuit of FIG. 6.
• the instantaneous values respective of these voltages are shown during time T when T corresponds to the duration of the synchronization pulse (as shown in Figure 5), starting from the assumption that the potential Mi of the arming pulse is low (i.e. + VB volts).
• Figure 8 shows the respective instantaneous values of these voltages during time T, on the assumption that the potential Mi of the arming pulse is high (eg +1.5 volts).
• the gray scale brightness of a selected liquid crystal display pixel is close to its maximum value V M , the starting gate potential Mi remains high for a relatively long time, leaving the free field to many disturbances on the value of V 3 (which can be
• REPLACEMENT SHEET numerous in a scale design for fine intensity steps). These disturbances normally tend to partially discharge V 4 . However for a 2 volt plateau for the thin film transistor (TFT) 108, using the positive bias + VB of about 2 volts, a disturbance of V 3 as high as 3 volts can keep 1 volt below the threshold. This can keep the TFT practically non-passing. A negligible discharge of the voltage V 4 can therefore be caused by the transistor 108 in the active phase of 50 ⁇ s maximum of a scanning line, as indicated by the experimental threshold and the data relating to the leaks.
• TFT thin film transistor
• each of the transistors 106 should be maintained in the 3 stages "not selected" in the closed state.
• Another advantage of employing a series of periodic synchronization pulses for each of the 4 phases having a period of only half the time interval of the given duration is that it allows the duration of each synchronization pulse to be extended longer than time T (see the dashed boxes in Figure 5). This extension of the duration of the synchronization pulses outside the limits in dotted lines is possible without the danger of a
• REPLACEMENT SHEET "weak trigger” or "false trigger”.
• This arrangement allows the transistor 108 (that is to say the one having a channel width of about 200 ⁇ m) to be smaller compared to the transistor 102 for controlling the pixel column (that is to say say the one having a channel width of about 750 ⁇ m), because the transistor 108 now has more time to complete the discharge of the gate capacitance of the transistor 102 for controlling the column of pixels.
• FIG. 9 shows an embodiment which uses only a least significant bit and which receives two arming pulses MiA and MiB. This device is thus useful with the type of divided bus comparator described in FIG. 5 of application RCA 85,678. The device of FIG.
• FIG. 9 comprises 4 stages 200A to 200D which, as indicated by the identical reference numbers for the identical elements, are very similar to stages 100A to 100D in FIG. 3.
• FIG. 9 There are 3 important differences between FIG. 9 and the diagram of the device of FIG. 3: (1) the parallel pairs of the transistors 109 of FIG. 3 are replaced by single transistors 200A to 200D on each stage; (2) the diagram of the device in FIG. 3 uses 2 arming transistors 201A and 201B which respectively receive the arming pulses MiA and MiB; (3) there are 2 drop transistors 202A and 202B, one or the other lowers the output signal Mo when the transistor is supplied with electric current.
• the cocking MiA pulse is applied only to 0AV phases 0 and BV * 3 while the arms ue MiB pulse is applied to 0CV phases 0 and DV
• the FI9 ure shows the application of data signals and DIV DIV to transistor gates 200.
• DIV is high and MiA is low, either phase 0AV or phase 0BV can stop the supply of transistor 102.
• either 0CV or either 0DV can stop the supply of the transistor 102. Consequently with the diagram of the device of figure 9, 8 widths of pulses are possible for the output pulses Mo.
• FIG. 11 represents the diagram of the device of a vernier circuit 300 which receives an arming pulse Min and thus is useful to the diagram of the comparator device described in the S / N application (RCA 85,678) which gives only 'an arming pulse Mi to the vernier.
• the diagram of the vernier device of FIG. 11 comprises 8 stages 300A to 300H. Each of the stages 300 is identical to the stages 100 of the diagram of the device of FIG. 3, as indicated by the identical reference numbers. However, each of the stages 300 includes 3 parallel transistors 301 with the ground locking node A when the electrical supply is opened by a control signal.
• the DIV, DIV, D2V, D2V and D3V and D3V are applied to the vernier as shown in FIG. 12.
• the signal DIV and its complement DIV are received from the comparator stage, the same as in the diagram of the device in FIG. 3.
• the D2V and D3V signals, and their complements are the 2 bits of the vernier.
• the synchronization of Figure 11 follows the synchronization of Figure 5 but there are 8 vernier clock pulses from 0A to 0H .
• the vernier Mo output pulses can thus have any of the 16 possible pulse widths.
• FIG. 13 represents the diagram of the device of a vernier 400 which receives 2 arming pulses MiA and, MiB of the diagram of the comparator stage device which gives 2 output pulses Mo.
• the diagram of the device of FIG. 13 works with the 8 phases 0AV to 0HV supplied to the 8 stages 400A to 400H respectively.
• the other elements Capacitance 105 and thin film transistor (TFT) 104 and 106 of each stage and the TFT 201A, 201B, 202A, 202B of the vernier, are the same as those of the diagram of the device of FIG. 9.
• each stage comprises 2 thin film transistors (TFT), the gates of the two
• SHEET OF RE LACEREZ must be of logic ZERO for a phase 0 pulse to close the thin film transistor (TFT) 102.
• TFT thin film transistor

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• 1990
  • 1990-12-03 US US07/620,681 patent/US5122676A/en not_active Expired - Fee Related
• 1991
  • 1991-12-03 WO PCT/FR1991/000959 patent/WO1992009985A1/fr not_active Application Discontinuation
  • 1991-12-03 EP EP92901530A patent/EP0513325A1/fr not_active Withdrawn
  • 1991-12-03 JP JP4501439A patent/JPH05504211A/ja active Pending

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