EP0511573A2 - Clock with clock adjusting data memory - Google Patents

Clock with clock adjusting data memory Download PDF

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Publication number
EP0511573A2
EP0511573A2 EP92106800A EP92106800A EP0511573A2 EP 0511573 A2 EP0511573 A2 EP 0511573A2 EP 92106800 A EP92106800 A EP 92106800A EP 92106800 A EP92106800 A EP 92106800A EP 0511573 A2 EP0511573 A2 EP 0511573A2
Authority
EP
European Patent Office
Prior art keywords
clock
adjusting data
data memory
adjusting
clock adjusting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP92106800A
Other languages
German (de)
English (en)
French (fr)
Other versions
EP0511573A3 (enrdf_load_stackoverflow
Inventor
Yoichi C/O Seikosha Co. Ltd. Seki
Hiroyuki C/O Seikosha Co. Ltd. Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seikosha KK
Original Assignee
Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seikosha KK filed Critical Seikosha KK
Publication of EP0511573A2 publication Critical patent/EP0511573A2/en
Publication of EP0511573A3 publication Critical patent/EP0511573A3/xx
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G3/00—Producing timing pulses
    • G04G3/02—Circuits for deriving low frequency timing pulses from pulses of higher frequency
    • G04G3/022—Circuits for deriving low frequency timing pulses from pulses of higher frequency the desired number of pulses per unit of time being obtained by adding to or substracting from a pulse train one or more pulses

Definitions

  • the present invention relates to a clock with a clock adjusting data memory, and more particularly, to a clock with a clock adjusting data memory having its clock adjusting data memory for storing an error of an oscillation frequency.
  • some of carrying, portable and stationary devices such as cameras, video tape recorders, facsimilies, telephones or time recorders have built-in clock systems for indicating or printing the dates, hours, minutes and seconds in accordance with the purposes of photographing an object, recording a video image, transmit by facsimiles indicating the telephone rates, and managing when the employee enters and leaves the office.
  • a clock equipped with a highly accurate oscillation source such as a crystal resonator is packaged in the camera so that a film exposing means such as a printing liquid crystal indicator is caused to flash with the date and time data which are outputted from the clock when the shutter is released.
  • the camera may be packaged with not only the printing liquid crystal indicator but also a data indicating liquid crystal indicator for indicating the photographic data such as the frame numbers of the film.
  • the liquid crystal indicator is driven with atemating current of 100 Hz or so, that is required to have only a low accuracy.
  • Another oscillation source of the camera is one for the CPU, which is required to have characteristics different from those of the afore-mentioned oscillation source.
  • the device thus far described has difficulties such as the increase in the parts number due to the double oscillation sources, the reduction in the flexibility for design due to the increase in the parts number, the diversification of the clock circuit, and the increase in the numbers of individual adjustments due to the diversified clock circuit.
  • the present invention has been conceived in view of the above-specified difficulties and has an object to provide a clock with a clock adjusting data memory, which is enabled to reduce the number of parts, improve flexibility for design standardize the clock circuit, eliminate the fast/slow adjusting member and simplify the individual fast/slow adjustments by providing the clock built in a device with a clock adjusting data memory which is stored with an error in the oscillation frequency and fast/slow adjusting data.
  • Another object of the present invention is to provide a clock with a clock adjusting data memory, which is enabled to reduce the clock adjusting data memory by storing the clock adjusting data in a non-volatile memory EEPROM disposed for another purpose.
  • a clock with a clock adjusting data memory comprising: an oscillation circuit acting as the base of a timing function; an output means for outputting clock signal from the oscillation circuit; a clock adjusting data memory means for storing a characteristic error included in the oscillation circuit as clock adjusting data; and a clock adjusting means for adjusting the output of the output means on the basis of the clock adjusting data memory means.
  • An EEPROM 8 as shown in Fig. 1, is stored with the frequency error or period of crystal oscillation unit 1. Further stored are the clock data which are made in the manufacture process by a clock timer 16 in accordance with the clock adjusting program CLKADJ which is stored in ROM 9, as shown in Fig. 2. In case of the camera, the program for its control is interrupted at each predetermined period by a clock counter 6, as shown in Fig. 1, so that the clock adjustment is accomplished while the camera is in operation or standby by executing the clock adjusting program CLKADJ.
  • the interruption period is 11 hours and 39 minutes and is stored in the EEPROM 8.
  • a clock with the clock adjusting data memory EQ1, according to the present invention is constructed, as shown in Fig. 1, to include; a crystal oscillation unit 1 composed of a crystal resonator 2, a resistor 3, an inverter 4 and capacitors C1 and C2; a frequency divider 5 a clock counter 6; an LCD 7; an EEPROM 8; a ROM 9; and a RAM 10.
  • the crystal resonator 2 of the crystal oscillation unit 1 has its one end connected with one end of the resistor 3, the input terminal of the inverter 4 and one end of the capacitor C1 which has the other end connected with the ground point. Moreover, the other end of the crystal resonator 2 is connected with the other end of resistor 3, the output terminal of the inverter and one end of the capacitor C2 which has the other end connected with the ground point.
  • an oscillation signal is outputted from the crystal oscillation unit 1 to the input terminal of the frequency divider 5 through a terminal 1a.
  • the output terminal of the frequency divider 5 is connected with the input terminal of the clock counter 6, which has its parallel output terminals connected with the LCD 7 having a function as output means.
  • the clock counter 6 is connected with a CPU 13 through a data bus 11.
  • the RAM 10 and the ROM 9 stored with the clock adjusting program CLKADJ as a clock adjusting means are individually connected with the CPU 13 through the data bus 11.
  • the CPU 13 is connected through a timer data bus 12 with a clock timer 16, which can be disposed outside of the clock with the clock adjusting data memory EQ1, and also with a terminal T1 for outputting a signal having a period of 1 second, which is produced by dividing the frequency of the output of the crystal oscillation unit 1.
  • the clock timer 16 is a meter which is used for rewriting the clock adjusting data of predetermined address in the EEPROM 8 of the clock with clock adjusting data memory EQ1 during the manufacture process and for measuring the error of a clock composed of the crystal oscillation unit 1 and so on.
  • a signal having a period of 1 second is outputted from the terminal T1 of the clock with the clock adjusting data memory EQ1 when the clock timer 16 is connected with said clock with the clock adjusting data memory EQ1.
  • the clock adjusting program CLKADJ as shown in Fig. 2, is executed. Specifically, the present time is read at first from the clock counter 6 by the CPU 13. Next, the clock adjusting data are read from the EEPROM 8 so that the present time and the adjusting data are calculated together in the CPU 13. The present time is delayed by the adjusting data when it is advanced but is advanced, when it is delayed. After this operation, the arithmetically adjusted time is set in the clock counter 6 so that the correct time is indicated. Incidentally, since the time indication is usually at a unit of second even at the minimum, the value less than second is decided according to the required accuracy. If the higher time accuracy is required, the fraction less than second is stored in the RAM 10 so that the time may be adjusted after 12 hours including the fraction. These clock adjustments are accomplished in a remarkably short time so that the current consumption will hardly increase.
  • the oscillation circuit in the foregoing embodiment uses the crystal as the resonator but may be exemplified by an IC or CR oscillation circuit.
  • the clock adjustment is accomplished for every 12 hours in the embodiment but may be accomplished at a constant time interval such as at 9 o'clock every morning.
  • the amount of adjustment itself may enter as an error (for example, in case the time is set at 8 : 59).
  • the required accuracy and the amount of adjustment are so considered in advance that they may be within ranges of no problem. If the amendments should raise a problem, the number of interruptions for the adjustment might be increased.
  • the foregoing embodiment has been described in connection with the method, in which the EEPROM 8 is stored with the time amount of 0.00003 seconds to be adjusted. If however, the amount of adjustment has a constant period of 1 second and if the error is 0.023843 seconds, the interruption period is every 11 hours and 39 minutes, and this period may be stored in the EEPROM 8.
  • Means for detecting the ambient temperature may be provided so that the adjusting data in the foregoing embodiment may be used as those for the error which is caused due to the ambient temperature.
  • the clock with the clock adjusting data memory is constructed to comprise; the oscillation circuit acting as the base of a timing function; the output means for outputting a clock signal from the oscillation circuit; the clock adjusting data memory means for storing a characteristic error included in the oscillation circuit as clock adjusting data; and the clock adjusting means for adjusting the output of the output means on the basis of the clock adjusting data memory means.
  • the clock with the clock adjusting data memory has the effects capable of reducing the number of parts, improving the flexibility for design dom, standardizing the clock circuit, eliminating the fast/slow adjusting member, and simplyfying the fast/slow adjustments.
  • Another effect capable of reducing the clock adjusting data memory can be obtained by storing the clock adjusting data in the EEPROM which is provided for another purpose.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Electric Clocks (AREA)
EP92106800A 1991-04-19 1992-04-21 Clock with clock adjusting data memory Withdrawn EP0511573A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP88197/91 1991-04-19
JP3088197A JPH04319694A (ja) 1991-04-19 1991-04-19 時刻補正データメモリ付時計装置

Publications (2)

Publication Number Publication Date
EP0511573A2 true EP0511573A2 (en) 1992-11-04
EP0511573A3 EP0511573A3 (enrdf_load_stackoverflow) 1994-02-16

Family

ID=13936177

Family Applications (1)

Application Number Title Priority Date Filing Date
EP92106800A Withdrawn EP0511573A2 (en) 1991-04-19 1992-04-21 Clock with clock adjusting data memory

Country Status (2)

Country Link
EP (1) EP0511573A2 (enrdf_load_stackoverflow)
JP (1) JPH04319694A (enrdf_load_stackoverflow)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0683443A3 (en) * 1994-05-20 1996-03-20 Nec Corp Correcting the time of an electronic watch.
EP0691598A3 (de) * 1994-07-04 1998-05-20 GRUNDIG Aktiengesellschaft Verfahren und Anordnung zum Betreiben einer Software-Uhr in einem Gerät der Unterhaltungselektronik
US6304517B1 (en) 1999-06-18 2001-10-16 Telefonaktiebolaget Lm Ericsson (Publ) Method and apparatus for real time clock frequency error correction

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08101286A (ja) * 1994-09-30 1996-04-16 Nec Gumma Ltd カレンダ時計回路
JP2010256240A (ja) * 2009-04-27 2010-11-11 Denso Corp 車両用時計および車両用時計の製造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57117184A (en) * 1981-01-13 1982-07-21 Citizen Watch Co Ltd Non-volatile memory circuit for portable electronic device
CH664868GA3 (enrdf_load_stackoverflow) * 1986-07-10 1988-04-15

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0683443A3 (en) * 1994-05-20 1996-03-20 Nec Corp Correcting the time of an electronic watch.
US5748570A (en) * 1994-05-20 1998-05-05 Nec Corporation Time correction of an electronic clock
EP0691598A3 (de) * 1994-07-04 1998-05-20 GRUNDIG Aktiengesellschaft Verfahren und Anordnung zum Betreiben einer Software-Uhr in einem Gerät der Unterhaltungselektronik
US6304517B1 (en) 1999-06-18 2001-10-16 Telefonaktiebolaget Lm Ericsson (Publ) Method and apparatus for real time clock frequency error correction

Also Published As

Publication number Publication date
JPH04319694A (ja) 1992-11-10
EP0511573A3 (enrdf_load_stackoverflow) 1994-02-16

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