EP0482746A2 - Sélection de tables de consultation pour fenêtres multiples - Google Patents

Sélection de tables de consultation pour fenêtres multiples Download PDF

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Publication number
EP0482746A2
EP0482746A2 EP91307969A EP91307969A EP0482746A2 EP 0482746 A2 EP0482746 A2 EP 0482746A2 EP 91307969 A EP91307969 A EP 91307969A EP 91307969 A EP91307969 A EP 91307969A EP 0482746 A2 EP0482746 A2 EP 0482746A2
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EP
European Patent Office
Prior art keywords
windows
window
selecting
display
display position
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP91307969A
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German (de)
English (en)
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EP0482746A3 (en
Inventor
Taggart Huth Robertson
Paul Mark Schanely
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International Business Machines Corp
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International Business Machines Corp
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Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of EP0482746A2 publication Critical patent/EP0482746A2/fr
Publication of EP0482746A3 publication Critical patent/EP0482746A3/en
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/02—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed
    • G09G5/06—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed using colour palettes, e.g. look-up tables
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/14—Display of multiple viewports

Definitions

  • This invention relates to a method and apparatus for selecting a data signal such as a palette identifier in a graphics system having multiple windows on a display screen.
  • VRAM video RAM
  • the VRAM data is converted by a digital-to-analog converter (DAC) to one or more analog outputs --typically, separate red (R), green (G) and blue (B) outputs in a colour system -- which are used by the display as intensity representations of the original VRAM data.
  • DAC digital-to-analog converter
  • VRAM lookup table
  • palette additional RAM
  • the address input to the LUT is provided by the pixel data originating from the VRAM.
  • the new value for that pixel, which is stored in the LUT, is read out from the address location corresponding to the pixel data.
  • the resulting output from the LUT is then used for the DAC operation.
  • the VRAM data can be converted, using a LUT, to a wide range of colour combinations.
  • a computer program or application controls the values stored or loaded in the LUT and does so independently from other applications.
  • each application is confined to an area, or window, of display on the CRT.
  • These windows are often overlapping in the sense that a given pixel may be common to two or more windows. In such a case, the windows are prioritised and it is the pixel data for the highest-priority window of two or more overlapping windows that is actually displayed on the screen. It is also common for a single application to use multiple windows. Multiple LUTs are used to allow the use of separate LUTs for separate application windows or for separate windows within a single application.
  • the assignment and selection of LUTs for each window on the CRT display can be accomplished by providing additional planes in the VRAM to store bits identifying the LUT to be used for each pixel. In such an arrangement, for each pixel stored in the VRAM there is an associated definition for the LUT to be used for that particular pixel. Because there is an associated cost for the additional planes that contain the LUT selection definition, it is apparent that a more cost-effective method of selecting LUTs is desirable.
  • the present invention now contemplates a method of selecting a data signal for a particular position on a display within a graphics system providing multiple windows on a display, each of said windows having defined boundaries on said display and a data signal associated therewith, said windows being ranked by relative priorities assigned thereto, the method comprising storing quantities representing the boundaries of each of said windows, generating signals representing said display position, selecting the windows whose boundaries as represented by said stored quantities include said display position, and selecting the data signal associated with the selected window with the highest priority.
  • the present invention also contemplates a graphics system providing multiple windows on a display screen, each of said windows having defined boundaries on said display and a data signal associated therewith, said windows being ranked by relative priorities assigned thereto, the system having apparatus for selecting one of said data signals for a particular position on said display such apparatus comprising means for storing quantities representing the boundaries of each of said windows, means for generating signals representing said display position, means responsive to said storing means and said generating means for selecting the windows whose boundaries include said display position, and means for selecting the data signal associated with the selected window with the highest priority.
  • Display device 12 may be a cathode ray tube (CRT) display, liquid crystal display (LCD), gas plasma display, colour printer or any other suitable display device known to the art.
  • CTR cathode ray tube
  • LCD liquid crystal display
  • gas plasma display gas plasma display
  • colour printer any other suitable display device known to the art.
  • the particular display technology used is not relevant to the present invention.
  • display device 12 provides a rectangular display comprising a plurality of pixels that are organised into rows and columns, as is conventional in the art.
  • the display screen 40 may comprise 1024 rows, each of which contains 1280 pixels. These pixels are conventionally identified using X Y coordinates as shown in the figure so that the lower left pixel p1 has the X Y screen coordinates (0,0) while the upper right pixel p2 has the screen coordinates (1279,1023).
  • window 42 is a rectangular window having an extent less than that of the entire screen.
  • XMIN is the X coordinate of the leftmost pixels (e.g., p3) in the window 42
  • XMAX is the X coordinate of the pixels (e.g., p4) immediately to the right of the window 42.
  • YMIN is the coordinate of the lowermost pixels (e.g., p3) in the window 42;
  • YMAX is the Y coordinate of the pixels (e.g., p4) immediately above the window 42. If the window 42 borders the right or top edge of the screen 42, XMAX or YMAX is set equal to 1280 or 1024, respectively.
  • pixel data to be provided to display device 12 is stored in a video ram, or VRAM, 14, also referred to in the art as a frame buffer.
  • VRAM video ram
  • each pixel stored in VRAM 14 contains 8 bits of data.
  • This pixel data may be arranged in VRAM 14 by providing a number of planes equal to the number of bits in each pixel and by providing row addresses corresponding to the Y screen position (or 1023 - Y) and column addresses corresponding to the X screen position in Fig. 2.
  • Other types of memory organisation alternatively may be used; the exact manner in which pixel data is organised in VRAM 14 is not as such relevant to the present invention.
  • VRAM 14 provides pixel data to a lookup table RAM 18 via lines 16.
  • RAM 18 comprises a plurality of groups LUT0-LUT7 of contiguous locations functioning as lookup tables (LUTs), one of which is selected in accordance with a selection signal provided on lines 22 originating from selection logic 20 that is the subject of the present invention.
  • each of lookup tables LUT0 through LUT7 comprises 256 consecutively addressable locations, each of which stores a word having a length of 8 bits, or 1 byte.
  • the combined address signal representing the concatenation of the selection signal provided by selection logic 20 and the pixel data signal provided by VRAM 14 selects the particular location within RAM 18; selection logic 20 provides the three most significant bits on lines 22 to select one of lookup tables LUT0 through LUT7, while VRAM 14 supplies the 8 least significant bits to select a particular location within the selected table LUT0 through LUT7.
  • fewer LUTs in RAM 18 may be provided if desired.
  • tables LUT5 through LUT7 may be eliminated, and table LUT4 selected if the most significant bit of the three-bit selection signal is one, regardless of the value of the other two bits.
  • VRAM 14 provides pixel data simultaneously for a group of four adjacent pixels A0 through A3 along a given row, while simultaneously selection logic 20 provides selection signals on lines 22 for the same group of four pixels. Since each pixel requires eight bits of pixel data from VRAM 14 and three bits of selection data from selection logic 20, VRAM 14 provides RAM 18 on each read cycle with 32 bits of data, representing four adjacent pixels A0 through A3. In a similar manner, selection logic 20 provides a 12-bit control signal on each read cycle, 3 bits for each of pixels A0-A3. Since VRAM 14 is providing pixel data to RAM 18 four pixels at a time, the clock signal used to read out data from VRAM 14, as well as to read out the control signal from selection logic 20, is only one fourth the frequency at which pixels are scanned on the screen 40.
  • RAM 18 provides the words selected by the address signals on line 16 and 22 to a digital-to-analog converter (DAC) 32 one pixel at a time on lines 30.
  • An output line 34 couples DAC 32 to display device 12.
  • VRAM 14, RAM 18 and DAC 32 are shown in Fig. 1, separate elements would typically be used for each of the three colour outputs (R G B) in a standard system.
  • display device 12 also receives suitable horizontal and vertical synchronisation signals from graphics system 10.
  • Selection logic 20 is preferably implemented as a single application-specific integrated circuit (ASIC), although other implementations are of course possible.
  • ASIC application-specific integrated circuit
  • a plurality of extent registers 50 are used to define the X and Y extremes (minima and maxima) of each of up to eight windows WO-W7 (Fig. 7) to be displayed on the screen 40.
  • each window W0-W7 there is an XMIN register 52 for storing the minimum X coordinate for the window, an XMAX register 54 for storing the maximum X coordinate of the window (actually, the X coordinate just to the right of the window), a YMIN register 56 for storing the minimum Y coordinate of the window, and a YMAX register 58 for storing the maximum Y coordinate for the window (actually, the Y coordinate just above the window).
  • a total of 32 registers 50 are used to define the extents of up to eight windows W0-W7.
  • Each of the signals stored by extent registers 50 has the 11-bit format shown for XMIN and XMAX in Fig. 12.
  • X and Y counters indicated generally by the reference numeral 62 in Fig. 4 are shown in more detail in Fig. 6.
  • an X counter 132 providing an X count on line 74 receives a reset input from an HSYNC line 24 and an incrementing count input from a CLOCK line 28.
  • HSYNC line 24 carries a pulse at the beginning of each horizontal scan across the screen 40
  • CLOCK line 28 carries a clock signal generated synchronously with the readout of pixel data from VRAM 14 (Fig. 1).
  • X counter 132 provides an output on line 74 that emulates the horizontal sweep of the scanning beam (if a CRT display is used) across the display 40.
  • the CLOCK signal on line 28 is generated synchronously with the readout of pixel data from VRAM 14. Since, as noted above, data for contiguous groups of pixels A0-A3 are read out from VRAM 14 in parallel, four pixels at a time, the CLOCK signal frequency is one fourth the frequency at which successive pixels are displayed on screen 40. Accordingly, the X output from X counter 132 has the nine-bit format shown in Fig. 11, in which the least significant bit position (X8) represents, in effect, the 4's position of the X count.
  • a Y counter 134 providing a Y count on line 76 receives a load input from a VSYNC line 26 and a decrementing count input from the same HSYNC line 24 coupled to the reset input of counter 132.
  • VSYNC line 28 carries a pulse at the beginning of the first (i.e., uppermost) left-to-right scan across screen 40.
  • counter 134 Upon receiving a VSYNC pulse at its load input, counter 134 is loaded with an input (not separately shown) corresponding to a Y coordinate (in this instance 1024) just above the uppermost line on screen 40.
  • X Y compare logic 60 simultaneously compares the current X and Y position as indicated by X Y counter registers 62 with the contents of each of the extent registers 50, the X position being compared with the contents of the X extent registers and the Y position being compared with the contents of the Y position registers. This allows window select logic 64 to determine which of the windows W0-W7, if any, includes the current position.
  • X Y compare logic 60 contains, for each window, an XMIN comparator 86, an XMAX comparator 88, a YMIN comparator 90 and an YMAX comparator 92.
  • XMIN comparator 86 receives as inputs the nine-bit X position signal provided on line 74 from X counter 132 as well as the nine most significant bits of the XMIN signal (Fig. 12) provided on line 78 from the XMIN register 52 for that window.
  • XMAX comparator 88 receives as inputs the X position signal on line 74 as well as the nine most significant bits of the XMAX signal (Fig. 12) provided on line 80 from the XMAX register 54 for that window.
  • XMIN comparator 86 provides an XMIN COMPARE signal on line 94 whenever the two inputs to the comparator match, while XMAX comparator 88 similarly provides an XMAX COMPARE signal on line 98 when its two inputs match.
  • the two least significant bits of the XMIN signal (XMIN9 and XMIN10) are not fed to comparator 86 but instead are provided as outputs on lines 96.
  • the two least significant bits (XMAX9 and XMAX10) of the XMAX signal on lines 80 are not fed to XMAX comparator 88 but are instead supplied as output signals on lines 100.
  • YMAX comparator 92 receives as inputs the Y position signal on line 76 from Y counter 134 and the YMAX signal on line 84 from the YMAX register 58 for that window.
  • YMIN comparator 90 receives as input signals the Y position signal on line 76 from Y counter 134 as well as the YMIN signal on line 82 from the YMIN register 56 for that window.
  • the Y counter 134 is continually decremented from its maximum value as scanning progresses downwardly on the screen 40.
  • YMAX comparator 92 provides an output setting a Y condition latch 102 for that window.
  • YMIN comparator 90 provides an output resetting the same Y condition latch 102.
  • the Y condition latch 102 for that window provides a Y condition signal on the corresponding line 104 indicating that the current position is within the Y boundaries of the window. This signal is applied, together with the signals on lines 94, 96, 98 and 100 for that window, to the window select logic 64.
  • Fig. 13 shows a portion of the window select logic 64 that is replicated for each of the windows W0-W7.
  • pixel latch logic 106 responsive to the XMIN COMPARE and XMAX COMPARE signals on lines 94 and 98 as well as the XMIN9-XMIN10 and XMAX9-XMAX10 signals on lines 96 and 100 controls the setting and resetting of respective latches 108, 110, 112 and 114 associated with the respective pixels A0-A3 being concurrently processed. More particularly, each pixel latch indicates whether that pixel is within the X boundaries of the window as indicated by the XMIN and XMAX signals on lines 78 and 80 from the corresponding XMIN and XMAX registers 52 and 54.
  • An XMIN COMPARE signal on line 94 from X Y compare logic 60 indicates the occurrence of a left window boundary (i.e., the leftmost pixel in the window) coincident with one of the pixels A0-A3, as indicated by the least significant bits XMIN9 and XMIN10 of the XMIN signal, provided on line 96.
  • Pixel latch logic 106 responds to the XMIN COMPARE signal on line 94 by setting one or more of pixel latches 108-114 in accordance with the values XMIN9 and XMIN10.
  • latches 110-114 are set if XMIN9 and XMIN10 are 0 and 1, while latches 112 and 114 are set if XMIN9 and XMIN10 are 1 and 0. Any latches not set on the current cycle of the CLOCK signal on line 28 are set on the next cycle, since the pixels processed on that cycle are even farther to the right of the left window boundary.
  • pixel latch logic 106 resets one or more of pixel latches 108-114 in accordance with the values of XMAX9 and XMAX10 on lines 100.
  • the right window boundary i.e., the leftmost pixel to the right of the window
  • Pixel latches 108-114 are therefore all reset, since pixels A0-A3 are all outside of the window.
  • pixels A0-A2 lie within the window, while pixel A3 lies without.
  • Pixel logic 106 therefore resets A3 latch 114 immediately and resets the remaining latches 108-112 on the next clock cycle. Suitable means within pixel latch logic 106 are provided to handle the situation where the left and right window boundaries occur within the same group or adjacent groups of pixels A0-A3. Pixel latches 108-114 provide outputs to respective AND gates 116, 118, 120 and 122, each of which also receives an input from the Y CONDITION line 104. AND gates 116-122 provide outputs B0-B3 on lines 124, 126, 128 and 130, indicating whether the respective pixels A0-A3 are within the window in question. Since there are eight windows W0-W7, window select logic 64 provides a total of 32 outputs, eight binary outputs per pixel A0-A3.
  • respective programmable priority registers 70 store signals indicating the relative priorities P(0)-P(7) assigned to the eight windows W0-W7 provided for in the embodiment shown.
  • Priorities P(0)-P(7) may each range between O and 7, with the higher numbers indicating higher priorities.
  • Priority select logic 66 responds to the signals from window select logic 64 and from priority registers 70 to select, from the priorities P(i) associated with the selected windows W(i), the highest of such assigned priorities P(i).
  • a 12-bit output from priority select logic 66 indicates the selected priority P(i) for each of the four pixels A0-A3 being concurrently processed. If none of the windows W0-W7 contains a particular pixel A0-A3, then the priority P(i) generated by priority select logic 66 for that pixel is the lowest assigned priority contained in priority register 70.
  • Windows W0-W7 are assigned default priorities to enable a unique selection if two or more windows have the same assigned priority stored in priority registers 70. Thus, window W7 is assigned the highest default priority, window W6 the next highest default priority and so on, with window W0 having the lowest default priority. These default priorities, as already noted, are only used in the event two or more windows inclusive of the current position have the same programmed priority.
  • respective programmable LUT registers 72 store signals L(0)-L(7) identifying the lookup tables LUT0-LUT7 of RAM 18 respectively assigned to the windows W0-W7.
  • two or more windows Wi may also have the same assigned lookup table LUTi in RAM 18.
  • LUT select logic 68 responds to the signal P(i) from priority select logic 66, indicating the highest priority associated with a window inclusive of the current position, as well as to the signals from priority registers 70 and LUT registers 72 to generate a signal L(i) on line 22 identifying the lookup table LUTi associated with that highest priority.
  • LUT select logic 68 accomplishes this by first using the priority signal P(i) from priority select logic 66 and the priority registers 70 to identify the corresponding window Wi by generating a cross-reference of window versus assigned priority. LUT select logic 68 then uses LUT register 72 to obtain the corresponding LUT identifier L(i), which it outputs on lines 22. This three-bit signal is supplied via lines 22 as additional address bits to RAM 18 to select the particular lookup table LUT0-LUT7 within the RAM. These operations are performed in parallel for each of the four pixels A0-A3, for a total of 12 bit outputs on lines 22 each cycle of the CLOCK signal on line 28.
  • two or more windows W0-W7 can have the same assigned priority stored in priority registers 70. In such an instance, it may not be possible to associate a priority P(i) received from priority select logic 66 with a particular window Wi. In order to provide a unique LUT selection where the selected priority is associated with two or more windows, LUT selection logic 68 selects the LUT assigned to the highest-numbered window having the selected priority P(i).
  • Fig. 7 shows a typical situation in which screen 40 contains overlapping windows W0-W7.
  • the identifiers Pi indicate the priority associated with a particular window Wi
  • the identifiers Li indicate the particular lookup table LUTi of RAM 18 associated with window Wi.
  • window O has a priority P(0) of three and is associated with lookup table LUT1
  • window W1 has a priority P(1) of two and is associated with lookup table LUT3 in RAM 18.
  • priorities and lookup tables are assigned to windows W0-W7 by storing the following values P(i) in the priority registers 70 i P(i) 0 3 1 2 2 4 3 5 4 7 5 6 6 1 7 0 and by storing the following values in the LUT registers 72: i L(i) 0 1 1 3 2 3 3 4 4 5 5 2 6 1 7 0
  • Extent registers 50, priority registers 70 and LUT registers 72 are loaded under program control and altered at appropriate times, such as during the VSYNC pulse or during a blanking interval when pixels are not being scanned.
  • X Y compare logic 60, window select logic 64, priority select logic 66 and LUT select logic 68 are each clocked logic circuits, timed by the CLOCK signal on line 28, with outputs following the inputs from which they are generated from one clock cycle. Each logic unit latches its outputs in registers before passing them to the next unit in the pipeline. It will be seen that as a result of this pipelined architecture and timing scheme, the LUT select signal on line 22 will trail the current position signals on lines 74 and 76 by four cycles of the clock signal 28 or 16 pixels. In order to ensure that the output signal on line 22 is properly synchronised with the readout of pixel data from VRAM 14, the counters 132 and 134 are so controlled as to compensate for the delay occasioned in the pipeline.
  • the disclosed selection logic can be used to generate a data signal that identifies or otherwise provides information associated with the highest-priority window that includes a particular pixel. In such a case, the registers 72 would be loaded with the data signals associated with the windows.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Controls And Circuits For Display Device (AREA)
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EP19910307969 1990-10-23 1991-08-30 Multiple-window lookup table selection Withdrawn EP0482746A3 (en)

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US60183590A 1990-10-23 1990-10-23
US601835 1990-10-23

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EP0482746A2 true EP0482746A2 (fr) 1992-04-29
EP0482746A3 EP0482746A3 (en) 1992-07-01

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0541220A2 (fr) * 1991-09-09 1993-05-12 Sun Microsystems, Inc. Appareil et méthode pour gérer l'allocation des valeurs d'identification des attributs d'affichage et des tables de matériels multiples de consultation pour couleurs
EP0574630A1 (fr) * 1992-06-19 1993-12-22 International Business Machines Corporation Système d'affichage comportant des fenêtres
EP0590778A1 (fr) * 1992-10-01 1994-04-06 Hudson Soft Co., Ltd. Dispositif de traitement d'images
WO1995019029A1 (fr) * 1994-01-04 1995-07-13 Honeywell Inc. Architecture de sortie video reconfigurable avec amelioration de trame
EP1043886A2 (fr) * 1999-04-09 2000-10-11 Sun Microsystems, Inc. Méthode et appareil d'affectation de couleurs

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4808989A (en) * 1984-12-22 1989-02-28 Hitachi, Ltd. Display control apparatus
EP0392551A2 (fr) * 1989-04-14 1990-10-17 Brooktree Corporation Codeur de priorité pour fenêtres
EP0431754A2 (fr) * 1989-12-07 1991-06-12 Advanced Micro Devices, Inc. Circuit de conversion de couleurs

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JPS60221794A (ja) * 1984-04-18 1985-11-06 富士通株式会社 画面表示制御方式
JPS6177977A (ja) * 1984-09-25 1986-04-21 Canon Inc 画像処理装置
JPS62198980A (ja) * 1986-02-26 1987-09-02 Meidensha Electric Mfg Co Ltd 図形表示装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4808989A (en) * 1984-12-22 1989-02-28 Hitachi, Ltd. Display control apparatus
EP0392551A2 (fr) * 1989-04-14 1990-10-17 Brooktree Corporation Codeur de priorité pour fenêtres
EP0431754A2 (fr) * 1989-12-07 1991-06-12 Advanced Micro Devices, Inc. Circuit de conversion de couleurs

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
MESURES REGULATION AUTOMATISME. vol. 52, no. 1, 19 January 1987, PARIS FR pages 63 - 66; NICOLAS PARIS ET AL.: 'Multi-fenêtrage: deux solutions pour mieux voir' *

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0541220A2 (fr) * 1991-09-09 1993-05-12 Sun Microsystems, Inc. Appareil et méthode pour gérer l'allocation des valeurs d'identification des attributs d'affichage et des tables de matériels multiples de consultation pour couleurs
EP0541220A3 (en) * 1991-09-09 1995-02-15 Sun Microsystems Inc Apparatus and method for managing the assignment of display attribute identification values and multiple hardware color lookup tables
EP0574630A1 (fr) * 1992-06-19 1993-12-22 International Business Machines Corporation Système d'affichage comportant des fenêtres
US5664130A (en) * 1992-06-19 1997-09-02 International Business Machines Corporation Windowing display system
EP0590778A1 (fr) * 1992-10-01 1994-04-06 Hudson Soft Co., Ltd. Dispositif de traitement d'images
WO1995019029A1 (fr) * 1994-01-04 1995-07-13 Honeywell Inc. Architecture de sortie video reconfigurable avec amelioration de trame
EP1043886A2 (fr) * 1999-04-09 2000-10-11 Sun Microsystems, Inc. Méthode et appareil d'affectation de couleurs
EP1043886A3 (fr) * 1999-04-09 2003-03-12 Sun Microsystems, Inc. Méthode et appareil d'affectation de couleurs

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JPH04264617A (ja) 1992-09-21
EP0482746A3 (en) 1992-07-01

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