EP0472137A1 - Horloge à division de fréquence fractionnaire et asservissement de cette horloge - Google Patents

Horloge à division de fréquence fractionnaire et asservissement de cette horloge Download PDF

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Publication number
EP0472137A1
EP0472137A1 EP91113849A EP91113849A EP0472137A1 EP 0472137 A1 EP0472137 A1 EP 0472137A1 EP 91113849 A EP91113849 A EP 91113849A EP 91113849 A EP91113849 A EP 91113849A EP 0472137 A1 EP0472137 A1 EP 0472137A1
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EP
European Patent Office
Prior art keywords
signal
clock
circuit
producing
frequency division
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP91113849A
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German (de)
English (en)
French (fr)
Inventor
Luc Dartois
Peter Reusens
Etienne Vanzieleghen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel CIT SA
Original Assignee
Alcatel Mobile Communication France SA
Alcatel Radiotelephone SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Mobile Communication France SA, Alcatel Radiotelephone SA filed Critical Alcatel Mobile Communication France SA
Publication of EP0472137A1 publication Critical patent/EP0472137A1/fr
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
    • H03K23/662—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by adding or suppressing pulses

Definitions

  • the present invention relates to a clock with fractional frequency division and means for controlling this clock on a synchronization signal.
  • a programmable counter receiving a rhythm signal and provided for periodically delivering, according to the recurrence period, a first and a second successive series of pulses, the repetition frequencies of these two series being sub-multiples of the frequency of the rhythm signal.
  • Such a device in addition to the programmable counter, requires two additional counters to determine the number of pulses of each series and the control means. It therefore occupies, in the case of an integrated form, a relatively large substrate surface, which is an obstacle to the miniaturization of the equipment in which it is implanted.
  • phase shift between the output signal and a signal whose frequency is exactly in the division ratio of that of the rhythm signal is widely variable and can have a large amplitude.
  • a first object of the present invention is the production of a clock with fractional frequency division having a reduced size thanks to the use of simpler elementary circuits and whose output signal exhibits a limited phase shift with the desired frequency.
  • This phase shift in a preferred embodiment, is less than a period of the rhythm signal.
  • the present invention therefore also relates to control means specially adapted to this type of clock with fractional frequency division.
  • a mobile terminal of this system in fact comprises a speech coding and decoding member which can be carried out by means of a standard component operating with clock signals of 8 kHz and 2048 kHz.
  • the terminal also includes an internal clock producing a 13 MHz rhythm signal and generates a 50 Hz synchronization signal on which the coding and decoding member must be synchronized.
  • the invention thus makes it possible, from the rhythm signal, to produce the clock signals synchronized with the synchronization signal.
  • the fractional frequency division clock comprises a division circuit which produces a clock signal from a rhythm signal, the frequencies of these two signals being in a division ratio which is the sum of '' an integral part and a fractional part, a pulse absorber receiving the rhythm signal and transmitting it to the division circuit by suppressing at least one pulse from this signal on command, and is characterized in that it comprises accumulation means for controlling the pulse absorber each time the product of the number of pulses of the clock signal counted from an original instant and said fractional part changes unit.
  • phase shift between the clock signal and the timing signal is thus minimized.
  • the accumulation means comprise an accumulation register producing a first operand which takes the value of an addition signal in response to the clock signal and an addition circuit producing this signal addition as the sum modulo the denominator of the fractional part of the first operand and of a second operand comprising at least the numerator of the fractional part and producing a retaining signal, said pulse absorber being designed to absorb a number of pulses equal to the difference of said two fac dividers in response to the carry signal.
  • the fractional frequency division clock being designed to be controlled by a synchronization signal, it comprises a control module receiving this synchronization signal and said clock signal and producing a correction signal, the second operand being the sum of the numerator and the correction signal.
  • the servo module comprises means for producing a count value corresponding to the number of pulses of said holog signal appeared during a period of fixed duration measurement, means for producing a correction value proportional to the difference between a second and a first count value and inversely proportional to the duration separating the middle of the second and of the corresponding corresponding measurement periods, the correction signal usually zero, being assigned the correction value during a correction period expressed as a number of periods of the clock signal.
  • the servo module comprises a counter receiving the signal d clock and producing a phase signal, the capacity of this counter being a submultiple of the ratio of the frequencies of the clock and synchronization signals, comprises a summing circuit producing the second count value as the sum of the values taken by the phase signal at the rate of the synchronization signal, a time delay register producing the first count value as the second count value with a delay of a measurement period, a subtraction circuit producing a phase difference signal as the difference of said second and first count values, and a correction module producing the correction value in p proportion of the phase difference signal.
  • an elementary output of the counter is used to produce an auxiliary clock signal.
  • the fractional frequency division clock further comprises a compensation circuit now producing the correction value as the sum of the values of the output signal of the correction module during the previous measurement period and the current measurement period.
  • the compensation circuit includes a saturation adder limiting said correction value to a determined maximum value.
  • the fractional frequency division clock comprises a limitation circuit affecting the correction signal of the correction value during the first appearance of a determined state of an elementary output of the counter following the start a period of the synchronization signal, the correction signal being zero for the rest of the period.
  • the fractional frequency division clock includes a synchronization register producing as a measurement signal the phase signal in response to a trigger signal from a trigger circuit whose output takes the value of said synchronization signal on command of the clock signal, the measurement signal being sent to the summing circuit.
  • the fractional frequency division clock comprises a control circuit producing a control signal whose period is equal to the measurement period, this control signal causing the reset of the summing circuit, the transfer of the input to the output of the timer register and the modification of the compensation circuit output signal.
  • the fractional frequency division clock receives an initialization signal intended to initialize the compensation circuit.
  • the fractional frequency division clock includes an initialization circuit imposing on the counter a start value in response to the initialization signal.
  • the whole part of the division ratio is zero. It is also possible to provide in the fractional frequency division clock that the difference of the two division factors is equal to unity, the pulse absorber suppressing a single pulse on command.
  • Fractions with fractional frequency division receive a rhythm signal and produce a clock signal and are designed so that the frequencies of these signals are in a Q division ratio.
  • This ratio can always be decomposed set as the sum of the product of a first division factor A and a fractional part F and the product of a second division factor B and the complement to one of this fractional part, where the division factors are numbers integers and the fractional part a number between zero and one:
  • the different numbers can also be chosen such that the difference of the two division factors is equal to one:
  • fractional part can be represented in the form of a fraction comprising a numerator N and a denominator D:
  • the invention will be presented in relation to a concrete application case concerning the digital cellular radiocommunication system.
  • a mobile terminal is provided with an internal oscillator which produces the rhythm signal at a frequency of 13 MHz. It is necessary to produce from this signal, the clock signal used in particular for speech processing circuits at a frequency of 2.048 MHz.
  • the division ratio is therefore worth:
  • the fractional frequency division clock of the invention represented in FIG. 1 comprises a pulse absorber 1 which receives the rhythm signal R and whose output is connected to the input of a division 2 circuit which produces the clock signal Ck. It also includes accumulation means 3 receiving this clock signal and controlling the pulse absorber by a carry signal C, these means being provided to limit the phase shift of the clock signal as will appear later.
  • the pulse absorber 1 transmits the rhythm signal R directly to its output, except when it receives the carry signal C. In the latter case it removes a pulse from the rhythm signal.
  • the division circuit 2 produces the clock signal Ck whose frequency is a submultiple of that of the signal applied to its input. This sub-multiple is equal to the second division factor B, 6 in the present case.
  • This circuit can be a counter, for example, and when it divides by an even number, it will advantageously be a ring counter also known as a "Johnson" counter.
  • a counter of this type is produced by putting series flip-flops, the first of which receives the output signal of the last which is the clock signal Ck.
  • the submultiple here is twice the number of flip-flops.
  • the accumulation means 3 are provided for triggering the pulse absorber 1 each time the product of the fractional part F and of a number of pulses of the clock signal counted from an instant of origin changes unit, that is to say when its entire part increases by one.
  • This original instant is arbitrarily fixed, it only constitutes a time reference. It can be, for example, the time of activation of the clock.
  • accumulation means 3 in a particular embodiment which should not be considered as a limitation of the invention comprises an addition circuit 31 and an accumulation register 32.
  • the accumulation register 32 produces a first operand 0 1 which has the value that an addition signal S had when the last pulse of the clock signal Ck appeared.
  • the addition circuit 32 produces this addition signal S as the sum of the first operand and of a second operand 0 2 modulo the denominator D of the fractional part F.
  • the second operand, in this first part of the invention takes the value of the numerator N of this fractional part F.
  • This circuit is further provided for delivering the carry signal C to the pulse absorber 1, when this sum is greater than the denominator.
  • the denominator is equal to 256.
  • the addition circuit can therefore consist of a simple adder delivering an output signal on 8 bits and a carry signal.
  • the invention applies if the division ratio is reduced to the fractional part, that is to say if the first A and second B division factors are respectively worth 1 and 0.
  • the division circuit 2 is reduced to a single link, the clock signal Ck being the output signal of the pulse absorber 1.
  • the clock with fractional frequency division is designed to be slaved by a servo module on a synchronization signal whose frequency is a submultiple of that of the clock signal.
  • This servo module is designed to record the number of pulses of the clock signal Ck during a fixed value measurement period. It produces a first count value during a first measurement period, then a second count value during a second measurement period. It then calculates a correction value which is proportional to the difference of these two count values and inversely proportional to the duration separating the media from the two corresponding measurement periods. Finally, it produces a correction signal which takes this correction value during a correction period and which is zero the rest of the time. This correction signal is added to the numerator N of the fractional part F to form the second operand 0 2 of the addition circuit 31.
  • This servo module 4 appears in an embodiment given only for information in Figure 2. It includes several bodies which will now be detailed.
  • a counter 40 receives the clock signal Ck and produces a phase signal P which corresponds to the number of pulses appeared since its reset.
  • the capacity of this counter is a submultiple of the frequency ratio of the clock signal Ck and the synchronization signal T.
  • a trigger circuit 41 produces a trigger signal D which takes the value that the synchronization signal T had when the last pulse of the clock signal Ck appeared. It can be, for example, a rocker known as rocker D.
  • a synchronization register 42 produces a measurement signal Pe which has the value that the phase signal P had when the last pulse of the trigger signal D.
  • a control circuit 43 produces a periodic control signal L whose period is equal to the measurement period.
  • this measurement period will be a multiple of the period of the synchronization signal.
  • a summing circuit 44 delivers the second count value P 2 which is the sum of the values taken by the measurement signal Pe during each pulse of the synchronization signal T. This circuit is reset to zero by the control signal L. It It will now appear more clearly why the output signal of this circuit is the second count value.
  • a timer register 45 produces the first count value P1 as the second count value delayed by a measurement period, that is to say by a control signal period L.
  • the output signal from this register has the value that had the output signal from the summing circuit 44 during the previous measurement period.
  • a subtraction circuit 46 produces a phase difference signal E as the difference of the two count values: P 2 - P1.
  • a correction module 47 produces an output signal whose value is that of the phase difference signal E divided by the ratio between the measurement period and the period of the synchronization signal T and multiplied by a constant which is called commonly coefficient of servo stiffness.
  • a compensation circuit 48 produces a correction value m which is the sum of the values of the output signal of the correction module 47 during the previous measurement period and during the current period.
  • This circuit is designed to limit this correction value to a maximum value. It will for example include a saturation adder which produces the sum of the two values or this maximum value if this sum is greater than it.
  • This circuit is also intended to be initialized by means of an initialization signal I.
  • a limitation circuit 49 produces the correction signal M which has the correction value m during a correction period and which is zero the rest of the time.
  • This correction period may be of any value and will be determined by a person skilled in the art.
  • This correction signal M is added with an adder not shown in the figure to the numerator N of the fractional part F to give the second operand 02.
  • the counter 40 is initialized to a starting value I T by means of an initialization circuit 50 controlled by the initialization signal on appearance of the synchronization signal T.
  • the counter 40 is further provided for delivering an auxiliary clock signal H on the output of one of these counting cells.
  • This auxiliary clock signal is in synchronism with the clock signal and, like the latter, it is controlled by the synchronization signal T.
  • the capacity of the counter 40 will be chosen equal to 256, the most significant bit corresponding to the auxiliary clock signal H at a frequency of 8 kHz.
  • the count values Pi, P 2 are not equal to the number of pulses of the clock signal Ck produced during the corresponding measurement periods, since the counter 40 will have completed several cycles (160 in this case) for a period of the synchronization signal.
  • These count values correspond to these numbers of pulses since they are congruent (modulo 256 in this case).
  • the capacity of the counter is sufficient. If this were not the case, it is always possible to increase the capacity of this counter in order to widen the possible correction range, its capacity being limited to the ratio of the frequencies of the clock signal and the synchronization signal.
  • An advantageous solution consists in making the limitation circuit 49 so that the correction period is the period of the auxiliary clock signal H.
  • the correction signal is assigned the correction value during this period and is zero during the rest of the period of the synchronization signal T. This operation is repeated periodically at the rate of the synchronization signal, for example.
  • the correction value may take one of the values -2 , -1, 0, 1 or 2.
  • the second operand 0 2 which is the sum of the correction value and the numerator will therefore be an integer between 87 and 91.
  • the adder which produces this second operand can be reduced to a simple combinational circuit which produces the 4 bits of low weight of this operand, its 3 most significant bits being invariable. Indeed, the 5 decimal values that this operator can take are expressed as follows in binary numbering:
  • the carry signal C of the addition circuit 33 is periodic. Its period corresponds to 256 pulses of the clock signal Ck. It follows that the auxiliary clock signal which has the same period has the particularity that all of its pulses have the same phase shift because they are separated by the same number of periods from the rhythm signal R. Thus, when the signal auxiliary clock is used as the sampling signal, it does not introduce parasitic modulation on the signal which is sampled.
  • Another advantage of the invention lies in the fact that the temporal distribution of the divisions by the first A and by the second B division factor is as uniform as possible.
  • the maximum phase difference between the clock signal Ck and the rhythm signal also called phase jitter, is worth one period of the rhythm signal, ie 76.9 ns.
  • the embodiment of the servo module 4 which has been described has a very complete structure which provides the advertised performance.
  • the invention also applies if certain organs are removed.
  • the trigger circuit 41 is not strictly necessary, it only makes it possible to synchronize the synchronization register 42 with the clock signal Ck. It can be deleted by directly ordering this register with the signal synchronization T instead of the trigger signal D.
  • the second count value P 2 is equal to the measurement signal Pe which is applied directly to the input of the timer register 45 at the place of the output signal of the summing circuit 44.
  • This synchronization register is controlled by the synchronization signal T instead of the control signal L, which is also the case for the compensation circuit 48.
  • this compensation circuit can also be omitted, the output of the correction module 47 being directly connected to the input of the limitation circuit 49.

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
EP91113849A 1990-08-24 1991-08-19 Horloge à division de fréquence fractionnaire et asservissement de cette horloge Withdrawn EP0472137A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9010616A FR2666184A1 (fr) 1990-08-24 1990-08-24 Horloge a division de frequence fractionnaire et asservissement de cette horloge.
FR9010616 1990-08-24

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EP0472137A1 true EP0472137A1 (fr) 1992-02-26

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EP91113849A Withdrawn EP0472137A1 (fr) 1990-08-24 1991-08-19 Horloge à division de fréquence fractionnaire et asservissement de cette horloge

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US (1) US5267273A (US07223432-20070529-C00017.png)
EP (1) EP0472137A1 (US07223432-20070529-C00017.png)
JP (1) JPH0514185A (US07223432-20070529-C00017.png)
FR (1) FR2666184A1 (US07223432-20070529-C00017.png)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3327028B2 (ja) * 1995-02-14 2002-09-24 松下電器産業株式会社 周波数シンセサイザ
US5802132A (en) * 1995-12-29 1998-09-01 Intel Corporation Apparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking scheme
FR2757001B1 (fr) * 1996-12-05 1999-02-05 Sgs Thomson Microelectronics Dispositif de decoupage de la periode d'un signal en n parties quasi-egales
CN1120602C (zh) * 1998-04-14 2003-09-03 弗兰霍菲尔运输应用研究公司 多载波解调系统中精细频率同步化的方法及装置
US6629256B1 (en) * 2000-04-04 2003-09-30 Texas Instruments Incorporated Apparatus for and method of generating a clock from an available clock of arbitrary frequency
DE10291151D2 (de) * 2001-03-15 2004-04-15 Bosch Gmbh Robert Verfahren und Vorrichtung zur Bildung von Taktimpulsen in einem Bussystem mit wengistens einem Teilnehmer, Bussystem und Teilnehmer
DE10159257C2 (de) * 2001-12-03 2003-11-13 Siemens Ag Vorrichtung zur Nachbildung eines Taktsignals
US7443935B2 (en) * 2002-11-02 2008-10-28 Texas Instruments Incorporated Apparatus and method for dynamically adjusting receiver bandwidth
US9954535B2 (en) * 2016-07-21 2018-04-24 Andapt, Inc. Noise-immune reference (NREF) integrated in a programmable logic device
CN111416617B (zh) * 2020-03-18 2024-05-03 广州土圭垚信息科技有限公司 一种时钟同步方法、装置及电子设备
CN114204937B (zh) * 2022-02-16 2022-06-14 山东兆通微电子有限公司 一种分频器电路及频率合成器
CN116841346A (zh) * 2022-03-25 2023-10-03 长鑫存储技术有限公司 时钟计数器、时钟计数方法及存储装置
US11811403B2 (en) 2022-03-25 2023-11-07 Changxin Memory Technologies, Inc. Clock counter, method for clock counting, and storage apparatus

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0019412A1 (en) * 1979-05-09 1980-11-26 The Marconi Company Limited A method of synthesizing an output frequency and circuit arrangement therefor

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4228403A (en) * 1977-06-17 1980-10-14 Nippon Gakki Seizo Kabushiki Kaisha Submultiple-related-frequency wave generator
US4555793A (en) * 1983-11-28 1985-11-26 Allied Corporation Averaging non-integer frequency division apparatus
US4658406A (en) * 1985-08-12 1987-04-14 Andreas Pappas Digital frequency divider or synthesizer and applications thereof
JPS6379420A (ja) * 1986-09-22 1988-04-09 Nec Corp 周波数奇数分周器
US4712224A (en) * 1986-10-09 1987-12-08 Rockwell International Corporation Offset digitally controlled oscillator
US4914680A (en) * 1987-06-03 1990-04-03 Sanyo Electric Co., Ltd. Signal distinction circuit
DE3826006C1 (US07223432-20070529-C00017.png) * 1988-07-30 1989-10-12 Wandel & Goltermann Gmbh & Co, 7412 Eningen, De
US4991187A (en) * 1989-07-21 1991-02-05 Motorola, Inc. High speed prescaler

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0019412A1 (en) * 1979-05-09 1980-11-26 The Marconi Company Limited A method of synthesizing an output frequency and circuit arrangement therefor

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FR2666184A1 (fr) 1992-02-28
US5267273A (en) 1993-11-30
JPH0514185A (ja) 1993-01-22
FR2666184B1 (US07223432-20070529-C00017.png) 1994-04-22

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