EP0471526A1 - Vertical power MOSFET - Google Patents

Vertical power MOSFET Download PDF

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Publication number
EP0471526A1
EP0471526A1 EP91307370A EP91307370A EP0471526A1 EP 0471526 A1 EP0471526 A1 EP 0471526A1 EP 91307370 A EP91307370 A EP 91307370A EP 91307370 A EP91307370 A EP 91307370A EP 0471526 A1 EP0471526 A1 EP 0471526A1
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EP
European Patent Office
Prior art keywords
conductivity type
drain
source
resistivity layer
layer
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP91307370A
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German (de)
French (fr)
Inventor
Minoru Yoshioka
Mitsuo Matsunami
Toshiaki Miyajima
Hideyuki Tsuji
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Sharp Corp
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Sharp Corp
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Publication of EP0471526A1 publication Critical patent/EP0471526A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0886—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate

Definitions

  • the invention relates to a vertical power MOSFET and more particularly to a vertical power MOSFET devices which can lower on-resistance at a high power application.
  • Fig. 4 exemplifies a structure of a conventional vertical power MOSFET, a n-channel vertical power MOSFET 100 which comprises a n-type low resistivity drain substrate 101 (N+) and a high resistivity drain layer 102 (N ⁇ ) formed thereon and provided with a plurality of p-type well regions 103 for forming channels and also with n-type low resistivity source regions 104 (N+ region) each formed in the respective p-type well regions 103.
  • the well regions 103 are spaced with each other in a fixed interval and coated on their surface with a silicon oxide film 106 except a part of each well region 103 at which the source region 104 contacts with a source electrode 107.
  • a polysilicon gate electrode 105 extends above the silicon oxide film 106 and between adjacent well regions 103 and is coated with an insulating film 108, such as PSG (phosphorus glass).
  • the source electrode 107 is deposited on the insulating layer 108 by sputtering and contacts with both of the source region 104 and the well region 103 as shown.
  • a metal drain electrode 109 is deposited at the back of the drain substrate 101 by vacuum deposition or the like.
  • the portion illustrated by the dotted line in Fig. 4 shows an extent of a depletion layer which is created when the pn junction between source and drain in the vertical power MOSFET 100 is biased reversely.
  • the MOSFET constructed above can have a larger surface area to fetch current therethrough in comparison with a horizontal MOSFET wherein source and drain electrodes are arranged on the same surface, so that it can be used in high power applications.
  • the well regions 103 and the source regions 104 are formed in a manner of self-alignment by using the gate electrode 105 as a mask, so that density of an impurity to be doped can be controlled accurately, thereby allowing Vth of MOSFET devices in operation to have 1narrow scatter and be precise.
  • the present invention has been designed to overcome the problems of the conventional art under the above circumstance.
  • An object of the invention is to provide a vertical power MOSFET which solves the problems.
  • a vertical power MOSFET which comprises a semiconductive substrate of a first conductivity type serving as drain, an impurity region of a second conductivity type on a part of the surface of the semiconductive substrate, an impurity region of a first conductivity type formed on a part of the surface of the second conductivity type impurity region and serving as source, and a surface portion of a second conductivity type semiconductive substrate between source and drain serving as a channel portion with a gate electrode thereon through an insulating film, so that voltage is applied to the gate electrode to control channel current between source and drain, wherein the first conductivity type semiconductive substrate comprises a low resistivity layer and a high resistivity layer epitaxially formed on the low resistivity layer, and at an interface between the low resistivity layer and the high resistivity layer is provided a convexed portion which projects at least to the high resistivity layer side.
  • the convexed portion may be rectangular in cross-section or may be tapered to some extent at the shoulders of the rectangular cross-sectional shape. Also, the convexed portion using an embedding region of the first conductivity type impurity may be shaped as convexed partially to the low resistivity layer side.
  • the convexed portion provided at the interface between the low resistivity layer and the high resistivity layer decreases resistance of a portion in the high resistivity layer through which current flows, thereby allowing on-resistance to be lowered.
  • Fig. 1 is a longitudinal sectional view schematically showing a structure of an embodiment of the present invention.
  • Figs. 2(a) to (c) are schematic diagrams showing the forming process of the convexed portion in the example.
  • Fig. 3 is a longitudinal sectional view showing another structure of a modified embodiment of the invention.
  • Fig. 4 is a longitudinal sectional view showing a structure of a conventional example.
  • Fig. 1 is a sectional view of a n-channel vertical power MOSFET of an example of the present invention.
  • 1 is a N+ type of low resistivity layer and 2 is a N ⁇ type of high resistivity layer, and the layers 1 and 2 constitute a semiconductive substrate of a first conductivity type serving as drain.
  • a plurality of p-type well regions 3 are formed in the high resistivity layer 2 to form a channel portion, and a convex 11 is provided at an interface between the low resistivity layer 1 and the high resistivity layer 2 just under a region sandwiched between the well regions 3.
  • n-type low resistivity source region which is formed in the respective well regions 3.
  • the upper surfaces of the well regions 3 and source regions 4 except their parts contacting with a conventional source electrode 7 are coated with a gate oxide film 6.
  • a gate electrode 5 of polysilicon is arranged in a predetermined position on the gate oxide film 6 and coated with an insulating film 8.
  • the source electrode 7 is formed on the insulating film 8.
  • 9 is a drain electrode.
  • the low resistivity layer 1 is provided by that a low resistivity n-type silicon substrate is first subjected to taper-etching (or a complete trench etching) by RIE process using, for example, SiCl4 + N2 gas and a photoresist mask to form the convex 11.
  • the region to be etched in this case is set in position corresponding to a region sandwiched between the well regions 3 in Fig. 3.
  • a high resistivity silicon layer 2a having the same conductivity type as the low resistivity layer 1 is epitaxially formed in a predetermined thickness as shown in Fig. 2(b) followed by grinding to remove a convexed portion formed on the surface of an epitaxial layer (N ⁇ ) corresponding to the convex 11 so as to form a uniform mirror surface as shown in Fig. 2(c), thereby providing the high resistivity layer 2.
  • the gate oxide film 6 is applied 500 to 1000 ⁇ in thickness on the mirror surface of the high resistivity layer 2 by thermal oxidation, on which polysilicon serving as the gate electrode 5 is deposited 4000 to 6000 ⁇ in thickness by low pressure CVD process, followed by continuously etching of the polysilicon and the gate oxide film 6 through RIE process using a photoresist mask.
  • Boron (B) is implanted to form the p-type well regions 3 and then arsenic (As) to form the source regions 4 (N+) in a self-alignment manner using the polysilicon gate electrode 5 as a mask.
  • PSG or the like is deposited 6000 ⁇ to 1 ⁇ m in thickness on the well and source regions by CVD process to form the insulating layer 8 which is then etched to provide a contact 10 for the source electrode 7, followed by depositing Al-Si 1 ⁇ m in thickness by sputtering to form the source electrode 7.
  • Cr-Ni-Ag or the like is deposited at the back of the low resistivity layer 1 by vacuum deposition to form the drain electrode 9 followed by final sintering of the device at 450°C to complete the processes.
  • the present invention may be applicable to a p-channel vertical power MOSFET other than the n-channel vertical power MOSFET referred to in the above example.
  • n+ type of impurity embedding region 11a serving as the convexed portion is formed at the interface between the low resistivity layer 1 and the high resistivity layer 2.
  • the impurity embedding region 11a is convexed to both of the low and high resistivity layers sides at the interface therebetween.
  • the impurity embedding region 11a is provided by that n-type impurity, such as phosphorous (P) is first implanted in density of more than 1 x 1016cm ⁇ 3 in a region of the low resistivity layer 1 just below the gate electrode 5 by using a photoresist mask. Then, the photoresist is peeled off and the impurity embedding region 11a is washed followed by epitaxially forming the high resistivity layer 2 in a predetermined thickness (few to 100 ⁇ m). Then, the gate oxide film 6 is formed 500 to 1000 ⁇ in thickness by thermal oxidation and polysilicon is deposited thereon 4000 to 6000 ⁇ in thickness by LPCVD process to form the gate electrode 5.
  • n-type impurity such as phosphorous (P) is first implanted in density of more than 1 x 1016cm ⁇ 3 in a region of the low resistivity layer 1 just below the gate electrode 5 by using a photoresist mask. Then, the photoresist
  • the deposited polysilicon serving as the gate electrode 5 and the underlying gate oxide film 6 are patterned by dry etching with a photoresist mask followed by implanting boron (B) to form the p-type well regions 3 and arsenic (As) to form the source regions 4 by use of the gate electrode 5 as a mask.
  • PSG or the like is deposited 6000 ⁇ to 10000 ⁇ in thickness on the well and source regions by CVD process to form the insulating layer 8 which is then smoothed in shape by heating at 1000°C and etched to provide a contact for the source electrode 7, followed by depositing Al-Si for wiring of the source electrode 7 by sputtering.
  • Cr-Ni-Ag or the like is deposited at the back of the low resistivity layer 1 by vacuum deposition to form the drain electrode 9 followed by final sintering of the device at 450°C to complete the processes.
  • the present invention provides the convexed portion in a specific region at the interface between the low resistivity layer serving as drain and the high resistivity epitaxially formed layer thereon, so that on-resistance can be lowered without deteriorating other properties. Also, devices designed as having equal on-resistance may be subminiatured in chip size to enable cost to produce to be lowered. The advantage effects on heating of devices, power consumption or the like.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A vertical power MOSFET which comprises a semiconductive substrate of a first conductivity type serving as drain, an impurity region of a second conductivity type on a part of the surface of the semiconductive substrate, an impurity region of a first conductivity type formed on a part of the surface of the second conductivity type impurity region and serving as source, and a surface portion of a second conductivity type semiconductive substrate between source and drain serving as a channel portion with a gate electrode thereon through an insulating film, so that voltage is applied to the gate electrode to control channel current between source and drain, wherein the first conductivity type semiconductive substrate comprises a low resistivity layer and a high resistivity layer epitaxially formed on the low resistivity layer, and at an interface between the low resistivity layer and the high resistivity layer is provided a convexed portion which projects at least to the high resistivity layer side.

Description

    BACKGROUND OF THE INVENTION 1. Field of the Invention
  • The invention relates to a vertical power MOSFET and more particularly to a vertical power MOSFET devices which can lower on-resistance at a high power application.
    • 2. Description of the Related Art
  • Fig. 4 exemplifies a structure of a conventional vertical power MOSFET, a n-channel vertical power MOSFET 100 which comprises a n-type low resistivity drain substrate 101 (N⁺) and a high resistivity drain layer 102 (N⁻) formed thereon and provided with a plurality of p-type well regions 103 for forming channels and also with n-type low resistivity source regions 104 (N⁺ region) each formed in the respective p-type well regions 103.
  • The well regions 103 are spaced with each other in a fixed interval and coated on their surface with a silicon oxide film 106 except a part of each well region 103 at which the source region 104 contacts with a source electrode 107. A polysilicon gate electrode 105 extends above the silicon oxide film 106 and between adjacent well regions 103 and is coated with an insulating film 108, such as PSG (phosphorus glass).
  • The source electrode 107 is deposited on the insulating layer 108 by sputtering and contacts with both of the source region 104 and the well region 103 as shown. A metal drain electrode 109 is deposited at the back of the drain substrate 101 by vacuum deposition or the like.
  • The portion illustrated by the dotted line in Fig. 4 shows an extent of a depletion layer which is created when the pn junction between source and drain in the vertical power MOSFET 100 is biased reversely.
  • A predetermined voltage is applied to the gate electrode 105 in the above structure for MOSFET to form a channel layer in the well regions placed beneath the gate electrode 105. When voltage is applied between the drain electrode 109 and the source electrode 107, current flows therebetween through the drain substrate 101, the drain layer 102, the channel layers and the source region 104.
  • The MOSFET constructed above can have a larger surface area to fetch current therethrough in comparison with a horizontal MOSFET wherein source and drain electrodes are arranged on the same surface, so that it can be used in high power applications. Also, the well regions 103 and the source regions 104 are formed in a manner of self-alignment by using the gate electrode 105 as a mask, so that density of an impurity to be doped can be controlled accurately, thereby allowing Vth of MOSFET devices in operation to have 1narrow scatter and be precise.
  • In the conventional vertical power MOSFET 100, current flows through the portion of high resistivity drain layer 102 sandwiched between the well regions 103. Hence, there is a limit to lower resistance between source and drain when electrified (on-resistance). In detail, when resistivity of the high resistivity drain layer 102 is lowered, a larger electric field is excited at the junction with the well regions 103 to lower the breakdown voltage between source and drain electrodes, resulting in such defect that resistivity of the drain layer 102 is lowered only to some extent. Also, to increase the number of the unit cell for lowering the on-resistance should lead to an increase of required surface area of chip, creating the problems of high cost to produce and difficulty in provision of that structure.
  • The present invention has been designed to overcome the problems of the conventional art under the above circumstance. An object of the invention is to provide a vertical power MOSFET which solves the problems.
    • SUMMARY OF THE INVENTION
  • According to the present invention, there is provided a vertical power MOSFET which comprises a semiconductive substrate of a first conductivity type serving as drain, an impurity region of a second conductivity type on a part of the surface of the semiconductive substrate, an impurity region of a first conductivity type formed on a part of the surface of the second conductivity type impurity region and serving as source, and a surface portion of a second conductivity type semiconductive substrate between source and drain serving as a channel portion with a gate electrode thereon through an insulating film, so that voltage is applied to the gate electrode to control channel current between source and drain, wherein the first conductivity type semiconductive substrate comprises a low resistivity layer and a high resistivity layer epitaxially formed on the low resistivity layer, and at an interface between the low resistivity layer and the high resistivity layer is provided a convexed portion which projects at least to the high resistivity layer side.
  • The convexed portion may be rectangular in cross-section or may be tapered to some extent at the shoulders of the rectangular cross-sectional shape. Also, the convexed portion using an embedding region of the first conductivity type impurity may be shaped as convexed partially to the low resistivity layer side.
  • The convexed portion provided at the interface between the low resistivity layer and the high resistivity layer decreases resistance of a portion in the high resistivity layer through which current flows, thereby allowing on-resistance to be lowered.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • Fig. 1 is a longitudinal sectional view schematically showing a structure of an embodiment of the present invention.
  • Figs. 2(a) to (c) are schematic diagrams showing the forming process of the convexed portion in the example.
  • Fig. 3 is a longitudinal sectional view showing another structure of a modified embodiment of the invention.
  • Fig. 4 is a longitudinal sectional view showing a structure of a conventional example.
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS EXAMPLES
  • Next, the present invention will be further detailed with referring to the attached drawings. The present invention should not be limited to the example described hereunder.
  • Fig. 1 is a sectional view of a n-channel vertical power MOSFET of an example of the present invention. In the drawing, 1 is a N⁺ type of low resistivity layer and 2 is a N⁻ type of high resistivity layer, and the layers 1 and 2 constitute a semiconductive substrate of a first conductivity type serving as drain. A plurality of p-type well regions 3 are formed in the high resistivity layer 2 to form a channel portion, and a convex 11 is provided at an interface between the low resistivity layer 1 and the high resistivity layer 2 just under a region sandwiched between the well regions 3.
  • 4 is a n-type low resistivity source region which is formed in the respective well regions 3. The upper surfaces of the well regions 3 and source regions 4 except their parts contacting with a conventional source electrode 7 are coated with a gate oxide film 6. A gate electrode 5 of polysilicon is arranged in a predetermined position on the gate oxide film 6 and coated with an insulating film 8. The source electrode 7 is formed on the insulating film 8. 9 is a drain electrode.
  • As shown in Fig. 2(a), the low resistivity layer 1 is provided by that a low resistivity n-type silicon substrate is first subjected to taper-etching (or a complete trench etching) by RIE process using, for example, SiCl₄ + N₂ gas and a photoresist mask to form the convex 11. The region to be etched in this case is set in position corresponding to a region sandwiched between the well regions 3 in Fig. 3.
  • Next, a high resistivity silicon layer 2a having the same conductivity type as the low resistivity layer 1 is epitaxially formed in a predetermined thickness as shown in Fig. 2(b) followed by grinding to remove a convexed portion formed on the surface of an epitaxial layer (N⁻) corresponding to the convex 11 so as to form a uniform mirror surface as shown in Fig. 2(c), thereby providing the high resistivity layer 2. Then, the gate oxide film 6 is applied 500 to 1000Å in thickness on the mirror surface of the high resistivity layer 2 by thermal oxidation, on which polysilicon serving as the gate electrode 5 is deposited 4000 to 6000Å in thickness by low pressure CVD process, followed by continuously etching of the polysilicon and the gate oxide film 6 through RIE process using a photoresist mask.
  • Boron (B) is implanted to form the p-type well regions 3 and then arsenic (As) to form the source regions 4 (N⁺) in a self-alignment manner using the polysilicon gate electrode 5 as a mask.
  • PSG or the like is deposited 6000Å to 1µm in thickness on the well and source regions by CVD process to form the insulating layer 8 which is then etched to provide a contact 10 for the source electrode 7, followed by depositing Al-Si 1µm in thickness by sputtering to form the source electrode 7. Cr-Ni-Ag or the like is deposited at the back of the low resistivity layer 1 by vacuum deposition to form the drain electrode 9 followed by final sintering of the device at 450°C to complete the processes.
  • The present invention may be applicable to a p-channel vertical power MOSFET other than the n-channel vertical power MOSFET referred to in the above example.
  • Next, a modified embodiment of the present invention will be detailed with referring to Fig. 3.
  • In this example, n⁺ type of impurity embedding region 11a serving as the convexed portion is formed at the interface between the low resistivity layer 1 and the high resistivity layer 2. The impurity embedding region 11a is convexed to both of the low and high resistivity layers sides at the interface therebetween.
  • The impurity embedding region 11a is provided by that n-type impurity, such as phosphorous (P) is first implanted in density of more than 1 x 10¹⁶cm⁻³ in a region of the low resistivity layer 1 just below the gate electrode 5 by using a photoresist mask. Then, the photoresist is peeled off and the impurity embedding region 11a is washed followed by epitaxially forming the high resistivity layer 2 in a predetermined thickness (few to 100µm). Then, the gate oxide film 6 is formed 500 to 1000Å in thickness by thermal oxidation and polysilicon is deposited thereon 4000 to 6000Å in thickness by LPCVD process to form the gate electrode 5.
  • The deposited polysilicon serving as the gate electrode 5 and the underlying gate oxide film 6 are patterned by dry etching with a photoresist mask followed by implanting boron (B) to form the p-type well regions 3 and arsenic (As) to form the source regions 4 by use of the gate electrode 5 as a mask.
  • PSG or the like is deposited 6000Å to 10000Å in thickness on the well and source regions by CVD process to form the insulating layer 8 which is then smoothed in shape by heating at 1000°C and etched to provide a contact for the source electrode 7, followed by depositing Al-Si for wiring of the source electrode 7 by sputtering. Cr-Ni-Ag or the like is deposited at the back of the low resistivity layer 1 by vacuum deposition to form the drain electrode 9 followed by final sintering of the device at 450°C to complete the processes.
  • A plurality of impurity embedding regions of N⁺ type 11a may be provided by several times of epitaxial formation corresponding to specific predetermined thickness thereof to further lower the on-resistance. In detail, an impurity embedding region is first formed in the low resistivity layer 1. Epitaxial formation of the high resistivity layer 2 is stopped in the midst of operation and a further impurity embedding region is applied on that impurity embedding region. Then, the high resistivity layer 2 is epitaxially formed again.
  • It will be appreciated that the present invention may be applicable to p-channel vertical power MOSFET other than n-channel vertical power MOSFET referred to above.
  • The present invention provides the convexed portion in a specific region at the interface between the low resistivity layer serving as drain and the high resistivity epitaxially formed layer thereon, so that on-resistance can be lowered without deteriorating other properties. Also, devices designed as having equal on-resistance may be subminiatured in chip size to enable cost to produce to be lowered. The advantage effects on heating of devices, power consumption or the like.
  • The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the scope of the invention.
  • There are described above novel features which the skilled man will appreciate give rise to advantages. These are each independent aspects of the invention to be covered by the present application, irrespective of whether or not they are included within the scope of the following claims.

Claims (4)

  1. A vertical power MOSFET which comprises a semiconductive substrate of a first conductivity type serving as drain, an impurity region of a second conductivity type on a part of the surface of the semiconductive substrate, an impurity region of a first conductivity type formed on a part of the surface of the second conductivity type impurity region and serving as source, and a surface portion of a second conductivity type semiconductive substrate between source and drain serving as a channel portion with a gate electrode thereon through an insulating film, so that voltage is applied to the gate electrode to control channel current between source and drain, wherein the first conductivity type semiconductive substrate comprises a low resistivity layer and a high resistivity layer epitaxially formed or the low resistivity layer, and at an interface between the low resistivity layer and the high resistivity layer is provided a convexed portion which projects at least to the high resistivity layer side.
  2. A vertical power MOSFET according to claim 1, wherein the convexed portion comprises a high doped impurity embedding region of a fist conductivity type.
  3. A vertical power MOFSET according to claim 1, wherein the convexed portion is rectangular in cross-section or is tapered to some extent at the shoulders of a rectangular cross-sectional shape.
  4. A vertical power MOSFET comprises:
       a semiconductor substrate of a first conductivity type providing a drain;
       an impurity region of a second conductivity type in contact with a first surface portion of the substrate, providing a source;
       a gate electrode adjacent a second surface portion of the substrate operable to provide a voltage to control current flow between the source and drain;
       the semiconductor substrate comprising a first layer providing the first and second surface portions having a relatively high resistance and a second layer of relatively low resistance;
    characterised in that the interface between the first and second layers of the semiconductor substrate is configured to substantially minimise the current path between the source and drain.
EP91307370A 1990-08-11 1991-08-09 Vertical power MOSFET Withdrawn EP0471526A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP212512/90 1990-08-11
JP2212512A JPH0494576A (en) 1990-08-11 1990-08-11 Vertical power mos fet

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US5925911A (en) * 1995-04-26 1999-07-20 Nippondenso Co., Ltd. Semiconductor device in which defects due to LOCOS or heat treatment are suppressed
EP1119052A2 (en) * 2000-01-19 2001-07-25 Infineon Technologies AG Vertical DMOS transistor device having a low on-resistance

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JP5025935B2 (en) * 2005-09-29 2012-09-12 オンセミコンダクター・トレーディング・リミテッド Method for manufacturing insulated gate field effect transistor
JP2009088005A (en) * 2007-09-27 2009-04-23 Sanyo Electric Co Ltd Semiconductor device and method of manufacturing the same
US20120175755A1 (en) * 2011-01-12 2012-07-12 Infineon Technologies Ag Semiconductor device including a heat spreader
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FR2731841A1 (en) * 1995-03-07 1996-09-20 Nippon Denso Co INSULATED GRID TYPE FIELD EFFECT TRANSISTORS AND METHOD FOR MANUFACTURING SAME
US5753943A (en) * 1995-03-07 1998-05-19 Nippondenso Co., Ltd. Insulated gate type field effect transistor and method of manufacturing the same
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US5925911A (en) * 1995-04-26 1999-07-20 Nippondenso Co., Ltd. Semiconductor device in which defects due to LOCOS or heat treatment are suppressed
EP1119052A2 (en) * 2000-01-19 2001-07-25 Infineon Technologies AG Vertical DMOS transistor device having a low on-resistance
EP1119052A3 (en) * 2000-01-19 2002-05-15 Infineon Technologies AG Vertical DMOS transistor device having a low on-resistance

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US5229634A (en) 1993-07-20

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