EP0465014A2 - Verfahren und Anordnung zur auf Regeln beruhende Datenübertragung - Google Patents

Verfahren und Anordnung zur auf Regeln beruhende Datenübertragung Download PDF

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EP0465014A2
EP0465014A2 EP91305185A EP91305185A EP0465014A2 EP 0465014 A2 EP0465014 A2 EP 0465014A2 EP 91305185 A EP91305185 A EP 91305185A EP 91305185 A EP91305185 A EP 91305185A EP 0465014 A2 EP0465014 A2 EP 0465014A2
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Prior art keywords
dasd
cpu
internal memory
data
channel
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EP0465014A3 (en
EP0465014B1 (de
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Robert Wesley Shomler
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International Business Machines Corp
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International Business Machines Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device

Definitions

  • This invention relates to the exchange of data between CPU internal memory and attached external storage subsystems, and more particularly, to those exchanges where some of the data are located in non-contiguous memory or storage locations.
  • CPU central processing unit
  • memory storage organization
  • storage organization of a hierarchically controlled computer system exemplified by the IBM System/370.
  • I/O is managed by a dedicated virtual machine termed a "channel" which effectuates the access and movement of data between CPU internal memory and external storage.
  • the channel manifests control by way of a series of channel commands communicated to and interpreted by the external storage subsystem (see Clarke et al below).
  • the CPU internal memory addresses to which data are to be exchanged are expressed by way of a list of address words (CCW's or S/370 Indirect Address List Facility).
  • CCW's or S/370 Indirect Address List Facility The list processing associated with the access and transfer takes significant time.
  • command encapsulation is one known measure for reducing the number of additional command exchanges between the external storage subsystem and the channel, it does not alleviate the list processing of addresses in the data transfer.
  • External storage sub-systems in the form of direct access storage device (DASD) arrays see Brady et al below) and parallel access transfer data from non-contiguous locations and otherwise impose extensive list processing requirements.
  • DASD direct access storage device
  • a CPU or processor typically includes a local operating system (OS), RAM implemented internal store, local instruction and data caches operatively formed from the internal store, an external store, and lock, cache, and storage resource managers.
  • OS operating system
  • RAM implemented internal store
  • local instruction and data caches operatively formed from the internal store
  • an external store and lock
  • cache and storage resource managers.
  • internal storage or “system storage” specifies that portion of storage randomly addressable for single read or write transfers.
  • internal storage is byte addressable except for an extension (“expanded store”).
  • Expanded store is random accessed on a block or page addressable (4096 bytes/page) basis.
  • expanded store may be managed as an LRU real memory backed paging store. The choice of unit of data size or frame is arbitrary.
  • “external storage” refers to that bulk portion of storage that is not randomly addressable and must be directly accessed as on DASD.
  • a DASD is a constant speed rotating magnetic storage disk device supporting direct access by read/write heads. Because the magnetic disk medium is rotating, each data access requires positioning movable read/write heads in space and time over concentric tracks on the disk.
  • the disk is also characterized as being a cyclic track recording medium.
  • the IBM System 360 architecture introduced a virtual machine dedicated to accessing and exchanging data between the CPU internal memory and attached external storage or other devices over a physical path connection.
  • the virtual machine was in the form of a collection of software procedures associated with control and data exchange. It was responsible for allocating the resource to the CPU and controlling references to it.
  • the virtual machine is invoked by a high level OS command (GET, PUT). Control is passed from the CPU to the virtual machine (denominated a channel) by a START I/O command and instructions under the aegis of the channel would execute until the I/O task was either completed, suspended, or aborted.
  • the channel in turn, would send series of subordinate commands (termed channel command words or CCW's) directing an attached I/O controller to perform preparatory (SEEK, SET SECTOR, STATUS) or executory acts (READ,WRITE.).
  • Clarke described a physical path connection involving a channel, a IOCU communicating with the channel on one side in an asynchronous relationship, and, selected DASDs on the other side.
  • the operating system of the CPU initiated the transfer by a START I/O instruction. This caused control to be relinquished to a series of channel commands (CCW's).
  • CCW's channel commands
  • a sequence or chain of channel commands was, in turn, sent from the CPU over the channel to the IOCU for selecting and accessing the storage DASD as well as effectuating the data movement across the interface.
  • the IOCU interpreted the CCW's and responded accordingly.
  • Yates shows encapsulation into a single message of a multi-function command for remote reception and execution by a second DASD.
  • Bass et al teaches the use of a pair of sequential commands issued by a CPU to control access to DASD data which is recorded in fixed block form (FBA).
  • the first command defines the boundaries of the DASD space accessible to the CPU while the second command specifies an operation and address.
  • each access in Bass outside of the prescribed storage boundaries on the storage DASD requires the series of commands to be restarted in the CPU.
  • an "array” has two meanings. The first refers to an indexed row and column formatted data type. The second connotes a type of synchronous arrangement of N DASD's in external storage susceptible of parallel operation. When transferring a data array between a CPU internal memory and a DASD array, it is desired to preserve the array "shape" or "stride". This means that the address intervals over which the next row or column in a row or column major ordered data array should be mapped are preserved.
  • Co-pending Brady et al European application 91304503.5, "METHOD AND MEANS FOR ACCESSING DASD ARRAYS WITH TUNED DATA TRANSFER RATE AND CONCURRENCY" (SA9-89-028) discloses a method for adjusting the data rate and concurrency with respect to read and write accesses by a CPU of at least one logical track having KN sequentially ordered blocks distributed and stored onto an external store in the form of an array of N DASD's.
  • each DASD physical track has a storage capacity of K blocks.
  • the array of N DASD's included control means for securing synchronous access to selectable ones of the N DASD's.
  • the method steps comprise (a) formatting the KN blocks onto N tracks of the N DASD's of the array in row major order K modulo M and in column major order K modulo MN, M being less than or equal to K; and (b) executing large and small access requests over the array such that each access involves a synchronous data exchange of b blocks at a time with b counterpart DASD's such that (N-b) DASD's are concurrently available for binding to another access request.
  • M is the parameter used for balancing the data rate and concurrency.
  • the invention provides a method of rule-based data transfer between the internal memory of a CPU and a cyclically operable storage device over a path including a channel and a device controller, said CPU including an operating system for initiating the data transfer, whereby a series of commands are sent to the channel and controller for execution, including commands for selecting and accessing the storage device and performing the data transfer, said method being characterised by the steps of: (a) transferring at least one rule from said CPU to said channel, said rule defining one or more internal memory address computations corresponding to at least one of said series of commands; and (b) said channel generating internal memory address arguments using said rule, and responsive to any access command in said series of commands, causing transferred data to be accessed at internal memory locations specified by said generated address arguments.
  • the cyclically operable storage device comprises an array of N DASD's, each DASD comprising recording tracks having a storage capacity of K blocks each, and said rule spfecifies an internal memory address stride of M, where M has the value 1 ⁇ M ⁇ K, to allow tuned transfer between the CPU and the DASD array.
  • stride is the number of sequential blocks on each DASD.
  • said device controller includes means for securing synchronous access to selectable ones of the N DASD's.
  • the invention also provides a data processing system comprising a CPU having an internal memory; an array of N DASD's, each DASD including a cyclic track recording medium, with each track having a storage capacity of K blocks; and means for synchronously accessing selectable ones of the DASD's and for randomly accessing the internal memory to transfer data blocks between the CPU and the DASD array, said CPU including an operating system for initiating the data transfer, whereby a series of commands are sent to the synchronous and random accessing means for execution, including commands for selecting and accessing the DASD array and performing the data transfer, said synchronous and random accessing means including means for transferring KN sequentially ordered data blocks distributed onto N DASD's such that each DASD stores K blocks in a single track, said KN blocks being formatted in row major order K modulo M and in column major order K modulo MN, where M is a parameter lying in the closed integer interval 1 ⁇ M ⁇ K; wherein the system further comprises:
  • the invention minimises CPU and path time occupancy in the transfer of data between the CPU internal memory and external storage. It also allows tuned data transfer between the CPU internal memory and an external store such as DASD, DASD strings, DASD arrays, tape, and the like, and can also preserve the address intervals into which data array rows and columns are transferred between CPU internal memory and an external store formed from an array of N DASD's.
  • a CPU implemented method and means for accessing an external storage sub-system in which rules defining computation of the internal memory addresses are distributed with the data to a virtual I/O machine termed a "channel".
  • the internal memory addresses are determined by computational rule by the channel. This ensures that the shape of the data transferred between internal memory addresses and external storage will remain invariant and time and occupancy required by the address list management associated with the prior art transfers is avoided.
  • At least one rule is transferred from the CPU to said channel, said rule defining one or more main memory address computations according to at least one of said series of channel commands (CCW's). Responsive to said rule, the channel generates address arguments, and responsive to any access command in the series of CCW's, transferred data is accessed at main memory locations locations specified by the generated address arguments.
  • CCW's series of channel commands
  • Figure 1 depicts a hierarchical CPU, channel, and external storage architecture environment.
  • Figure 2 shows the storage of data pages or blocks on a DASD and at internal memory locations separate from page/block control information currently fashioned to facilitate system management of storage.
  • Figure 3 depicts data blocks used in numerically intensive computation as stored on DASD and in internal memory where shape or stride is preserved.
  • Figure 4 sets forth the mapping of of an NK block logical track mapped onto a row track layout of a type 2H array of N DASD's.
  • Figure 5 shows a CCW chain of addresses according to the prior art.
  • FIG. 6 illustrates a representative format for Transfer Address Control Words (TACW) embodying the computational rule for determining successive internal memory addresses used in the data exchange between CPU internal memory and external storage.
  • TACW Transfer Address Control Words
  • the present invention can be conveniently practiced in a general purpose computer such as an IBM/360 or 370 architected CPU having the IBM MVS operating system.
  • An IBM/360 architected CPU is fully described in Amdahl et al, US Pat. 3,400,371, "Data Processing System", issued on Sept. 3, 1968.
  • MVS Microsoft-S/Extended Architecture System Programming Library: System Macros and Facilities
  • Volume 1 IBM publication GC28- 1150, "MVS/Extended Architecture System Programming Library: System Macros and Facilities", Volume 1. Details of standard MVS or other operating system services such lock management, sub-system invocation by interrupt or monitor, and the posting and waiting of tasks is omitted. These OS services are believed well appreciated by those skilled in the art.
  • CPU 1 includes a byte addressable RAM internal memory 9 and a page or block addressable RAM expanded store 11. Internal memory also includes program and data caches (not shown). Ordinarily, portions of executing applications and operating system software 3 are resident in internal memory 9. For execution the program processor 5 and channel processor 7 are coupled to memory over paths 13 and 17.
  • the channel 7 as a dedicated I/O processor may be implemented in real or in virtual in whole or in part.
  • channel 7 is in communication with external store 2 over path 19.
  • path 19 comprises separate data and control lines terminating in I/O Control UNIT 21 (IOCU). It should be appreciated that other equivalent path modalities may also be utilized such as a serial link within which the control and data paths are merged.
  • External store 2 may comprise conventional selectable DASD strings coupled to the channel 7 over demand/response interfaces by way of at least one path having buffered staged controllers as shown for example in Clark et al, Beausoleil, US Pat. 3,336,582, Boehner et al US Pat. 3,564,502., and Luiz et al, US Pat. 4,207,609.
  • external store 2 may comprise a DASD array.
  • IOCU 21 attaches N DASD's 27, 29, 31, 33, 35 directly over a control and addressing path 23 and indirectly over a data path including path 25, cache/buffer 37 and control and data paths 39 and 41.
  • the data mapping between CPU internal memory and external storage will assume a type 2H N DASD array for external storage, as described in the copending Brady et al application.
  • an "N DASD array” is any arrangement of synchronized DASD's which may be selectively accessed in parallel i.e. accessed in an identical manner at the same time. Synchronous behavior requires N DASDs to rotate at the same rpm, have the same angular offset, and be accessed in an identical manner at the same time.
  • the formatting and subsequent read/write accessing of an array proceeds by copying/inserting values in consecutive positions on either a row or a column basis. If the operation is performed in a column direction, it is designated as being performed in "column major order”. Likewise, if performed in a row direction, it is designated as being performed in "row major order”. Next, the mapping is done from the logical "array" to the physical store (i.e.ganged group of DASDs).
  • indexed positions of blocks in the array are mappable onto "closed integer intervals".
  • a "closed integer interval” is one over which an index variable can assume all INTEGER interval values including the end points.
  • the "Type 2H DASD array” is a version of the level 4 and 5 arrays as described by Patterson et al, "A Case for Redundant Arrays of Inexpensive Disks (RAID)", p109-116, ACM SIGMOD Conference, Chicago Illinois, June 1-3, 1988, and modified in the co-pending Brady et al. application.
  • the type 2 array improves performance with respect to small read and write accesses. This is achieved by storing blocks along the column extent so that in a first time slot (DASD sector 1) blocks 1 to N can respectively be stored on DASD 1 to N while in the second time slot (DASD sector 2) blocks N+1 to 2N are stored etc.
  • blocks [(K-1)]*N+1 to KN are stored on corresponding devices.
  • the Patterson fourth level permits access to DASD individually. This means that small transfers can occupy few DASDs while large transfers can also be accessed synchronously across N devices.
  • the accessing/addressing problem is that of mapping NK blocks of an arbitrary logical track onto K blocks per physical track over N DASDs.
  • the K block contents of a physical track can be mapped onto a time line such as that defined by a single DASD disk rotation.
  • the contents of each block position on the time line or counterpart track extent constitute K column entries for the ith row.
  • the contents of N blocks occupying that sector over N DASDs constitute N row entries for the jth column.
  • the array appears as a single logical store providing data at N-1 times the data rate of a single DASD and having N-1 times the capacity of the native device.
  • the model assumes that of the NK blocks per logical track, K blocks are dedicated to parity spanning a predetermined number of the (N-1)K data blocks.
  • the inherent redundancy of DASDs in an array permits the logical store to remain operable, even in degraded mode, over a longer interval (mean time between failures) than the MBTF interval of single DASD.
  • a CPU's relationship to a DASD in a CPU of the IBM System 360/370 type begins when the CPU 1 invokes the START I/O instruction.
  • This instruction serves to establish a connection between the CPU 1 and an addressed DASD and the execution of a channel program with the DASD.
  • the invocation of the START I/O instruction causes control to be relinquished to a series of channel commands.
  • This series or chain of channel commands (CCW's) is, in turn, sent over the channel path 19 to the IOCU 21 unit for selecting and accessing the DASD subset (27-35) of interest and for performing any data movement across the interfaces.
  • each channel program consists of a sequential list of operations resident in the CPU main memory. In the prior art, it has used a chained list of data addresses in the form of CCW's to also define locations of the data objects to be moved or transferred.
  • the transmission to and execution at IOCU 21 of the commands from the CCW's takes place only after initial connection between the CPU 1 and the IOCU takes place.
  • For each operation (CCW) in the channel program one or more counterpart operations are required either at the IOCU or DASD level over an active connection.
  • the list or CCW sequence may be discontinuously executed (segmented).
  • the first active connection is denominated as an initial selection sequence. This sequence is invoked with a CPU START I/O operation in which an initial path is set up both electrically and logically in terms of DASD address (virtual/real) and DASD status (available/busy).
  • the next 16 active connection relates to that of CCW command transfer and execution.
  • a control CCW such as a SEEK requires physical positioning or activity at the DASD.
  • the IOCU in response to receipt of a control CCW, can execute the CCW in disconnected mode. This means that the IOCU disconnects from the channel while executing the indicated operation. The IOCU does not require any more channel activity until it reconnects to said channel.
  • a IOCU After a IOCU has received a SEEK CCW and the parameters (target address) it disconnects for 10 milliseconds or more. 10 milliseconds is an average time it takes to dispatch an accessing arm of a DASD in order to arrive at the tracks of a cylinder of interest. During this "dead time" both the channel and the IOCU are free to establish other connections.
  • CCW's involving the movement or transfer of data between the channel and the DASD such as READ or WRITE CCW's require the IOCU to remain connected to the channel in order to perform the data transfer.
  • each page/record/block is stored on DASD (external storage) contiguous to its descriptor.
  • DASD external storage
  • the descriptor may be stored non-contiguously. This is to facilitate system managed storage of data with respect to allocation, recovery, security, and aging out etc.
  • rule means a computation direction or accessing step.
  • rules are processed by the channel and direct the data transfer to alternate between transferring pages to and from internal memory address A and the descriptors to and from internal memory address B as set out in Figure 2.
  • Rules are defined to the channel via a list of Transfer Address Control Words (TACW) as depicted in Figure 6.
  • the list begins with a header identifying the number of TACW's, the total transfer length of the list, and a stated number of TACW's.
  • Each TACW contains a memory address for data transfer, a transfer count, specification of the memory address following transfer, and the index of the next TACW for the channel to process.
  • next TACW index is useful if the TACW's themselves are executed in other than a repetitive top-to-bottom sequence.
  • step (2) a single construct is defined containing the values (a) memory address (A), (b) block (C, 4096), (c) stride (K, 64), and (d) cycle (N, 4).
  • the preceding example would proceed as described through step (7).
  • the channel On receipt of the first data byte from the IOCU, the channel would proceed with the following steps:

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EP91305185A 1990-06-22 1991-06-10 Verfahren und Anordnung zur auf Regeln beruhende Datenübertragung Expired - Lifetime EP0465014B1 (de)

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JPH04233056A (ja) 1992-08-21
EP0465014A3 (en) 1992-07-01
EP0465014B1 (de) 1996-03-20
US5379385A (en) 1995-01-03
JPH0776950B2 (ja) 1995-08-16
DE69118029D1 (de) 1996-04-25

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