EP0464632A3 - Parallel data processing apparatus with signal skew compensation - Google Patents

Parallel data processing apparatus with signal skew compensation Download PDF

Info

Publication number
EP0464632A3
EP0464632A3 EP19910110561 EP91110561A EP0464632A3 EP 0464632 A3 EP0464632 A3 EP 0464632A3 EP 19910110561 EP19910110561 EP 19910110561 EP 91110561 A EP91110561 A EP 91110561A EP 0464632 A3 EP0464632 A3 EP 0464632A3
Authority
EP
European Patent Office
Prior art keywords
processing apparatus
data processing
parallel data
skew compensation
signal skew
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP19910110561
Other versions
EP0464632B1 (en
EP0464632A2 (en
Inventor
Hideki Yoshizawa
Hideki Kato
Hiroki Iciki
Daiki Masumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of EP0464632A2 publication Critical patent/EP0464632A2/en
Publication of EP0464632A3 publication Critical patent/EP0464632A3/en
Application granted granted Critical
Publication of EP0464632B1 publication Critical patent/EP0464632B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
EP91110561A 1990-06-28 1991-06-26 Parallel data processing apparatus and method with signal skew compensation Expired - Lifetime EP0464632B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP171069/90 1990-06-28
JP17106990 1990-06-28
JP2171069A JP2507677B2 (en) 1990-06-28 1990-06-28 Distributed data processor

Publications (3)

Publication Number Publication Date
EP0464632A2 EP0464632A2 (en) 1992-01-08
EP0464632A3 true EP0464632A3 (en) 1993-08-25
EP0464632B1 EP0464632B1 (en) 1999-12-08

Family

ID=15916461

Family Applications (1)

Application Number Title Priority Date Filing Date
EP91110561A Expired - Lifetime EP0464632B1 (en) 1990-06-28 1991-06-26 Parallel data processing apparatus and method with signal skew compensation

Country Status (6)

Country Link
US (1) US5220660A (en)
EP (1) EP0464632B1 (en)
JP (1) JP2507677B2 (en)
AU (1) AU636768B2 (en)
DE (1) DE69131822T2 (en)
FI (1) FI913114A (en)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5577214A (en) * 1992-05-18 1996-11-19 Opti, Inc. Programmable hold delay
US5572722A (en) * 1992-05-28 1996-11-05 Texas Instruments Incorporated Time skewing arrangement for operating random access memory in synchronism with a data processor
JPH0793386A (en) * 1993-09-28 1995-04-07 Fujitsu Ltd Lsi package designing system
US5467465A (en) * 1993-11-17 1995-11-14 Umax Data System Inc. Two clock method for synchronizing a plurality of identical processors connected in parallel
JPH07248847A (en) * 1994-03-11 1995-09-26 Fujitsu Ltd Method and device for adjusting clock signal
US5768620A (en) * 1996-04-09 1998-06-16 International Business Machines Corporation Variable timeout method in a missing-interrupt-handler for I/O requests issued by the same operating system
US6115769A (en) * 1996-06-28 2000-09-05 Lsi Logic Corporation Method and apparatus for providing precise circuit delays
US6294937B1 (en) 1999-05-25 2001-09-25 Lsi Logic Corporation Method and apparatus for self correcting parallel I/O circuitry
US6557066B1 (en) 1999-05-25 2003-04-29 Lsi Logic Corporation Method and apparatus for data dependent, dual level output driver
DE10006236C2 (en) * 2000-02-11 2001-12-20 Infineon Technologies Ag Arrangement for generating signal pulses with defined pulse lengths in a module with a BIST function
JP3628265B2 (en) * 2001-02-21 2005-03-09 株式会社半導体理工学研究センター Multiprocessor system unit
KR100414943B1 (en) * 2001-12-28 2004-01-16 엘지전자 주식회사 Apparatus and Method for Distribution Clock in Multiple Processing System based on Compact Peripheral Component Interconnect
US7043649B2 (en) * 2002-11-20 2006-05-09 Portalplayer, Inc. System clock power management for chips with multiple processing modules
US7698490B2 (en) * 2005-12-21 2010-04-13 Nvidia Corporation Passive USB power configuration switching
US7414550B1 (en) 2006-06-30 2008-08-19 Nvidia Corporation Methods and systems for sample rate conversion and sample clock synchronization
US9209792B1 (en) 2007-08-15 2015-12-08 Nvidia Corporation Clock selection system and method
US8327173B2 (en) * 2007-12-17 2012-12-04 Nvidia Corporation Integrated circuit device core power down independent of peripheral device operation
US9088176B2 (en) * 2007-12-17 2015-07-21 Nvidia Corporation Power management efficiency using DC-DC and linear regulators in conjunction
US9411390B2 (en) 2008-02-11 2016-08-09 Nvidia Corporation Integrated circuit device having power domains and partitions based on use case power optimization
US8762759B2 (en) * 2008-04-10 2014-06-24 Nvidia Corporation Responding to interrupts while in a reduced power state
US9423846B2 (en) 2008-04-10 2016-08-23 Nvidia Corporation Powered ring to maintain IO state independent of the core of an integrated circuit device
JP5604799B2 (en) * 2009-03-06 2014-10-15 日本電気株式会社 Fault tolerant computer
JP5800752B2 (en) * 2012-04-25 2015-10-28 三菱電機株式会社 Signal source synchronization circuit
US9395799B2 (en) 2012-08-09 2016-07-19 Nvidia Corporation Power management techniques for USB interfaces
US9471395B2 (en) 2012-08-23 2016-10-18 Nvidia Corporation Processor cluster migration techniques
US20140062561A1 (en) 2012-09-05 2014-03-06 Nvidia Corporation Schmitt receiver systems and methods for high-voltage input signals
EP2775655B1 (en) * 2013-03-08 2020-10-28 Pro Design Electronic GmbH Method of distributing a clock signal, a clock distributing system and an electronic system comprising a clock distributing system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4063308A (en) * 1975-06-27 1977-12-13 International Business Machines Corporation Automatic clock tuning and measuring system for LSI computers
US4847516A (en) * 1986-11-26 1989-07-11 Hitachi, Ltd. System for feeding clock signals
US4868522A (en) * 1988-12-13 1989-09-19 Gazelle Microcircuits, Inc. Clock signal distribution device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4769558A (en) * 1986-07-09 1988-09-06 Eta Systems, Inc. Integrated circuit clock bus layout delay system
US4805196A (en) * 1987-04-29 1989-02-14 Gte Laboratories Incorporated Line delay compensation for digital transmission systems utilizing low power line drivers
US5086500A (en) * 1987-08-07 1992-02-04 Tektronix, Inc. Synchronized system by adjusting independently clock signals arriving at a plurality of integrated circuits
US5041966A (en) * 1987-10-06 1991-08-20 Nec Corporation Partially distributed method for clock synchronization

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4063308A (en) * 1975-06-27 1977-12-13 International Business Machines Corporation Automatic clock tuning and measuring system for LSI computers
US4847516A (en) * 1986-11-26 1989-07-11 Hitachi, Ltd. System for feeding clock signals
US4868522A (en) * 1988-12-13 1989-09-19 Gazelle Microcircuits, Inc. Clock signal distribution device

Also Published As

Publication number Publication date
EP0464632B1 (en) 1999-12-08
AU7927391A (en) 1992-03-26
FI913114A (en) 1991-12-29
DE69131822D1 (en) 2000-01-13
JP2507677B2 (en) 1996-06-12
JPH0460742A (en) 1992-02-26
DE69131822T2 (en) 2000-04-06
FI913114A0 (en) 1991-06-26
EP0464632A2 (en) 1992-01-08
US5220660A (en) 1993-06-15
AU636768B2 (en) 1993-05-06

Similar Documents

Publication Publication Date Title
EP0464632A3 (en) Parallel data processing apparatus with signal skew compensation
EP0343930A3 (en) Data signal processing apparatus
GB2250362B (en) Parallel data processing system
GB2251098B (en) Apparatus for processing data
EP0306662A3 (en) Apparatus for skew compensating signals
GB9005030D0 (en) Image data processing
EP0454355A3 (en) Image signal processing apparatus
GB2244622B (en) Image signal processing
GB9112754D0 (en) Data processing apparatus
EP0473374A3 (en) Image data processing
EP0454417A3 (en) Image signal processing apparatus
EP0469836A3 (en) Image signal processing apparatus
EP0486143A3 (en) Parallel processing of data
EP0484981A3 (en) Image data processing apparatus
EP0528695A3 (en) Data processing apparatus
EP0452064A3 (en) Apparatus for detecting digital data
GB2243474B (en) Data processing apparatus with self-repeat function
EP0438316A3 (en) Image data processing apparatus
EP0314516A3 (en) Document data processing apparatus
EP0498454A3 (en) Signal processing apparatus
GB9117187D0 (en) Data processing apparatus
EP0473375A3 (en) Image signal processing
EP0459389A3 (en) Image signal processing apparatus
EP0503891A3 (en) Signal processing apparatus
GB9200048D0 (en) Digital signal processing apparatus

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): DE FR GB

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): DE FR GB

17P Request for examination filed

Effective date: 19940218

17Q First examination report despatched

Effective date: 19970813

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 19991208

REF Corresponds to:

Ref document number: 69131822

Country of ref document: DE

Date of ref document: 20000113

EN Fr: translation not filed
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
REG Reference to a national code

Ref country code: GB

Ref legal event code: IF02

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20060621

Year of fee payment: 16

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20060622

Year of fee payment: 16

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20070626

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20080101

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20070626