EP0447919A2 - Steuereinrichtung für eine Bildpunktmatrixanzeige - Google Patents

Steuereinrichtung für eine Bildpunktmatrixanzeige Download PDF

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Publication number
EP0447919A2
EP0447919A2 EP91103736A EP91103736A EP0447919A2 EP 0447919 A2 EP0447919 A2 EP 0447919A2 EP 91103736 A EP91103736 A EP 91103736A EP 91103736 A EP91103736 A EP 91103736A EP 0447919 A2 EP0447919 A2 EP 0447919A2
Authority
EP
European Patent Office
Prior art keywords
voltage
signal
drivers
drive circuit
supplying
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP91103736A
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English (en)
French (fr)
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EP0447919B1 (de
EP0447919A3 (en
Inventor
Jean-Frederic Clerc
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Stanley Electric Co Ltd
Original Assignee
Stanley Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stanley Electric Co Ltd filed Critical Stanley Electric Co Ltd
Publication of EP0447919A2 publication Critical patent/EP0447919A2/de
Publication of EP0447919A3 publication Critical patent/EP0447919A3/en
Application granted granted Critical
Publication of EP0447919B1 publication Critical patent/EP0447919B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3681—Details of drivers for scan electrodes suitable for passive matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3692—Details of drivers for data electrodes suitable for passive matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation

Definitions

  • This invention relates to a dot matrix display, and more particularly to a dot matrix display drive circuit capable of using a low voltage segment driver.
  • a dot matrix LCD is driven by common drivers on row side and by segment (individual) drivers on segment side.
  • pixels aligned in one direction form a row and are given with a set of display data at a same time.
  • the direction of row may either along x direction or along y direction, but the description hereinbelow will be made assuming that the row is along the x direction (horizontal direction).
  • Fig. 2 shows signals for two successive fields supplied to the matrix from the common driver and from the segment driver in the conventional addressing mode, in part(A) and part(B), respectively.
  • part (C) of Fig. 2 shows a combined effective voltage which in applied to the pixel (picture element) at each element of the LCD matrix.
  • the common driver supplies a voltage waveform signal formed of 4 levels of voltage V1, V2, V5 and -VEE as shown in part (A) of Fig. 2, to each row of the matrix.
  • the maximum voltage difference V1+VEE is of the order of about 25-40 volts.
  • the segment driver supplies a voltage waveform signal formed of 4 levels of voltage V1, V3, V4 and -VEE as shown in part (B) of Fig. 2, to each column of the matrix.
  • the voltage difference in each field e.g. V1-V3 is of the order of about 3 volts.
  • Cross-hatched region represents that any voltage in the region may be applied.
  • the voltages are changed widely, for example by about 25-40 volts.
  • voltages of V2 and -VEE are applied to the row and voltages of V1 and V3 are applied to the column depending on the state of display.
  • voltages of V1 and V5 are applied to the row and voltages of V4 and -VEE are applied to the column depending on the state of display.
  • the combined signal VPIXEL which the pixel receives takes the peak amplitude during the selection time ⁇ R.
  • the peak amplitude becomes (VSCAN + ⁇ VDATA) in the first field, and -(VSCAN + ⁇ VDATA) in the second field.
  • the coefficient ⁇ is 1 when the pixel is "on” and is -1 when the pixel is "off”.
  • the peak amplitude (VSCAN + VDATA) corresponding to the on state is equal to the maximum voltage difference of the power source.
  • the combined signal which the pixel receives is VDATA or -VDATA except the selection frame ⁇ R, the absolute value of which is constant.
  • VDATA except the selection time is equal to V1-V2, V2-V3, V4-V5, or V5-(-VEE).
  • the dot matrix display is driven by the six voltages as described above.
  • both of the common driver and the segment driver should supply signals having a high peak amplitude.
  • the peak amplitude of the common driver is V1-(-VEE).
  • the peak amplitude of the segment driver is also V1-(-VEE). Therefore, each common driver and each segment driver should have the maximum operable voltage of V1-(-VEE) or above. In the case of highly multiplied dot matrix, the voltage V1-(-VEE) is of the order of 25 to 40 volts.
  • Both the common driver and the segment driver generate four voltage levels. Each output stage uses one switch for each voltage level, and include four high voltage, heavy current switches in total.
  • the power source is simple.
  • the six levels of voltage to be supplied are fixed in an appropriate voltage range from V1 (usually +5 volts) to -VEE (usually 20 to 35 volts).
  • the power source should supply high peak currents at the respective voltages of V1, V2, V3, V4, V5 and -VEE (typically about 1 A in a ten inch display), and the stabilization should be 1 % or less for the respective levels of voltage.
  • the cost of the driver circuit occupies an important part of the total cost of the display device.
  • An object of this invention is to provide a drive circuit adapted for dot matrix display of low manufacturing costs.
  • CMOS driver Ordinary low voltage (of the order of ⁇ 3 volts) CMOS driver is used for the segment driver.
  • the segment driver is formed of a low voltage circuit and the common driver is formed of a high voltage circuit.
  • the two circuits are coupled logically by photo coupling means, and are isolated in dc sense.
  • CMOS circuits are used in the segment side, and the manufacturing cost thereof is reduced.
  • the number of output transistors can be reduced to about a half either in the common driver and the segment driver.
  • the number of transistors required to generate output voltages of one way is reduced from four to two.
  • the size of the semiconductor chip can be greatly reduced. Not only the cost can be reduced, mounting by TAB or COG can be made easy.
  • Fig. 1 is a block diagram showing a schematic structure of a dot matrix LCD device driven by a floating power source.
  • Fig. 2 is voltage waveform diagrams showing the addressing mode of the conventional dot matrix LCD by a six-level power source.
  • Figs. 3A and 3B are circuit diagram of a floating power source of a dot matrix LCD and a voltage waveform diagram produced in the circuit of Fig. 3A.
  • Figs. 4A, 4B and 4C are circuit diagrams showing a common driver.
  • Fig. 5 is waveform diagrams for illustrating the operation of the common driver.
  • Fig. 6A and 6B are circuit diagrams illustrating a segment driver.
  • Fig. 1 shows an outline of a matrix LCD drive circuit according to a general embodiment of this invention.
  • a dot matrix type liquid crystal display 1 has its rows driven by common drivers 2a and 2b and its columns driven by segment drivers 3a and 3b.
  • the common drivers 2a and 2b receive voltage signals from a level converter 5, and also receive control signals from an LCD controller 4 through photo coupling stage 6.
  • the photo coupling stage 6 isolate the LCD controller 4 and the common drivers 2a and 2b in dc sense, and couples them logically.
  • the level converter 5 is connected to a 6 level voltage source 11 which is similar to the conventional one, through a bridge and buffer stage 8.
  • the bridge and buffer stage 8 receives three voltage levels of +VSCAN, ground, and -VSCAN from the 6 level voltage source 11 and supplies five voltage levels of VSCAN, VSCAN-VLOGIC, ground -VLOGIC and -VSCAN.
  • the control signal from the LCD controller 4 are also supplied to the segment drivers 3a and 3b and the level converter 5.
  • the segment drivers 3a and 3b and the LCD controller 4 are low voltage circuits, and can be formed of low price, low voltage semiconductor circuits.
  • the supply voltages for these circuits are four levels of VDATA, -VDATA, -VLOGIC and ground (VG). These voltage levels are all included in the range from +5 V to - 5 V.
  • the common drivers 2a and 2b operate at high voltages.
  • the voltage source for the common driver is floating.
  • the common driver receives as the source voltage, three signals of F"1", F0LOGIC, and F"0".
  • the voltage differences between these three signals are kept constant, and are converted periodically and totally by a level converter 5 constructed of high voltage gates of VMOS or DMOS structures.
  • Photo coupling means 6 is used to perform the level conversion of these logic signals supplied to the common drivers 2a and 2b without noise.
  • a photo-coupling circuit may be formed of a voltage dividing circuit for establishing desired voltages, F"1" and L0LOGIC, and photo-excited switch means, such as photo-couplers, for extracting desired voltage.
  • the voltages which the segment drivers 3a and 3b should treat are only two low level voltages, VDATA and -VDATA, and the LCD controller 4 can be made to operate also at low voltages
  • the common drivers 2a and 2b have a floating power source, and simultaneously receive the level converted logic signals.
  • the voltage levels which the common driver 2a and 2b should treat are only two, F"1" and F"0".
  • the power source circuit corresponds, in the structure of Fig. 1, to the combination of the 6-level power source 11, the bridge and buffer stage 8 and the level converter 5, and supplies currents to the common drivers 2a and 2b, the segment drivers 3a and 3b, and the LCD controller 4.
  • FIG. 3A A structure of the power source circuit is shown in Fig. 3A.
  • a power source 11 similar to the conventional one supplies six constant voltages, VSCAN, VDATA, ground(VG), -VDATA, -VLOGIC and -VSCAN.
  • VDATA, VG, -VDATA and -VLOGIC are derived as low voltage levels and directly supplied to the segment drivers 3a and 3b and the LCD controller 4.
  • the bridge and buffer stage 8 which is formed of a resistance bridge and the associated buffers similar to the conventional one supply two intermediate levels VSCAN-VLOGIC and -VLOGIC. Only the logics of the common driver use these intermediate voltages. Therefore, these levels do not need to be adjusted precisely, and the required currents are very low (of the order of several mA).
  • a group of level converting elements in the level converter 5 realize the following three signals.
  • VMOS or DMOS switches 13 are periodically activated by the PHASE SHIFT signal supplied from the LCD controller 4.
  • F"1" VSCAN or VG (depending on the PHASE SHIFT signal)
  • F0LOGIC F"1"-VLOGIC
  • F"0" F"1"-VSCAN
  • the common driver circuit is shown in Figs. 4A, 4B and 4C.
  • a diver circuit for driving six rows is shown.
  • Fig. 4A shows a schematic circuit configuration
  • Fig. 4B shows the relation with the control signal
  • Fig. 4C is an enlarged diagram of a portion shown by a broken line in Fig. 4B.
  • the common driver is constructed of three stages.
  • the first stage is an ordinary shift register which is operated by two signals, DATA IN* and COMMON CLOCK* (the waveforms on which before level conversion are shown in Fig. 5).
  • the second stage is an inverter stage controlled by PHASE SHIFT* (the waveform of which before the level conversion is shown in Fig. 5).
  • This stage supplies six signals, Gate rowi* (i is 1 to 6,) which are used in the third stage.
  • the third stage is constructed of six output blocks, each having a structure as shown in Fig. 4C.
  • Fig. 5 shows the general relation of all the signals described hereinabove.
  • the PHASE SHIFT (or PHASE SHIFT*) is shown at the upper most part of Fig. 5. During the first field, the signal PHASE SHIFT is in the state "1", and during the second field, the signal PHASE SHIFT is in the state "0".
  • the next part shows the signal DATA IN (or DATA IN*).
  • the signal DATA IN is a signal pulse at the beginning of each field. This is a single “1" as the first data which initialize the shift resister.
  • the third part shows the signal ENABLE (or ENABLE*).
  • the signal ENABLE keeps the state of "0" (corresponding to the high impedance of all the common drivers) from the (N+1)th pulse of COMMON CLOCK to the first pulse of the next COMMON CLOCK.
  • the fourth part shows the signal COMMON CLOCK (or COMMON CLOCK*).
  • the signal COMMON CLOCK pushes out the signals in the shift register.
  • the signal COMMON CLOCK includes N+1 pulses.
  • the single “1”s are pushed out to make all the data in the shift register "0".
  • the fifth and the sixth parts show the common driver outputs corresponding to the succeeding two rows (for example, the first and the second rows).
  • the driver output becomes F"1" during the selection time and becomes F"0" during the non-selection time.
  • the common driver output becomes F"0" during the selection time and becomes F"1" during the non-selection time.
  • the table at the lower part of the figure represents the levels of the shift registers, and shows the respective states of the Gate Row signals supplied to the output state.
  • the signal ENABLE is “0". Therefore, when the PHASE SHIFT signal is switched from “0" to "1” or from “1” to "0" to activate the total change of the signals F"1", F0LOGIC and F"0" for the common driver power source, all the common drivers become of high impedance. Therefore, the common drivers are protected from the polarity inversion. Namely, we can know an important fact that when the level conversion is being performed, currents are not supplied.
  • the effective voltage applied to the cells is not varied, the level conversion does not require much current and the polarity inversion of the drivers has no risk.
  • Fig. 6 shows a structure of the segment driver.
  • a segment driver has four stages of low voltage circuits.
  • the block in the output driver 18 for each segment is formed of a pair of CMOS transistors directly driven by the signal GATE SEGMENT supplied in the third stage as shown in Fig. 6B.
  • the manufacturing costs of a dot matrix display can be reduced.
  • a high voltage stage and a low voltage stage are electrically isolated and logically coupled by a photo coupling stage, and hence the low voltage circuit does not require a high withstand voltage.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal (AREA)
EP19910103736 1990-03-13 1991-03-12 Steuereinrichtung für eine Bildpunktmatrixanzeige Expired - Lifetime EP0447919B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP61934/90 1990-03-13
JP6193490A JP2634680B2 (ja) 1990-03-13 1990-03-13 ドットマトリックスディスプレイ装置

Publications (3)

Publication Number Publication Date
EP0447919A2 true EP0447919A2 (de) 1991-09-25
EP0447919A3 EP0447919A3 (en) 1992-01-08
EP0447919B1 EP0447919B1 (de) 1995-07-19

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP19910103736 Expired - Lifetime EP0447919B1 (de) 1990-03-13 1991-03-12 Steuereinrichtung für eine Bildpunktmatrixanzeige

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EP (1) EP0447919B1 (de)
JP (1) JP2634680B2 (de)
DE (1) DE69111274T2 (de)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0721137A1 (de) * 1994-07-14 1996-07-10 Seiko Epson Corporation Stromversorgungsschaltung, flüssigkristallanzeigevorrichtung und elektronisches gerät
EP0726558A1 (de) * 1995-02-11 1996-08-14 Samsung Electronics Co., Ltd. Treiberschaltung für eine Flüssigkristallanzeige mit Dünnfilmtransistoren
WO2004003883A1 (en) * 2002-06-27 2004-01-08 Stmicroelectronics S.R.L. System for driving rows of a liquid crystal display
CN100345034C (zh) * 2004-09-08 2007-10-24 友达光电股份有限公司 内建直流－直流转换器的平面显示面板

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4413256A (en) * 1980-02-21 1983-11-01 Sharp Kabushiki Kaisha Driving method for display panels
DE3212863C2 (de) * 1981-04-07 1986-07-10 Seiko Instruments and Electronics Ltd., Tokio/Tokyo Flüssigkristall-Anzeigeeinrichtung
EP0216168A2 (de) * 1985-08-29 1987-04-01 Canon Kabushiki Kaisha Verfahren zum Steuern einer Anzeigetafel
WO1987005429A1 (en) * 1986-03-10 1987-09-11 Alcatel N.V. Liquid crystal display having improved electrode drive circuitry
JPS63262622A (ja) * 1987-04-21 1988-10-28 Nec Corp 液晶素子の駆動法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4413256A (en) * 1980-02-21 1983-11-01 Sharp Kabushiki Kaisha Driving method for display panels
DE3212863C2 (de) * 1981-04-07 1986-07-10 Seiko Instruments and Electronics Ltd., Tokio/Tokyo Flüssigkristall-Anzeigeeinrichtung
EP0216168A2 (de) * 1985-08-29 1987-04-01 Canon Kabushiki Kaisha Verfahren zum Steuern einer Anzeigetafel
WO1987005429A1 (en) * 1986-03-10 1987-09-11 Alcatel N.V. Liquid crystal display having improved electrode drive circuitry
JPS63262622A (ja) * 1987-04-21 1988-10-28 Nec Corp 液晶素子の駆動法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 13, no. 80 (P-832), 23 February 1989; & JP - A - 63262622 (NEC) 28.10.1988 *

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0721137A1 (de) * 1994-07-14 1996-07-10 Seiko Epson Corporation Stromversorgungsschaltung, flüssigkristallanzeigevorrichtung und elektronisches gerät
EP0721137A4 (de) * 1994-07-14 1997-08-13 Seiko Epson Corp Stromversorgungsschaltung, flüssigkristallanzeigevorrichtung und elektronisches gerät
US5859632A (en) * 1994-07-14 1999-01-12 Seiko Epson Corporation Power circuit, liquid crystal display device and electronic equipment
EP0726558A1 (de) * 1995-02-11 1996-08-14 Samsung Electronics Co., Ltd. Treiberschaltung für eine Flüssigkristallanzeige mit Dünnfilmtransistoren
WO2004003883A1 (en) * 2002-06-27 2004-01-08 Stmicroelectronics S.R.L. System for driving rows of a liquid crystal display
CN100373440C (zh) * 2002-06-27 2008-03-05 St微电子公司 驱动液晶显示器行的系统
CN100345034C (zh) * 2004-09-08 2007-10-24 友达光电股份有限公司 内建直流－直流转换器的平面显示面板

Also Published As

Publication number Publication date
JP2634680B2 (ja) 1997-07-30
JPH03261991A (ja) 1991-11-21
EP0447919B1 (de) 1995-07-19
DE69111274T2 (de) 1996-03-21
DE69111274D1 (de) 1995-08-24
EP0447919A3 (en) 1992-01-08

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