EP0441956A1 - Reduction du courant d'obscurite dans des dispositifs a couplage de charge - Google Patents

Reduction du courant d'obscurite dans des dispositifs a couplage de charge

Info

Publication number
EP0441956A1
EP0441956A1 EP19900914459 EP90914459A EP0441956A1 EP 0441956 A1 EP0441956 A1 EP 0441956A1 EP 19900914459 EP19900914459 EP 19900914459 EP 90914459 A EP90914459 A EP 90914459A EP 0441956 A1 EP0441956 A1 EP 0441956A1
Authority
EP
European Patent Office
Prior art keywords
gate
pixel
transfer
ccd
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19900914459
Other languages
German (de)
English (en)
Inventor
Bruce Burkey
Wing-Chyi Chang
Teh-Hsuang Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Eastman Kodak Co
Original Assignee
Eastman Kodak Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Eastman Kodak Co filed Critical Eastman Kodak Co
Publication of EP0441956A1 publication Critical patent/EP0441956A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/148—Charge coupled imagers
    • H01L27/14831—Area CCD imagers

Definitions

  • This invention relates to a method and apparatus for reducing dark current in charge coupled devices (CCDs).
  • a true two phase CCD refers to a device in which there are two physical gates per pixel, with each gate having both a transfer and a storage region formed in the silicon under it. There are two voltage phase lines ⁇ , and ⁇ .
  • the charge coupling concept is used in frame transfer and interline transfer CCD image sensing devices.
  • An example of a frame transfer area image sensor 10 is shown in FIG. 1.
  • FIG. la A schematic cross-section for a true two phase CCD is shown in FIG. la.
  • a true two phase CCD is described in detail in commonly assigned U.S. Patent 4,613,402 to Losee and Lavine.
  • a true two phase CCD has storage and transfer regions beneath each phase gate.
  • the phase gates are labeled by either first or second polycrystalline silicon (poly-Si), and the transfer and storage regions by regions (1) and (2) for ⁇ , and (3) and (4) for y •
  • poly-Si polycrystalline silicon
  • n-channel devices will be considered. In such devices the majority carriers are holes and the minority or signal carriers are electrons. This invention applies equally to p-buried channel devices.
  • the buried channel is formed by an n-type doping in a p-type substrate or in a p— ell in an n—type substrate.
  • the transfer and storage buried channel regions are differentiated by less or more of the n-buried channel doping, respectively.
  • U.S. Patent 4,613,402 discloses a detailed procedure for making true two phase CCD devices.
  • the electrostatic potential band diagram through one of the phase gate electrodes, the buried channel and the substrate of an image pixel is shown in FIG. 2.
  • the buried channel is shown reverse biased and with a positive gate voltage, Vg, to create a depleted surface.
  • the Fermi level (E F ) although not shown, will be near the middle of the band gap at the oxide-Si interface.
  • dark current arises from three main sources: (1) generation from a mid— ap state resulting from either the disrupted lattice or an impurity at a depleted Si-Si0 2 interface, (2) generation in the depletion region as a result of an impurity or defect with a mid-gap state and (3) diffusion of minority carriers to the buried channel from the substrate. All three sources result in spurious charges being collected as signal in the buried channel.
  • the mechanism for dark current generation both at the surface and in the depletion region is illustrated in FIG.
  • a generation site emits an electron (negative charge) into the conduction band in the buried channel and a hole (positive charge) into the valence band.
  • the electron is captured by the buried channel as dark signal, and if the spatial region where the hole is emitted to the valence band is depleted of majority carriers then the holes will migrate away from their point of generation thus leaving the region depleted of majority carriers.
  • a hole generated in the depletion region is driven to the substrate.
  • a hole generated at the surface goes laterally to a channel stop region, again leaving the surface depleted of majority carriers.
  • a method of reducing dark current in a buried channel CCD in which a pixel is defined by at least two adjacent electrodes comprising the step of: during the operation of such CCD simultaneously placing all electrodes in the accumulation mode of operation.
  • dark current generation is very effectively suppressed by holding all phase gates in the accumulation mode of operation for all but the time needed for the actual transfer of charge from one CCD stage to the next.
  • a voltage must be applied that attracts majority carriers to the silicon-Si0 2 interface.
  • the majority carriers are holes and for p-channel devices the majority carriers are electrons, therefore the appropriate voltages for the accumulation mode are negative and positive for n— and p-buried channel devices, respectively.
  • the true two phase architecture is ideally suited to this mode of operation.
  • the channel potentials beneath the barrier and storage regions must be chosen properly to avoid mixing of adjacent pixel signals when operating in the accumulation mode.
  • This invention is suitable for use in frame transfer CCD imagers during both integration and readout. It can also be applied to interline transfer CCD imagers during readout of the optically generated signal.
  • An advantage of the accumulation mode of operating a frame transfer CCD is to dramatically reduce the dark current during both integration and readout and the dark fixed pattern noise that accrues during integration.
  • the dark current reduction translates into both increased dynamic range and reduced dark signal shot noise.
  • Another advantage of this invention is the capability to accommodate interlaced operation during both integration and readout in a frame transfer image sensor without loss of performance by performing a one half stage normal transfer following one of the fields to assure proper pixel alignment to avoid pixel mixing during subsequent accumulation periods.
  • FIG. 1 is a schematic plan view of a true two phase area image sensor
  • FIG. la is a fragmentary, partially schematic vertical sectional view taken along the lines a-a of the two phase CCD device of FIG. 1 showing an image pixel;
  • FIG. 2 is an electrostatic potential band diagram for the image pixel of FIG. la illustrating the mechanisms for the generations of dark current;
  • FIGS. 3a and 3b illustrate electrostatic potential band diagrams similar to FIG. 2 showing surface depletion and accumulation modes of operation;
  • FIGS. 4a and 4b are graphs which respectively illustrate gate voltage vs . channel potential and gate voltage vs. dark current for a gate of FIG. la;
  • FIG. 5 schematically illustrates three gate electrodes of a true two phase CCD and potential wells under these gates when changing from the end of a transfer period through an accumulation mode of operating these gates;
  • FIG. 6 illustrates the electrostatic potential maximum, in volts, vs gate voltage for a vertical cross-section through regions (a), (c) and
  • charge transfer channels 12 run in vertical directions. Separating each transfer channel is a channel stop 14 which confines charge collected to the transfer channels and prevents charge leakage into adjacent channels.
  • Each transfer channel 12 has a plurality of sensing elements or image pixels (or, for an interline transfer CCD, stages of the vertical shift register). Each pixel is defined by two closely spaced gates per pixel since this is a two phase device.
  • the gate electrodes can be made from a transparent conductive material such as polysilicon. A potential is applied to each of the electrodes of each sensing element and a potential well or depletion region is formed under it.
  • Charge which is a function of scene brightness, is collected in the potential well.
  • the electrodes are disposed on an insulator such as Si0 2 -
  • the insulator overlies the substrate.
  • the substrate is doped and can be of a given polarity, for example, p—type for an n—channel device.
  • the surface region near the insulator in the substrate is n—polarity opposite to that of the bulk substrate and of such a concentration that when a predetermined potential is applied to the electrode, a potential well is formed within the substrate spaced from the insulator.
  • the image sensor 10 comprises a frame transfer true two phase CCD having voltage phase lines ⁇ , and ⁇ and a buried channel.
  • the pixels define a two dimensional array, which for illustrative purposes only, is shown to have 740 columns and 485 rows of pixels .
  • Each transparent electrode is connected to one line or phase of a two phase voltage clock signal source. After exposure to incident light, the voltage signals on the phase lines are sequentially applied in the well known manner to the image sensing array to move the imagewise charge pattern formed in the pixels one row at a time to an output register shown as block H.
  • High frequency clock pulses drive the polysilicon gate electrodes to read out each of the rows of the image sensor at a rate determined by the particular application.
  • the output register H is shown schematically as a block since it can be provided by a conventional two phase CCD shift register positioned between an optional transfer gate 16 and a horizontal channel stop 18.
  • the transfer gate 16 may be one of the phase clocks of the vertical register.
  • Each cell of the output register H has two gate electrodes aligned with a transfer channel. These electrodes are actuated by signals on voltage lines ⁇ , through ⁇ 2 in the conventional manner.
  • the transfer gate electrode 16 is actuated by a first transfer signal T, and transfers a row of photocharges to the output register H. After a row of photocharges has been transferred to the output register H, the transfer gate 30 is closed. By being closed is meant that a potential barrier is formed under this transfer electrode. At this time, the output register is operated in a two phase manner, clocking the photocharge out to an output diode 32, one pixel at a time. The output diode 32 converts the photocharges into a voltage.
  • the mechanism for operating in the accumulation mode will now be discussed. The generation of dark current due to surface generation sites can be significantly reduced if a voltage is applied to a gate electrode to accumulate majority carriers under that electrode. This will be referred to as an accumulation mode of operation.
  • M0S metal-oxide-semiconductor
  • the mechanisms underlying this effect will now be discussed.
  • the accumulation of holes or majority carriers at the Si-Si0 2 interface suppresses further generation of dark current and can be understood as driving the reaction of producing electron hole pairs (previously discussed) in the reverse direction, i.e., hole capture by the defect rather than hole emission from the defect.
  • the state of accumulation of holes at the Si-Si0 2 interface beneath any CCD phase gate can be controlled by the voltage, Vg, applied to the gate.
  • the hole density in the valence band is determined by the separation of the Fermi level, E réelle, from the valence band, Ev.
  • the density of holes increases dramatically when that separation becomes less than approximately 1/4 the band gap, i.e., the separation between Ev and Ec.
  • the separation is controlled by the gate voltage, V In FIG. 3a, this separation is practically the entire band gap so the semiconductor surface just beneath the gate insulator is depleted of holes (majority carriers).
  • FIG. 3b illustrates the condition of sufficiently more negative gate voltage than for FIG. 3a such that holes are attracted to the
  • FIGS. 4a and 4b show the dark current reduction
  • FIG. 4b shows the channel potential saturation when the surface is accumulated with holes.
  • FIG. 5 where the operation of the CCD of FIG. 1 in the accumulation mode is illustrated.
  • FIG. 5 At the top of this FIG. is a schematic representation of 1 and 1/2 pixels of the true two phase CCD shift register.
  • One pixel is comprised of two gates.
  • the regions labeled (a), (c), and (b) and (d) are the transfer and storage regions of the gate's buried channel. See also
  • FIG. la It is important to note as shown in FIG. la the transfer regions (a) and (c) are more lightly doped (n ) than the storage regions (b) and (d) (n ⁇ ) . It should be noted that other means than doping differences could be employed to form the storage and transfer regions beneath a phase gate.
  • One suitable method is a gate insulator thickness difference.
  • the storage region could be fabricated with a thicker gate insulator than the transfer region, for example.
  • Lines 1-7 show the channel potential (solid line) and the location of the signal charge (shaded) in a sequence of times as the phase one gates are clocked into accumulation between stage-to—stage transfer down the CCD shift register. A discussion of the accumulation mode of operation during charge integration follows the discussion of accumulation during stage—to—stage transfer. (A) Pixel-to-Pixel Transfer
  • Line 1 This is the voltage and signal charge configuration at the end of a normal stage-to-stage transfer down the CCD shift register.
  • the voltage applied to phase line ⁇ 2 is low and that applied to ⁇ , is high.
  • the signal charge resides in the storage well beneath the gates connected to ⁇ , .
  • the surface component of the dark current is suppressed beneath the gate connected to ⁇ 2 .
  • the dark current beneath the gate connected to ⁇ - can also be suppressed by driving it into accumulation.
  • Lines 2-4 Begin to take phase line ⁇ -, low, i.e. toward accumulation. All the signal charge still resides beneath the gate connected to ⁇ , . At some voltage on phase line, ⁇ - ⁇ , the transfer region becomes accumulated and this is the condition at line 4. At this point the channel potential in the transfer region saturates so that a further reduction in the ⁇ , voltage results in no further reduction in the channel potential beneath the gate transfer region connected to ⁇ , .
  • Line 5 Because this transfer region is now accumulated, a further reduction of the ⁇ -i gate voltage results in a reduction in the channel potential of the storage region. As a consequence, the storage well begins to collapse, resulting in a decrease in the charge handling capacity of the ⁇ , gate. The excess signal spills either backward or forward, depending on the relative channel potentials of phases 1 and 2. In this example, the channel potential is greater beneath ⁇ ,, so the excess charge spills backward and is shown shaded beneath ⁇ 2 .
  • Line 6 The gate connected to ⁇ -, is now completely accumulated and the signal is now shared between the pixel gates connected to ⁇ , and ⁇ 2> Both gates of each pixel are now simultaneously in the accumulation mode of operation. This is illustrated by the shaded areas. The surface contribution to the dark current is now suppressed.
  • the channel potentials should be chosen so that the charge capacity is not dramatically reduced, i.e., the accumulated charge capacity beneath one phase should be no less than approximately 1/2 the charge capacity in the normal unaccumulated bias condition, as is shown in line 2, since in the accumulated condition the signal is shared between both pixel gates.
  • Line 7 At the time that a stage-to-stage charge transfer is to be made, the ⁇ , voltage is increased and all the signal is held beneath the gate connected to ⁇ -, again.
  • the normal clocking sequence is applied to transfer the charge from one stage to the next, leaving the signal beneath the ⁇ , gate as shown in line 1, but transferred one full CCD stage along the shift register.
  • the cycle of lines 1—6 can now be repeated to simultaneously accumulate both gates again to suppress the dark current between stage-to-stage transfer.
  • the preceding procedure can be applied during the readout of either a frame transfer or an interline transfer CCD. Such a procedure is applied to the phase gates of the vertical CCD during readout of the horizontal output register.
  • the minimum dark current reduction depends on the fraction of the total frame readout time the phase gates are accumulated. Furthermore, the dark current reduction may be larger if the majority carriers are not emitted from the mid-gap states during the time the gates are not accumulated during the stage-to-stage transfer along the CCD shift register.
  • the dark current can also be suppressed during integration, i.e., during the time that the sensor pixels are optically exposed. This is accomplished by biasing the gates as in line 6 of FIG. 5.
  • the pixel must be defined just as in FIG. 5 to eliminate mixing of information between pixels.
  • an image pixel is defined by the left gate connected to ⁇ 2 and the middle gate connected to ⁇ , since excess charge beneath one will spill into the other and therefore remain in the same pixel.
  • the definition of a pixel is important if, for example, a color filter pattern is applied such that different colors occur in the same column.
  • the accumulation channel potential in the transfer region for ⁇ gate must be more positive than the accumulation channel potential for the ⁇ 2 gate.
  • FIG. 6 shows the electrostatic potential for the transfer and storage region for the ⁇ gate, along with its charge capacity. These curves are calculated from a one dimensional electrostatics model.
  • the charge capacity is determined to be the quantity of charge required to fill the storage region so that its electrostatic potential reaches to within 1/2 volt of the transfer region channel potential.
  • the electrostatic potential of the ⁇ 2 transfer region is also included on FIG. 6. It is designed to be approximately 1/2 volt less positive than ⁇ , as required for a pixel definition as was discussed for FIG. 5.
  • the experimentally measured channel potentials match the channel potential curves of FIG. 6, and the experimentally measured charge capacity is not diminished in the accumulation mode, which is consistent with the calculated charge capacity shown in FIG. 6.
  • each pixel has four electrodes but there are only two phase lines ⁇ , and ⁇ 2 -
  • the first two pixel electrodes are connected to ⁇ , and the second two electrodes are connected to ⁇ 2 .
  • One member of each pair becomes the storage region and the other member of each pair becomes the transfer region.
  • the values of the channel potentials of the storage and transfer regions of each pair must be chosen as described above for the true two phase in order to properly define a pixel.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

Dans un dispositif à couplage de charge, dans lequel un pixel est défini par au moins deux électrodes de porte adjacentes, des tensions sont appliquées aux deux électrodes de porte pour placer simultanément les deux portes de chaque pixel dans le mode d'accumulation de fonctionnement. De préférence, l'une de ces tensions est à un niveau de potentiel supérieur à l'autre.
EP19900914459 1989-09-05 1990-09-04 Reduction du courant d'obscurite dans des dispositifs a couplage de charge Withdrawn EP0441956A1 (fr)

Applications Claiming Priority (2)

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US40273589A 1989-09-05 1989-09-05
US402735 1989-09-05

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EP0441956A1 true EP0441956A1 (fr) 1991-08-21

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JP (1) JPH04503432A (fr)
WO (1) WO1991003840A1 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5182647A (en) * 1990-12-13 1993-01-26 Eastman Kodak Company High resolution charge-coupled device (ccd) camera system
EP0601638B1 (fr) * 1992-12-09 2000-07-26 Koninklijke Philips Electronics N.V. Dispositif à couplage de charge
JP2716011B2 (ja) * 1995-08-09 1998-02-18 日本電気株式会社 電荷転送装置及びその製造方法
JP2888207B2 (ja) * 1996-10-01 1999-05-10 日本電気株式会社 固体撮像装置及びその駆動方法
FR2771217B1 (fr) * 1997-11-14 2000-02-04 Thomson Csf Dispositif semiconducteur a transfert de charges
US6995795B1 (en) 2000-09-12 2006-02-07 Eastman Kodak Company Method for reducing dark current

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3896474A (en) * 1973-09-10 1975-07-22 Fairchild Camera Instr Co Charge coupled area imaging device with column anti-blooming control
US4679212A (en) * 1984-07-31 1987-07-07 Texas Instruments Incorporated Method and apparatus for using surface trap recombination in solid state imaging devices

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9103840A1 *

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Publication number Publication date
JPH04503432A (ja) 1992-06-18
WO1991003840A1 (fr) 1991-03-21

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