EP0440565A1 - Optischer Signalprozessor mit Ladungsverschiebeeinrichtung, insbesondere Sperrelement für quadratische Terme eines Zeitintegrationskorrelators - Google Patents

Optischer Signalprozessor mit Ladungsverschiebeeinrichtung, insbesondere Sperrelement für quadratische Terme eines Zeitintegrationskorrelators Download PDF

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Publication number
EP0440565A1
EP0440565A1 EP91400249A EP91400249A EP0440565A1 EP 0440565 A1 EP0440565 A1 EP 0440565A1 EP 91400249 A EP91400249 A EP 91400249A EP 91400249 A EP91400249 A EP 91400249A EP 0440565 A1 EP0440565 A1 EP 0440565A1
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Prior art keywords
charge
line
lines
cell
transfer
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EP91400249A
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English (en)
French (fr)
Inventor
Alain Becker
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Thales SA
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Thomson CSF SA
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
    • G06G7/19—Arrangements for performing computing operations, e.g. operational amplifiers for forming integrals of products, e.g. Fourier integrals, Laplace integrals, correlation integrals; for analysis or synthesis of functions using orthogonal functions
    • G06G7/1907—Arrangements for performing computing operations, e.g. operational amplifiers for forming integrals of products, e.g. Fourier integrals, Laplace integrals, correlation integrals; for analysis or synthesis of functions using orthogonal functions using charge transfer devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06E—OPTICAL COMPUTING DEVICES; COMPUTING DEVICES USING OTHER RADIATIONS WITH SIMILAR PROPERTIES
    • G06E3/00—Devices not provided for in group G06E1/00, e.g. for processing analogue or hybrid data
    • G06E3/001—Analogue devices in which mathematical operations are carried out with the aid of optical or electro-optical elements
    • G06E3/003—Analogue devices in which mathematical operations are carried out with the aid of optical or electro-optical elements forming integrals of products, e.g. Fourier integrals, Laplace integrals, correlation integrals; for analysis or synthesis of functions using orthogonal functions

Definitions

  • the present invention relates to an optical signal processor, in particular a time integration correlator, comprising a charge transfer device, a component also known under the terminology “DTC network” or “CCD network” (for Charge Coupled Device) .
  • DTC network for Charge Coupled Device
  • DTC networks can be used to carry out the optical processing of a signal (that is to say after this signal has been converted from electrical to optical), especially in two-dimensional processors operating in real time by optical processing of signals such as those delivered by radar or telecommunications receivers.
  • the present invention is applicable to any optical data processor implementing the detection of a light beam by a DTC network, whether this network is in the form of a one-dimensional network ("DTC strip") or two-dimensional , each time this processor will have to operate term by term the subtraction of two series of data, for example the subtraction of two vectors (in the case of a one-dimensional network) or of the rows or columns of two matrices (in the case of a two-dimensional network).
  • DTC strip one-dimensional network
  • two-dimensional two-dimensional
  • the modulated beam is then subjected, by deflecting means such as acousto-optical means, to scanning in one or two directions corresponding to the dimensions of the correlation space.
  • deflecting means such as acousto-optical means
  • a first beam from a laser source S is modulated at 1 by the signal s n (t) coming from the radar receiver.
  • the modulated beam produced is deflected in the horizontal direction (with the drawing convention) by an acousto-optical modulator 2 controlled by a sampled signal p (f i ) corresponding to the N samples of the distance domain for the signal s n (t).
  • a second beam is deflected in the perpendicular direction by a second acousto-optical modulator 3 controlled by a signal r m (t), also sampled, corresponding to the M Doppler boxes of the signal s n (t).
  • the two resulting beams then strike a charge transfer device 4 (shown in isolation in plan, in more detail, FIG. 2), formed of a network 10 of M lines 11 of N cells 12 each, only one of these lines having been illustrated in this figure.
  • a charge transfer device 4 shown in isolation in plan, in more detail, FIG. 2
  • a charge transfer device captures in each exposed pixel of an image zone (referenced ZI in FIG. 2) an incident light flux and transforms the corresponding energy into an electric charge; this charge is stored at the location of the pixel in an elementary capacitor and increases for the duration of the exposure, called "integration time".
  • the resulting charges are then transferred step by step in the network until they reach (either directly, as illustrated in FIG. 2, or via a non-photoactive buffer zone, called "memory zone") to a component. 40 capable of detecting each stored charge and of converting it into a voltage or a current usable by processing circuits 5 arranged downstream.
  • the result of the processing performed by the circuits 5 will be the ambiguity function, represented in 6, making it possible to determine the position of the target pursued by the radar in the ⁇ distance, speed ⁇ domain.
  • the product term of this quadratic sum constitutes the useful signal of the correlation, while the sum of the two square terms constitutes the mean component of the basic level or bias, which is added to the useful signal and the correlation pedestal .
  • the remedy proposed by the prior art consists in using two components out of phase with ⁇ radians, in carrying out simultaneously with them two correlations in two identical charge transfer devices, and in forming the difference between the samples resulting from these two correlations, so as to extract the only useful signal from them.
  • phase shift of one of the modulating signals will change the sign of the product term mentioned above, therefore the sign of the useful component of the signal, but not the sign of the two square terms (due to the elevation at square). Subtracting the two resulting samples will eliminate these square terms, keeping only the useful component of the signal.
  • a configuration such as that illustrated in FIG. 1 is used, by splitting the optical beam generated by the optical source S and also by splitting the beam at the output of the first acousto-optical modulator by means of a beam splitter, and by modulating the second branch of the input beam by an acousto-optical component 3 ′ similar to component 3, but controlled by a signal r m * (t) phase shifted by ⁇ with respect to the signal r m (t).
  • the resulting beam produced by this second branch strikes a second charge transfer device 4 ′, identical to the charge transfer device 4.
  • the two signals from the respective charge transfer devices 4 and 4 ′ are then subtracted from each other by a circuit 7 allowing the elimination of the bias, before being applied to the processing circuit 5.
  • the best current load transfer devices for example those sold under the Dynasensor brand by Dalsa, Inc., only have a dynamic range of the order of 120 dB, a dynamic whose limits are essentially dictated by risk. saturation of each pixel under the effect of too prolonged illumination (overflow effect on neighboring pixels), and above all saturation of the electric amplifier for reading the detection circuit (a dynamic range of 120 dB corresponds to effect at a voltage range which can go from 10 nV to 10 V, which represents a considerable voltage difference). In many applications, this 120 dB limit is still nonetheless insufficient for certain treatments or certain measurements that one would like to perform.
  • the invention proposes to overcome all of these drawbacks by means of an optical processor, in particular a bias suppressor for a time integration correlator, of the aforementioned general type, that is to say in which the terms are subtracted term by term.
  • N homologous values of two series of values, these values resulting from the integration of light energy selectively striking respective photoactive pixels of a charge transfer device.
  • the invention proposes, essentially, to use a charge transfer device configured in such a way as to allow the direct removal of the bias inside the component itself (therefore without degrading performance, in particular with regard to dynamics and noise) - while retaining to signal its total integrity.
  • said line of 2N cells is formed of two parallel elementary lines of N cells each, these elementary lines being sequenced concomitantly, the N pixels of the first elementary line integrating the light energy corresponding to the N respective terms of the first series of values and the N pixels of the second elementary line integrating the light energy corresponding to the N respective terms of the second series of values.
  • the two parallel elementary lines of the same line are preferably placed side by side on said component, so that two pixels corresponding to the two terms of the same rank in the two series are located in the same region of this component.
  • the basic idea is to broaden the dynamics of current networks by performing a double integration, but by performing the second integration directly in the component, without no output of the signal out of it nor transformation of the nature of the information between the beginning and the end of this double integration.
  • the load dividing means are, in themselves, conventional devices known to those skilled in the art, and they can be produced either in the form of a capacitive divider or in the form of an electric divider (with barrier controlled potential).
  • the load dividing means are capacitive dividing means, it is possible to combine this second embodiment with this improved embodiment.
  • said charge dividing means can also be electrical dividing means.
  • said predetermined division ratio is of the order of 1: 100, which makes it possible to obtain a corresponding increase in dynamics of 40 dB.
  • said looped line is produced on the component in the form of a folded line formed by two adjacent halves of the same length and transferring the loads in opposite directions.
  • the cells of the folded looped line then preferably have a width which is approximately that of each of said abovementioned parallel elementary lines of the first network, so that the homologous lines of each of the networks have respective widths which are substantially identical.
  • Figure 1 shows an optical signal processor with bias elimination, according to the prior art.
  • FIG. 1 shows the charge transfer device of the optical processor of Figure 1, according to the prior art.
  • FIG. 3 is equivalent to FIG. 1, for the optical processor of the present invention.
  • FIG. 4 is equivalent to FIG. 2, for the charge transfer device used by the optical processor of FIG. 3.
  • Figure 5 is a detail of Figure 4, corresponding to a horizontal line isolated from the charge transfer device.
  • FIG. 6 shows the transfer zone ZT of FIG. 5, in another phase of operation.
  • Figures 7 and 8 are homologous to Figures 5 and 6, for a second embodiment of the invention.
  • FIG. 9 schematically shows a charge transfer device according to the invention comprising, in addition to an image area ZI and a transfer area ZT, a memory area ZM configured so as to operate on the component even a second integration of the signal.
  • Figure 10 is a detail of Figure 9, corresponding to a horizontal line isolated from the component of Figure 9, with its same areas.
  • FIG. 11 is an explanatory diagram showing the manner in which the successive operations of subtraction, division and cumulation of charges are carried out in the component transfer zone (region 30 of FIG. 9).
  • FIGS. 3 and 4 are homologous to Figures 1 and 2 explained above, and the same reference numerals designate similar elements in the different figures.
  • the processor of the invention uses only one beam for each dimension of the treatment, which eliminates all the difficulties of alignment, of dispersion of the components, of the vibrations, etc. inherent in a splitting of the beams modulated by r m (t).
  • the processor of the invention uses only one charge transfer device 4, which makes it possible to eliminate the subtractor stage 7 ( figure 1).
  • This single charge transfer device 4 comprises, on a single and same component, a network of (2M) x N cells, each line 11 being in fact split, as can be seen in more detail in FIG. 4, in two elementary lines identical 11a and 11b of N cells each, designated respectively 12a and 12b, which will each receive one of the two phase-shifted signals of ⁇ radians intended to allow, as mentioned above, the elimination of bias by combination.
  • the cells 12a and 12b of the image area ZI are of conventional structure, each corresponding to a photoactive pixel receiving an elementary light energy h ⁇ and transforming it into an electric charge which will increase as the illumination takes place (phenomenon integration of the luminous flux).
  • the charges accumulated in the respective cells 12a and 12b will be combined, as will be explained below, by a subtractor circuit 30 located in a transfer zone ZT adjacent to the image zone ZI before being applied to the detection amplifier 40,
  • the detection amplifier 40 will transform the charges stored in the memory area into electrical voltage or current signals and deliver them to the outside for further processing.
  • This aspect of the component is conventional as such and will not be discussed in detail for this reason; it will however be indicated that all the known reading modes can be used, namely, mainly the simultaneous reading, in parallel, of all the lines of the network (in this case as many amplifiers 40 as lines) or the reading successive of the different lines, each being transferred in sequence to a buffer register formed by a shift register comprising the same number of pixels as each of the lines and connected, in this case, to a single detection amplifier 40.
  • the two elementary lines 11a and 11b corresponding to the same line 11 are placed side by side, in order to make the most of the uniformity local crystal on which the charge transfer device (this configuration also facilitates the interconnection of the two elementary lines of each line 11, and simplifies the optical alignment of the beam relative to the components).
  • the charge transfer device can also include, in itself known manner, in addition to the image area ZI, a non-photosensitive memory area, of the same dimension (in number of cells) as the photosensitive image zone ZI, and serving as a buffer zone in which the charges are transferred from the image zone before reading by the detection amplifiers 40.
  • the light beam emitted by the source 1 is modulated by a sampled signal s n (t), corresponding to the signal to be analyzed, of the form:
  • s n (t) S n (t) cos ⁇ t, with n ⁇ [1, N], signal which we will correlate with a reference signal, also sampled, of the form:
  • r m (t) R m (t) cos ( ⁇ t + ⁇ ), with m ⁇ [1, M].
  • the correlation product will be, for the sample (m, n) and at the end of the integration time T (with t ⁇ [O, T]), an expression of the form: with:
  • Figures 5 and 6 on the one hand, and 7 and 8 on the other hand, show, respectively, two possible embodiments of the subtractor circuit 30 of the transfer zone ZT.
  • the function of the circuit 30 is to make the difference between the charges Q n and Q ′ n contained in the respective cells 12a and 12b of the elementary lines 11a and 11b.
  • the subtractor circuit 30 comprises two capacitors 31 and 31 ′, of the same capacity and whose common point 32 is selectively connected to ground (or to a constant reference potential) by means switches 33, for example, a MOS switch.
  • the armature of the capacitor 31 opposite the common point 32 is connected to the output line 34 by means of a switch 35, while the armature of the capacitor 31 ′ opposite the common point 32 is connected to the ground (or at a constant reference potential) by a switch 34.
  • a first phase of the cycle corresponding to the situation in FIG. 5, the midpoint 32 is connected to ground (switch 33 closed) and the opposite armatures of the capacitors 31 and 31 ′ are both left in the air (switches 34 and 35 open).
  • the charge Q m from the cell 12a to the capacitor 31 and the charge Q ′ m from the cell 12b to the capacitor 31 ′ is then transferred, by the conventional means of the charge transfer device technique.
  • the switch 33 is opened and the switches 34 and 35 are closed.
  • the two capacitors 31 and 31 ′ will then be in series connection, equivalent to a capacitor single carrying between the two extreme armatures a load (Q m - Q ′ m ) corresponding to the differential load Qs sought.
  • This charge Qs will then be transferred by line 34 either to the output of the component for detection and amplification, or to a second integration network, as will be described below with reference to FIGS. 9 to 11.
  • the subtractor circuit 30 of each of the lines 11 uses a single capacitor 37, of capacity C, one of the armatures of which can be connected, by a switch 38, either to the cell 12a, either to the output line 34 and the other armature of which can be connected, by a switch 38 ′, either to cell 12b, either to ground or to a source of constant reference potential.
  • the respective armatures of the capacitor 37 are connected to cells 12a and 12b, which will cause the charge Q m which was in cell 12a and the charge Q ′ m which was in cell 12b to be pooled between these two cells (of capacity D each) and the capacitor 37 (of capacity C).
  • the capacitor 37 of the cells 12a and 12b is decoupled, the lower armature (that is, that of the switch 38 ′ is grounded). corresponding to the elementary line 11b) and the upper armature (that is to say the one corresponding to the elementary line 11a) is connected by the switch 38 to the output line 34.
  • the network illustrated in these FIGS. 9 to 11 is that of a charge transfer device with two separate image and memory areas, as already exists in certain conventional charge transfer devices.
  • Reference 10 designates the network of the image area ZI
  • reference 20 designates the network of the memory area ZM.
  • the image area ZI of the component is photoactive; it integrates the light signal for a given time until the result reaches a fraction of the saturation level, function of the quality sought and, at the end of each integration, it transfers its content to the memory zone ZM.
  • such a network in its conventional configuration, only transfers the data from the image zone to the memory zone, this transfer also being carried out at a rapid rate so as to minimize the latency time of the processing.
  • the memory area is then re-read at a slower rate during a new integration cycle of the image area, to restore the information stored. It is then no longer possible, after the transfer, to continue to integrate the initial optical signal.
  • the invention essentially proposes, in this improved embodiment with two levels of integration, to keep the charge in the memory area for a large number of cycles of integration of the image area and to increase this charge, from transfer to transfer, by adding to the charge already present in the memory area a fraction of the charge stored in the image area and which we have just transferred.
  • the charges accumulated in each of the pixels will be transferred, step by step, to the transfer zone ZT by appropriate control, according to a precise and coordinated sequencing, of the potential barriers separating each of the pixels.
  • This charge transfer step by step by checking the potential barriers separating the different pixels or cells is characteristic of all charge transfer devices and will not be described in detail for this reason.
  • Line 21 of the network constituting the memory area ZM is also conventional, and includes a plurality of cells such that 22, in a number equal to that of cells 12a, 12b of line 11 of image area ZI, and separated from each other by potential barriers whose control by appropriate clock signals makes it possible to ensure the offset loads along the line, from the first cell 23 to the last cell 24.
  • this second characteristic is not essential for the implementation of the invention; one could in fact provide a line 21 that is not folded back, with a return link making it possible to bring the load from the last cell (which would then be at the far right of the component, with the conventions of the figure) to the transfer zone, located in the central part of the component.
  • the width (physical dimension in the direction perpendicular to that of the line, that is to say in the vertical direction with the conventions of the figure) of cells 22 of the memory area ZM is approximately the same as that of cells 12 of the image area ZI, so that the overall width W of the two lines 11 and 21 placed end to end is substantially constant , which optimizes the surface occupied on the substrate and the photoelectric yield of the component (contiguous cells).
  • the transfer zone ZT preferably comprises the subtracting means 30 of the second embodiment described above with reference to FIGS. 7 and 8, that is to say which carry out, in addition to the subtraction, a division of the resulting charge.
  • These means 30 ensure, on the one hand, the transfer (after subtraction and division) of the charges from the image zone ZI to the memory zone ZM and, on the other hand and typically from the double integration, the recirculation of the stored charges in the memory area and the processing allowing the second integration to be carried out on these loads.
  • the charge on the capacitor 37 will be added to the each Qg already present in the cell of the line of the memory array corresponding to the pixel in question by means of a charge adder 39, the resulting charge Qg + Qs being reinjected in the network line of the memory area in the next cycle, in place of Qg, in order to make it recirculate there.
  • the predetermined division ratio n will be chosen so that the cumulative charge at the end of the final integration time (itself dependent on the number of recirculation cycles in the memory area) reaches a level generally lower than the network saturation level.
  • capacitive load dividing and adding means it is not necessary to use capacitive load dividing and adding means, but that it is also possible to use, instead of these capacitive means, electrical means operating (in a manner known as such) a division by means of a controlled electric field (potential barrier) or causing a controlled discharge of a fraction 0.99 Q m of the charge.
  • the charge Q s is added to that Q g already contained in the last cell of the memory area and obtained by previous transfers, and this charge is reinjected at the input of this same line of the area memory, the charge Q g thus becoming Q g + Q s .
  • the effect of the double integration is to provide a total dynamic which is the sum of the proper dynamic of the charge transfer device of the image area with the fraction of charge used by the network of the memory area.
  • the useful output information remains at the top of the 160 dB of the total dynamics of the internal processing, and therefore is perfectly usable. .

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  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
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  • Optics & Photonics (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
EP91400249A 1990-02-02 1991-02-01 Optischer Signalprozessor mit Ladungsverschiebeeinrichtung, insbesondere Sperrelement für quadratische Terme eines Zeitintegrationskorrelators Withdrawn EP0440565A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9001233 1990-02-02
FR909001233A FR2657976B1 (fr) 1990-02-02 1990-02-02 Processeur optique de signaux comportant un dispositif a transfert de charges, notamment suppresseur de biais pour correlateur a integration temporelle.

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EP0440565A1 true EP0440565A1 (de) 1991-08-07

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EP91400249A Withdrawn EP0440565A1 (de) 1990-02-02 1991-02-01 Optischer Signalprozessor mit Ladungsverschiebeeinrichtung, insbesondere Sperrelement für quadratische Terme eines Zeitintegrationskorrelators

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2409552A1 (fr) * 1977-11-22 1979-06-15 Thomson Csf Dispositif multiplicateur multicanaux, notamment pour systeme de traitement de signal par correlation, et systeme de traitement de signal comportant un tel dispositif
US4547864A (en) * 1982-01-07 1985-10-15 Canon Kabushiki Kaisha Correlation detecting device
US4833636A (en) * 1987-06-19 1989-05-23 Fuji Photo Film Co., Ltd. Analog, two signal correlator

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4797561A (en) * 1985-08-31 1989-01-10 Kyocera Corporation Reading apparatus with improved performance
US4722596A (en) * 1986-05-13 1988-02-02 Sperry Corporation Acousto-optic analyzer with dynamic signal compression
US4985618A (en) * 1988-06-16 1991-01-15 Nicoh Company, Ltd. Parallel image processing system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2409552A1 (fr) * 1977-11-22 1979-06-15 Thomson Csf Dispositif multiplicateur multicanaux, notamment pour systeme de traitement de signal par correlation, et systeme de traitement de signal comportant un tel dispositif
US4547864A (en) * 1982-01-07 1985-10-15 Canon Kabushiki Kaisha Correlation detecting device
US4833636A (en) * 1987-06-19 1989-05-23 Fuji Photo Film Co., Ltd. Analog, two signal correlator

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
GEC JOURNAL OF RESEARCH, vol. 2, no. 2, 1984, pages 88-95; P.V. GATENBY et al.: "Acousto-optic signal processing" *
ONZIEME COLLOQUE GRETSI, Nice, 1-5 juin 1987, pages 693-696; N. LAOUAR et al.: "Correlateur opto-electronique analogique pour le traitement en parallel de signaux de type radar" *

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US5170048A (en) 1992-12-08
FR2657976B1 (fr) 1994-07-01

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