EP0436959A2 - Digitales Videofarbanzeigesystem unter Verwendung schmutziger Bits zur Erzeugung von Pixeldaten mit hoher Geschwindigkeit in Rasteranzeigegeräten - Google Patents

Digitales Videofarbanzeigesystem unter Verwendung schmutziger Bits zur Erzeugung von Pixeldaten mit hoher Geschwindigkeit in Rasteranzeigegeräten Download PDF

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Publication number
EP0436959A2
EP0436959A2 EP90125789A EP90125789A EP0436959A2 EP 0436959 A2 EP0436959 A2 EP 0436959A2 EP 90125789 A EP90125789 A EP 90125789A EP 90125789 A EP90125789 A EP 90125789A EP 0436959 A2 EP0436959 A2 EP 0436959A2
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European Patent Office
Prior art keywords
pixel
data
image
value
buffer memory
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Withdrawn
Application number
EP90125789A
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English (en)
French (fr)
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EP0436959A3 (en
Inventor
Bruce E. Imsand
Joseph Clayton Terry
William Steve Pesto, Jr.
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Intergraph Corp
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Intergraph Corp
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/02—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed

Definitions

  • the present invention relates to raster display video systems generating high speed pixel data for displays utilized in multi-window environment workstations.
  • the raster display drivers have been unable to output more complex images, such as a window having an image in motion, without having a delay in the output of the image. Since the pixel data is written to and read from a frame buffer memory as the image changes, the key to providing a distortion-free moving image is a fast throughput in the reading and writing of the pixel data.
  • Gouraud shading performs a bilinear interpolation to determine the red, green and blue values of the pixels which display the model component of the image.
  • the use of z-buffering positions arbitrary model components of the display image in the 3-D model space with respect to each other such that a pixel for one model component will be written over a pixel for a second model component of the same display image only if the first model component is logically determined to be in front of the second model component in the 3-D model space.
  • the z-buffering technique is especially important to position arbitrary model components of the display image in 3-D space where there is no prior information of the relative location of the model components.
  • the need for fast throughput is found when a picture perspective changes during animated rendering, whereby a display driver will erase the z-buffer as the perspective of the model components in the window changes.
  • a major obstacle to fast throughput is the time needed to erase the z-buffer and the working buffer of a frame buffer memory before writing the next image, while currently displaying the present image of the display buffer of the frame buffer memory; the time needed to erase the buffers one pixel at a time may take as long as 16 milliseconds.
  • distortions or time lags may be present during animated rendering of the windowed images.
  • a multi-windowed system may use both pseudo color and true color images in the respective windows; for example, if a raster display includes three windows, each having its respective application program, window A and B may show pseudo-color images, whereby window C may show a true color image.
  • VLT video look-up table
  • True color images generally need more than 28 actual colors, so 24 bits (e.g., planes) of the frame buffer memory are used to generate the colors; however, since the RGB electron guns, the associated amplifiers and the human eye are all nonlinear, look-up tables are still needed to provide correction factors for the true color images.
  • DRAMs dynamic random access memories
  • a Flash Erase (or Fill) function has been developed in the DRAMs, whereby upon the receipt of a Flash Erase command either a 0 or 1 is forced into every location along a particular row within one memory cycle.
  • the display color video system of the present invention provides fast throughput in the reading and writing of the pixel data to minimize distortions, especially during animated rendering of windowed images.
  • This fast throughput is realized by a novel combination of the Flash Erase function of DRAMs with successive referencing of each pixel by its associated property or context.
  • each window of a multi-window applications environment will display certain images in accordance with its respective applications program, it is desirable to consider each window as having its own set of properties or contexts of interpretation, so that all pixels of the respective window are identified by the properties corresponding to the window.
  • each pixel has an associated ID properties bundle which enables the pixel to be mapped through a look-up table in order to generate the appropriate data for the RGB digital-to-analog (D/A) converters associated with the cathode ray tube (CRT).
  • each pixel has a second properties bundle which defines the context of interpretation of the respective ID properties bundle.
  • This second properties bundle enables rapid operations via a secondary look-up table on all pixels whose ID properties bundles have a given property defined within the predetermined context specified by the secondary properties bundle.
  • a given context of a window can be quickly modified with respect to the properties defined within that context.
  • the present invention takes advantage of the Flash Erase function of DRAM technology by defining at least one of the bits of the second properties bundle as a "Dirty Bit", capable of being Flash Erased by the DRAM.
  • the display color video system of the present invention has a memory organization defining each pixel to include frame buffer memory data for real or pseudo colors, z-buffer data, and pixel tag data.
  • the frame buffer memory data and the z-buffer data are stored in memory that does not use the Flash Erase function.
  • the pixel tag data for each pixel is stored in a DRAM having the Flash Erase function.
  • At least one of the second properties bundle bits is reserved as a dirty bit, which utilizes the Flash Erase function; by defining at least one bit of the pixel data as a dirty bit, a Flash Erase command will set all the dirty bits for all pixels of the raster display screen to either a 0 or a 1, whichever is preferred.
  • the display of the pixel, in light of the set dirty bit, can then be determined through a look up table in accordance with the remaining pixel tag data.
  • a context may be defined through a look up table such that the dirty bit invalidates the properties of the pixels of the given window, and redirects the pixels within that window to a predetermined null context; as a result, the pixel color data and z data for the redirected pixels are invalidated by the predetermined null context.
  • another context may be defined to disregard the dirty bit, so that the pixels associated with the alternate context are not redirected to the predetermined null context when their dirty bit is set.
  • the display color video system of the present invention can selectively switch between different contexts by assigning a bit of the pixel ID to be a dirty bit, flash filling all the dirty bits of all the pixels, and then determining whether the pixel associated with a particular context is defined to respond to or disregard the dirty bit. If the pixel is responsive to the dirty bit, the look up table directly maps the pixel to the null context; if, however, the pixel is to disregard the dirty bit, the pixel is output in accordance with its existing context.
  • the dirty bits of the pixel data are also used during the pixel-by-pixel image construction stage to more quickly construct in memory the model components of the next windowed image to be displayed. Those pixels that are responsive to the setting of dirty bits enter into a null context, such that the corresponding z value is irrelevant; since the z value of any pixel responding to the dirty bit is defined to be irrelevant whenever a pixel is written whose dirty bit is set, the z value of the existing image is ignored and the pixel data for the next model component is automatically written into the frame buffer memory and the z buffer memory, and the dirty bit for the pixel is reset.
  • a working buffer and the z buffer in a conventional system would be erased on a pixel-by-pixel basis at locations corresponding to the windowed image while the display buffer was outputting the display data for the current image.
  • the erase can be achieved much more quickly by flash setting the dirty bits for all pixels of the display image in response to a flash set signal.
  • the working buffer is then drawn along with the z buffer memory using standard z-buffering techniques when drawing multiple model components of the display image (e.g., comparing the z value of the existing pixel of the existing model component with the z value of the corresponding pixel of the next model component), except that whenever a pixel is written whose dirty bit is set, the z value is ignored and the new pixel data is written into the working buffer memory.
  • standard z-buffering techniques when drawing multiple model components of the display image (e.g., comparing the z value of the existing pixel of the existing model component with the z value of the corresponding pixel of the next model component), except that whenever a pixel is written whose dirty bit is set, the z value is ignored and the new pixel data is written into the working buffer memory.
  • the reading of the dirty bit during the construction of the image is done in parallel with the reading of the z value to maintain speed performance.
  • the new image can be written into the frame buffer memory, without ever needing to clear the frame buffer memory or the z buffer memory. The result is the savings of a substantial amount of time.
  • FIGURE 1 is a system block diagram of a digital color video system for a raster display according to the present invention.
  • a RISC processor 10 having digital signal processing (DSP) capabilities receives basic image and control data from a system bus 12.
  • the system bus 12 may be an I/O bus which passes the basic image and control data from, for example, a central computer.
  • the RISC processor 10 performs all necessary DSP functions before outputting video data to a hardware accelerator 14.
  • the accelerator 14 constructs the image to be displayed by writing the appropriate pixel data to a frame buffer memory 16, a z buffer memory 18 and a video interface 20; the accelerator 14 in constructing the image to be displayed may also perform functions such as Gouraud shading, drawing anti-aliased vectors, etc.
  • the z-buffer memory 18 stores the z value for each respective pixel.
  • the z value includes, for example, 24 bits for a possible 224 gradations in depth as positioned in the 3-D model space.
  • the frame buffer memory 16 stores the color data for each pixel; if the pixel color data is to be displayed as true color data, the frame buffer memory 16 is arranged to provide, for example, 24 planes (e.g., bits) of actual frame buffer memory; if, however, the pixel color data is to be displayed as pseudo color data, the frame buffer memory 16 is arranged to provide 12 planes of frame buffer memory for each of a front buffer and a back buffer, whereby the front buffer acts as a display buffer by providing the pixel color data for the display image while the back buffer acts as a working buffer, e.g., the pixel color data for the next image is written into the back buffer by the accelerator 14, and vice versa.
  • the front buffer acts as a display buffer by providing the pixel color data for the display image while the back buffer
  • the video interface 20 contains video look up tables (VLT) which contain color code data for the RGB electron guns; the VLTs map the pixel color data on a pixel-by-pixel basis from the frame buffer memory 16 to a predetermined context in accordance with corresponding pixel tag data (described in detail later).
  • VLT video look up tables
  • the color code data stored in the VLTs is preloaded before each new image is to be output.
  • FIGURE 2 is an exemplary schematic of the data associated with each pixel, in accordance with the present invention.
  • Bits 0-23 for each pixel are designated for z values, and are stored in the z buffer memory 18.
  • Bits 24-47 designate the color data for the respective pixel and are stored in the frame buffer memory 16; if pseudo color is desired, the frame buffer memory 16 is divided into a front and back buffer, such that bits 24-35 are reserved for the pseudo color code stored in the front buffer, and bits 36-47 are reserved for the pseudo color code stored in the back buffer.
  • Bits 48-55 designate the pixel tag data for each pixel. At least one of the bits of the pixel tag data is designated a dirty bit.
  • the pixel tag data for each pixel is used to characterize the pixel with respect to the context or the properties the pixel is intended to represent.
  • each window will display certain images in accordance with its respective applications program; those images of the window can be characterized as having a unique set of properties or contexts of interpretation. Since each pixel represents a color corresponding to one of the contexts, the pixel can be identified by the property or context it represents, as opposed to its location on the raster display. Thus, by identifying each pixel by the context in which the pixel is represented, a given context in a window can be quickly modified with respect to the properties defined within the context. Therefore, the value of the pixel tag data indicates the context in which the pixel is intended to be represented.
  • the pixel tag data for each pixel includes an ID properties bundle and a second properties bundle.
  • the ID properties bundle indicates the context which the pixel is intended to represent, and maps the pixel data through the VLT of the video interface 20 to generate the appropriate data for the RGB D/A converters of the CRT (not shown).
  • the second properties bundle include at least one bit reserved as a "Dirty Bit", which is used to provide rapid writing of the pixel data in the frame buffer memory, and to map pixels whose ID properties bundles have a specific property to a predetermined null context.
  • the second properties bundle characterizes the ID properties bundle in order to define a context of interpretation of the respective ID properties bundle (e.g., even the properties represented by the ID properties bundle have their own properties).
  • the accelerator 14 can identify all ID properties bundles having a specific property by their corresponding second properties bundle, and can modify through a secondary look up table the pixels whose ID properties bundle have a specific property in accordance with the second properties bundle.
  • FIGURE 3 is a block diagram of the frame buffer memory 16 and the video interface 20 of FIGURE 1.
  • the video interface 20 receives pixel color data from the frame buffer memory 16 and outputs digital color code data to D/A converters 22R, 22G and 22B in accordance with the corresponding pixel tag data.
  • the pixel tag data for each pixel is stored in a pixel tag memory 24, which is connected to the accelerator 14 via a bi-directional bus.
  • the pixel tag memory 24 is a DRAM having a Flash Erase function.
  • the DRAM of the pixel tag memory 24 is arranged so that two bits of the 8 bit pixel tag, DIRTY FB and DIRTY BB, are reserved as dirty bits which can be set to 0 in response to an external Flash Erase command.
  • Generation of the Flash Erase command may be application specific, and may, for example, arise from an external command from the system bus 12.
  • the external Flash Erase command has two bits to selectively flash set to 0 either DIRTY FB, DIRTY BB, or both.
  • the pixel tag data also includes HIGHLIGHT FB and HIGHLIGHT BB bits, and a 4-bit ID properties bundle.
  • the second properties bundle of the pixel tag includes the bits DIRTY FB, DIRTY BB, HIGHLIGHT FB and HIGHLIGHT BB.
  • the pixel tag memory 24 outputs the pixel tag data, in response to a corresponding address signal (not shown), to a pixel tag look up table (LUT) 26.
  • the pixel tag LUT 26 maps the pixel color data from the frame buffer memory 16 to the appropriate color contexts stored in VLTs 28R, 28G and 28B; thus, the pixel tag LUT 26 maps the pixel color data to a particular context of interpretation according to the properties of the respective ID properties bundle by selecting a Major Context, and a Minor Context of the VLTs 28R, 28G and 28B (described later).
  • the pixel tag LUT 26 also arranges the pixel color data via switching devices 30R, 30G and 30B, depending on whether the pixel color data represents pseudo or true color data.
  • the pixel tag LUT 26 outputs a buffer select signal (FB/BB) to a switching device 32.
  • the switching device 32 then outputs the pseudo color data from either the front buffer or back buffer of the frame buffer memory 16, in accordance with the buffer select signal.
  • the switching devices 30R, 30G and 30B provide the appropriate pixel color data to the VLTs 28R, 28G and 28B, each of which are 16k x 8 bit RAMs, in response to a Pseudo Select signal from the pixel tag LUT 26. If the Pseudo Select signal is 0, indicating true color data, the 4 bits of Minor Context data are combined with each of the 8 bits of the appropriate R,G and B true color data from the frame buffer memory 16, thus providing 12 bits of pixel color data output to the respective VLTs 28; if the Pseudo Select signal is 1, indicating pseudo color data, the same 12 bits of pseudo color data are output to the VLTs 28R, 28G and 28B.
  • Two bits of Major Context data are added to each of the 12 bits of color data from the switch devices 30R, 30G and 30B, thereby providing a total of 14 bits input to the VLTs 24R, 28G and 28B.
  • the data input to each VLT 28 includes 8 bits of the corresponding true color data from the frame buffer memory 16, 4 bits of Minor Context data, and 2 bits of Major Context data; in pseudo color mode, however, the data input to each VLT 28 includes 12 bits of pseudo color data from the frame buffer memory 16, and 2 bits of Major Context data.
  • the minor context data is not used for mapping in the VLT 28 during pseudo color mode.
  • FIGURE 4 is an exemplary block diagram of one of the VLTs 28 of the video interface 20 in FIGURE 3.
  • the VLT 28 is a 16k x 8 bit RAM subdivided into four major contexts.
  • the 14 bit data input into the VLT 28 serves as an address input, ranging from hexadecimal values 0-3FFF, to access the appropriate color code representing a particular color context.
  • the VLT 28 is updated with the color code data each time a new window is rendered active in the multi-windowed environment.
  • the VLT 28 is subdivided into four major contexts: reference 40 designates Major Context 0; reference 42 designates Major Context 1; reference 44 designates Major Context 2; and reference 46 Major Context 3.
  • the desired Major Context is addressed by the 2 bits of Major Context data from the pixel tag LUT 26.
  • Major Contexts 0, 1 and 2 are pseudo color contexts of 4k regions, each region being addressable by the 12 bits of pseudo color data from the frame buffer memory 16.
  • Major Context 3 is a true color context of a 4k region which is further subdivided into 16 minor contexts. Of the 16 minor contexts, true color contexts 0-13 contain conventional contexts for true color mapping; thus, the multiple true color contexts enable up to fourteen separate correction factors. Each minor context has 256 locations, addressable by the 8 bits of true color data from the frame buffer memory 16.
  • Two of the minor contexts of Major Context 3 are reserved for HIGHLIGHT and DIRTY functions.
  • the function of Dirty Bits is to redirect a pixel designated responsive to its dirty bit to a predetermined null context. That predetermined null context is defined in the DIRTY minor context: all 256 locations of the DIRTY minor context are loaded with the identical color code value.
  • Minor Context 1 Minor Context 0 being the HIGHLIGHT function
  • the pixel color data is disregarded and the VLT 28 outputs from the DIRTY minor context the color code value indicating the predetermined null context.
  • the use of the dirty bit enables the nullification of video data from frame buffer memory 16 without erasing the frame buffer memory 16 or the z buffer memory 18.
  • the HIGHLIGHT minor context works in a similar manner: a pixel is mapped to the HIGHLIGHT minor context if, in response to the pixel tag bits HIGHLIGHT FB or HIGHLIGHT BB being a value of 1, the pixel tag LUT 26 outputs a Major Context of 3 and a Minor Context of 0.
  • the HIGHLIGHT function can be used to highlight a given pixel to a predetermined highlight color code. This allows a highlighting of the pixel without erasing the true color data in the frame buffer memory 16. After the HIGHLIGHT FB or HIGHLIGHT BB pixel tag bits are reset to 0, the pixel can be displayed in accordance with the original pixel data.
  • FIGURE 5A shows an arrangement of the pixel tag LUT 26.
  • the pixel tag LUT 26 is segmented with respect to applications being simultaneously displayed on the raster display. Each ID segment is addressed by the ID properties bundle output from the pixel tag memory 24.
  • FIGURE 5B shows exemplary outputs for three display applications from the pixel tag LUT 26.
  • the output data for Application "A” is stored in ID segment 2 of the pixel tag LUT 26
  • the output data for Application "B” is stored in ID segment 14
  • the output data for Application "C” is stored in ID segment 8.
  • FIGURE 5C shows the inputs to the pixel tag LUT 26 corresponding to the output data described in FIGURE 5B.
  • the pixel tag LUT 26 will map the pixel color data to either one of two generic contexts if a dirty bit is set: a first context, which responds to the dirty bit, or a second context, which disregards the dirty bit.
  • Application "A" is a single buffered, 12 bit pseudo color application using highlight and which disregards the dirty bits.
  • a window is created by writing the 12 bits of pixel pseudo color data into the front buffer of the frame buffer memory 16.
  • the pixel tag memory 24 is also written to with the appropriate pixel tag data.
  • the pixel tag LUT 26 When HIGHLIGHT FB is set to 1, the pixel tag LUT 26 outputs a Pseudo Select signal of 0 to the switch devices 30R, 30G and 30B, and outputs a Major Context of 3 and a Minor Context of 0, which maps the pixel color data to the HIGHLIGHT Minor Context of the VLT 28, as shown in FIGURE 4.
  • the output data for Application “A” has redundant entries with respect to the input values of the dirty bits DIRTY FB and DIRTY BB; thus, Application "A" disregards the dirty bits.
  • the pixel tag LUT 26 directs the pixel color data to a predetermined context in response to the ID properties bundle of the pixel and the second properties bundle which includes the front and back buffer bits for the HIGHLIGHT and DIRTY functions.
  • FIGURE 6 is a block diagram of an image construction driver portion of the display color video system of the present invention.
  • the image construction driver portion 48 is located within the accelerator 14, which constructs the image to be displayed.
  • the accelerator 14 may also include a processor to address the appropriate pixel to be written into the frame buffer memory 16, the z buffer 18 and the pixel tag memory 24.
  • the image construction driver portion 48 enables the rapid drawing of multiple model components of the display image in the 3-D model space of the windowed environment, whereby a first model component will not be displayed in the windowed image if it is logically determined that a second model obstructs the first model component of the display image.
  • the image construction driver portion 48 has a write decision logic circuit 50 which determines whether new pixel data for a new model component of the display image from the RISC processor 10 should be written over the existing pixel data; the write decision logic circuit 50 examines both the dirty bits of the existing pixel tag data, and compares the z value of the existing pixel in memory with the z value of the corresponding pixel of the new model component.
  • the dirty bits of the existing pixel in memory are temporarily stored in a register 52, and the z value of the existing pixel in memory is temporarily stored in a register 54.
  • the write decision logic circuit 50 outputs a write signal to a memory controller 56 if the dirty bit associated with the current working buffer of the existing pixel in memory is set, or if the z value of the pixel of the new model component of the display image is greater than the z value of the corresponding existing pixel in memory.
  • the memory controller 56 will output a write enable signal to the frame buffer memory 16, the z buffer memory 18 and the pixel tag memory 24 in response to the write signal, thus causing the new pixel data for the new model component of the display image to be written into the appropriate memory.
  • the dirty bit of the pixel is cleared in order to enable the pixel to be displayed; the dirty bit is cleared by the writing of the new pixel tag data into the pixel tag memory 24.
  • the image construction driver portion 48 repeats the writing procedure until all model components included in the display image have been written, even though portions thereof may be obstructed by other model components that are closer to the display in the 3-D space.
  • the setting of the dirty bit redirects the pixel to a predetermined null context if the pixel tag data in the pixel tag LUT 26 is defined to be responsive to the dirty bit.
  • the z value of the pixel is considered to be at the lowest possible value (e.g., the farthest depth from the front of the raster display screen in the 3-D model space), and is therefore considered irrelevant; as a result, any other context must have a z value greater than that of the null context. However, the actual z value need not be changed.
  • the image construction driver portion 48 can output a write signal whenever the dirty bit is set. This use of the dirty bit enables rapid erasures and rapid writing of pixel data into memory.
  • a raster display initially shows a display image in accordance with pixel data from the front buffer of the frame buffer memory 16.
  • a window showing the image from Application "C” is created in the back buffer of the frame buffer memory 16 by first setting the dirty bit DIRTY BB in the pixel tag memory 24 for all pixels of the entire screen by sending the Flash Erase command to the pixel tag memory 24.
  • the 4 bits of pixel ID data in the pixel tag memory 24 for all of the pixels in the area defining the window are then written with a unique ID, in this case "8".
  • the new display image for the window in Application "C” is now written into the back buffer of the frame buffer memory 16 and the z buffer memory 18 by sequentially drawing each of the model components included in the display image in accordance with their respective locations in the 3-D model space.
  • the first model component of the display image will be automatically written; while standard z-buffering techniques are still used for subsequent model components of the same display image by comparing the z value of the existing model component with the z value of the corresponding pixel of the next model component of the same display image, if a pixel at an intended location of a model component has its dirty bit DIRTY BB set, the z value of the pixel of the new model component of the display image is ignored and the new pixel data for the new model component is automatically written, the dirty bit DIRTY BB being cleared thereafter.
  • the pixel tag LUT 26 is then reloaded during the vertical blanking interval of the raster display to display the back buffer pixels having an ID properties bundle value of 8.
  • This procedure repeats itself each time the image in the window changes, alternating between the front and back buffers without ever needing to clear the display memory or the z-value memory. Thus, a substantial amount of time is saved.
  • the back buffer would need to be first erased pixel-by-pixel along with the z-buffer memory for the window in use before the new image could be drawn.
  • This erasure of the frame buffer and z-buffer memory by conventional means for the new window data is very time consuming because it must be done one pixel at a time.
  • the erasure step is bypassed by setting the back buffer dirty bit DIRTY BB in the pixel tag memory 24 for all pixels of the display.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Image Input (AREA)
  • Processing Of Color Television Signals (AREA)
  • Image Processing (AREA)
EP19900125789 1990-01-08 1990-12-28 Digital color video system using dirty bits to provide high speed pixel data for raster displays Withdrawn EP0436959A3 (en)

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US45953790A 1990-01-08 1990-01-08
US459537 1990-01-08

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EP0436959A3 EP0436959A3 (en) 1992-03-04

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4431304A1 (de) * 1993-09-13 1995-03-16 Ind Tech Res Inst Aufbau eines Graphikspeichers für ein Anzeigesystem mit mehreren Betriebsarten
GB2476338A (en) * 2009-12-17 2011-06-22 Advanced Risc Mach Ltd Forming a Windowing Display in a Tiled Frame Buffer Using Dirty Pixel Data

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1989001218A1 (en) * 1987-07-24 1989-02-09 Apollo Computer, Inc. Display controller utilizing attribute bits

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1989001218A1 (en) * 1987-07-24 1989-02-09 Apollo Computer, Inc. Display controller utilizing attribute bits

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4431304A1 (de) * 1993-09-13 1995-03-16 Ind Tech Res Inst Aufbau eines Graphikspeichers für ein Anzeigesystem mit mehreren Betriebsarten
DE4431304C2 (de) * 1993-09-13 1998-02-19 Ind Tech Res Inst Steuerschaltung für die Farbsteuerung einer Anzeigevorrichtung in unterschiedlichen Betriebsarten
GB2476338A (en) * 2009-12-17 2011-06-22 Advanced Risc Mach Ltd Forming a Windowing Display in a Tiled Frame Buffer Using Dirty Pixel Data
US8803898B2 (en) 2009-12-17 2014-08-12 Arm Limited Forming a windowing display in a frame buffer
GB2476338B (en) * 2009-12-17 2014-10-15 Advanced Risc Mach Ltd Forming a windowing display in a frame buffer

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JPH04131895A (ja) 1992-05-06

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