EP0427016B1

EP0427016B1 - An electronic comparator device with hysteresis

Info

Publication number: EP0427016B1
Application number: EP90119873A
Authority: EP
Inventors: Fabrizio Sacchi; Loic Lietar; Gianfranco Vai; Giorgio Betti
Original assignee: STMicroelectronics SRL; SGS Thomson Microelectronics SRL
Current assignee: STMicroelectronics SRL
Priority date: 1989-11-10
Filing date: 1990-10-17
Publication date: 1997-12-29
Anticipated expiration: 2010-10-17
Also published as: IT8922335A0; JPH03220913A; IT1236692B; KR910010853A; DE69031863T2; EP0427016A2; KR100195395B1; DE69031863D1; IT8922335A1; EP0427016A3; US5126591A

Description

This invention relates to an electronic comparator with hysteresis as defined in the preamble of claim 1. A comparator of this type is known from Patent Abstrats of Japan, vol.7, no. 111, (E-175) [1256], May 14, 1983; & JP-A-58-33318.
As is well known, comparator devices are widely used in a multiplicity of electronic control and actuation circuits to determine the moment that a signal having a waveform whatever reaches a given reference level.
A known comparator type is comprised, for instance, of an operational amplifier, to the non-inverting input whereof a waveform to be compared is applied, whilst a reference or threshold voltage value Vs is maintained on its inverting input.
The comparator output takes a different value according to whether the amplitude of the signal in question lies below or above the threshold level. Normally, the output will only take two different levels, thus providing a binary function.
Where the input signal to the comparator results from the charging and discharging of a capacitor, to be provided by a current Io, said voltage signal may have two limiting waveforms according to the capacitor value. Such waveforms comprise a sawtooth broken line composed of a first, positive gradient slope, corresponding with the capacitor charging step, which merges with a successive, negative gradient slope corresponding with the discharge step.
The patterns for these curves are also shown in Figure 4 of the accompanying drawings.
Comparators according to the prior art generally have a fixed threshold level which is predetermined and causes the comparator output to change over at different times according to the gradient of the input signal waveform.
It could be also considered of keeping the value of the threshold voltage slightly above the so-called "clamp" voltage level, that is that voltage value from where the slope of the input signal will rise on the capacitor being charged.
However, by so doing, the comparator would be made highly sensitive to noise and deprived of a sufficient accuracy margin versus small variations in the threshold voltage and the so-called "offset" voltage drop between input and output.
The technical problem that underlies this invention is to provide a comparator having such structural and functional characteristics as to attenuate the dependence of the output change-over on the gradient of the input signal waveform, and, more particularly a comparator which has a threshold value dependent, with high-precision hysteresis, on the output value.
The technical problem is solved by a comparator as defined in claim 1.
The features and advantages of a comparator according to the invention will become apparent from the following detailed description of an embodiment thereof, given by way of illustration and not of limitation with reference to the accompanying drawings.
In the drawings:

Figure 1 is a diagramatic view of the comparator of this invention;
Figures 2 and 3 show respective schematical patterns for waveforms of signals appearing on the input and the output of the comparator shown in Figure 1; and
Figure 4 shows the pattern for signal waveforms in prior art comparators.

With reference to the drawing views, generally and schematically shown at 1 is an electronic comparator device having, in accordance with the invention, a threshold voltage Vs variable with high-precision hysteresis.
The device 1 comprises a first differential cell 2 composed of a pair of npn-type transistors T2 and T3, having their respective emitters connected together and to ground via a current source Io.
The base B2 of transistor T2 is connected to a terminal IN constituting a signal input for the comparator 1 and on which a voltage signal Vin appears having the pattern depicted by the broken line 3 in Figure 2 and resulting from charging and subsequently discharging a capacitor C through which the current Io is caused to flow.
The base B3 of transistor T3 constitutes instead the threshold input S for the comparator 1 on which a voltage value Vs is present which follows the pattern depicted by the broken line 8 in Figure 2.
The respective collectors C2 and C3 of the transistors T2 and T3 are connected to a positive supply pole +Vc via a pair of transistors T4 and T5 connected together into a current mirror configuration. The transistors T4 and T5 are both of the pnp type, with their respective bases connected together. The former transistor is associated, in a diode configuration, with the transistor T2, whilst the transistor T5 has its collector C5 connected both to the collector C3 and the base B6 of a pnp transistor T6 having the emitter E6 connected to the pole Vc.
This transistor T6 has the collector C6 connected to an output terminal OUT, constituting the output for the comparator 1, and to ground via a source Io.
Also provided are a pair of transistors T1, T15 connected together into a Darlington configuration, with the emitter E15 connected to the base B1 and the respective collectors C1, C15 connected to the supply pole Vc. Both of these transistors are of the npn type, and a reference voltage value Vref is maintained on the base B15 of transistor T15.
The emitter E1 of transistor T1 is connected to the input terminal IN and to ground through a current source having the value of 2Io.
Further provided in the comparator 1 is a second differential cell 9 comprising a pair of transistors T9 and T10, of the npn type, with the respective emitters connected together and to ground through a source of bias current having the value of 2Io.
The transistor T9 has, as an input for the cell 9, its base B9 connected directly to the output terminal OUT and its collector C9 connected to the supply pole Vc. The other transistor T10 has its base B10 connected, as a second input, both to ground via a current source Io, and to the emitter E14 of an npn transistor T14 connected in the device 1 into a diode configuration with the collector C14 connected directly to the emitter E15 of the transistor T15.
A second current mirror 5 composed of pnp-type transistors T7 and T8 having their respective emitters connected to the pole Vc and the bases connected together, connects a current source Io to the collector C10 of transistor T10. In particular, the transistor T7 has, in a diode configuration, its collector C7 connected to said source Io, whilst the collector C8 of transistor T8 is connected to the collector C10.
The threshold input S is also connected to said collector C10 of transistor T10 in the cell 9.
According to the present invention, the comparator 1 is provided with a circuit portion 10 effective to regulate the voltage value Vs present on the threshold input S.
Specifically, that circuit portion 10 comprises a pair of transistors T11, T13 of the npn type having respective bases B11, B13 which are both connected to the emitter E15 of the transistor T15, and respective collectors C11, C13 connected to the pole Vc.
In addition, the emitter E11 of transistor T11 is connected to the collector C12 of a further npn transistor T12 also connected to the collector C10 as an output for the portion 10.
The aforesaid transistor T12 is connected in the portion 10, into a diode configuration with the emitter E12 connected to the emitter E13 of transistor T13 and to ground through a transistor T16 operative as a current source with a value of 2Io.
The operation of the inventive comparator will be now described with reference to Figures 2 to 4 showing waveforms of signals having the same time base.
Up to time to, the value of the voltage Vin present on the input terminal IN will keep always above a so-called clamp value given by the following relation: $Vin = Vref - 2Vbe$
where Vref is the value of the reference voltage present on the base B15 of transistor T15, and 2Vbe is the sum of the base-emitter voltage drops present on the transistors T1 and T15.
The voltage present on the base B10 of transistor T10 will coincide with said voltage value Vin present on the terminal IN, due to the base-emitter voltages of the transistors T14 and T15 which are conducting at all times.
Under such conditions, the output terminal OUT will be at a logic high, because of the presence of a voltage value Vout thereon, which is indicated at 8 in Figure 3 and equal to: $Vout = Vc - Vce sat$
where Vce is the collector-emitter voltage drop of the transistor T6 in saturation.
This is due to the transistor T9 of the cell 9 being in conduction, whilst the transistor T10 is in the off state and the mirrored current Io from the mirror 5, composed of the transistors T7 and T8, can only flow, therefore, through the transistor T12.
The transistor T13 is also conducting and a current Io flows therethrough which is drained off, along with that flowing through the parallel transistor T12, by the transistor source T16 which will impose a current value of 2Io.
The value of the threshold voltage Vs present on the terminal S is indicated by the broken line 6 in Figure 2.
The voltage present on the base B13 of transistor T13, and hence on the base B1₁, is given by the reference Vref less the base-emitter voltage drop of transistor T15. But that voltage value is also present on the collector C12 of transistor T12, on the emitter E11 and the base B3 of transistor T3, being the equivalent of the threshold input S, to keep the transistor T11 off and the transistor T3 conducting because the voltage Vs on the base B3 is higher than that on the input terminal IN.
The transistor T2 is in the off state and the current flowing through the transistor T3 brings the transistor T6 to saturation while maintaining the voltage on the output OUT stable and at a logic high.
At the time t1, the positive gradient slope of the voltage Vin signal 3 present on the input terminal IN, shown in Figure 2, will have reached a value of Vref - Vbe.
The transistor T2 will be then turned on and the transistor T3 be simultaneously turned off. Consequently, the mirrored current from the mirror 4, comprising the transistors T4 and T5, will drive the transistor T6 off, causing the output OUT to change over to a logic low. Thus, the value Vs of the threshold voltage is reduced stepwise on the first change-over of the comparator output OUT.
Since the base of the transistor T9 is connected to the output OUT, this transistor will change over to an off state, thus enabling the other transistor T10 to be on and conduct a current of 2Io.
The current flowing through the transistor T10 is twice that mirrored through the transistor T8, which turns on the transistor T11 to conduct, in turn, a current Io.
The voltage Vs on the base B3 will then decrease to a value given by: $Vref - Vbe (T15) - Vbe (T11)$
where the Vbe entries denote the respective base-emitter voltage drops of the transistors T15 and T11 with one and the same current Io flowing therethrough.
This voltage is in all cases higher than the starting voltage value on the terminal IN at time to, because the current flown through the transistor T1 at time to was twice that flown through T11 at time t1.
At a successive time, indicated at t2, the voltage Vin on the input IN will change to a pattern represented by the down slope of the signal 3, e.g. due to the capacitor C being discharged.
The voltage value Vout on the output OUT will remain at a logic low until the voltage on the input IN reaches, at the time t3, the value indicated by relation (3) above.
On that value being reached, the transistor T2 will be turned off and transistor T3 turned on, which restores the circuit to its original state with the output OUT value at a high.
The voltage on the input IN will continue to decrease until it reaches the original clamp value given by relation (1) above.
It will be appreciated from the foregoing description that the comparator device according to the invention has a major advantage in that it is provided with a threshold input which follows substantially the pattern of the output voltage Vout. This allows a considerable reduction in the time range when the output is changed over as the gradient of the input signal varies. In addition, the comparator hysteresis is a high-precision one.
It may be also appreciated comparatively from Figure 4 that the time when the output Vout would be changed over, using a fixed threshold comparator according to the prior art, would be dependent on the gradient of the slope 3 and show considerable variability.

Claims

An electronic comparator (1) with hysteresis comprising
- a first differential cell (2) having a signal input (IN), a signal output (OUT) and a threshold input (S), said signal input (IN) and signal output (OUT) being the input and output terminals, respectively, of the comparator (1),

- a second differential cell (9) having a first input (B9) connected to said signal output (OUT), an output (C10) connected to said threshold input (S) and a second input (B10) and

- a controlling circuit portion (10) having a first terminal (E14) connected to said second input (B10) of the second differential cell (9) and a second terminal (E11) connected to said threshold input (S) and being responsive to a change-over of the output (C10) of said second differential cell (9) caused by a change-over of said signal output (OUT) to lower the threshold voltage level at said threshold input (S),
characterized in that said controlling circuit portion (10) comprises a first transistor (T14) in a diode configuration with its emitter (E14) connected to the second input (B10) of said second differential cell (9) and, via a first current source (I₀), to ground and its common base and collector terminals connected to a voltage supply pole (Vc) via a second transistor (T15) having a reference voltage (V_REF) at its base, third (T11) and fourth (T13) transistors having respective bases (B11, B13) connected to the common base and collector terminals (C14) of said first transistor (T14) and respective collectors (C11, C13) connected to said voltage supply pole (Vc), as well as a fifth transistor (T12) in a diode configuration and having its base and collector terminals (C12) connected to the emitter (E11) of the third transistor (T11), constiuting said second terminal of said controlling circuit portion (10), and its emitter (E12) connected both to the emitter (E13) of said fourth transistor (T13) and, via a second current source (T16), to ground, said change-over of the output (C10) of the second differential cell (9) causing the third transistor (T11) to switch.
A comparator according to Claim 1, characterized in that it comprises a sixth transistor (T1) connected to the second transistor (T15) in a Darlington configuration with respective collectors (C1, C15) connected to the voltage supply pole (Vc) and the emitter (E1) of the sixth transistor (T1) connected to said signal input (IN) of the comparator.
A comparator according to Claim 2, characterized in that it comprises a current mirror (5) connected between a current source (Io) having a predetermined value and said second terminal (E11) of said circuit portion (10).