EP0417715A1 - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the same Download PDFInfo
- Publication number
- EP0417715A1 EP0417715A1 EP90117452A EP90117452A EP0417715A1 EP 0417715 A1 EP0417715 A1 EP 0417715A1 EP 90117452 A EP90117452 A EP 90117452A EP 90117452 A EP90117452 A EP 90117452A EP 0417715 A1 EP0417715 A1 EP 0417715A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- well
- conductivity type
- ions
- forming
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 150000002500 ions Chemical class 0.000 claims abstract description 24
- 238000009792 diffusion process Methods 0.000 claims abstract description 23
- 239000012535 impurity Substances 0.000 claims abstract description 16
- 239000003990 capacitor Substances 0.000 claims abstract description 12
- 238000002347 injection Methods 0.000 claims description 11
- 239000007924 injection Substances 0.000 claims description 11
- 238000000034 method Methods 0.000 abstract description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 14
- -1 boron ions Chemical class 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 229910052796 boron Inorganic materials 0.000 description 7
- 229910052698 phosphorus Inorganic materials 0.000 description 7
- 239000011574 phosphorus Substances 0.000 description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 230000015654 memory Effects 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/01—Bipolar transistors-ion implantation
Definitions
- the present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a complementary MOS integrated circuit with wells and a method of manufacturing the same.
- DRAM memories introduce a vertical structure more often than a conventional planar structure. Capacitors of a trench structure are therefore used in such DRAM memories.
- Various problems are encountered in the manufacture of memories with trench capacitors. One of the problems is that a well is made deep in order to suppress leakage between trenches of shallow wells.
- CMOS IC complementary CMOS integrated circuit
- a p-type silicon substrate 1 having impurity condition of 1 ⁇ 1015 to 5 ⁇ 1015 cm ⁇ 3 is subjected to thermal oxidation under an oxygen atmosphere to form a first oxide film 2 having a thickness of 1000 angstroms (Fib. 4A).
- a photoresist 3 is deposited on the first oxide film 2 is selectively patterned so as to remain on an region where an n-type well is to be formed in order to form a p-type well.
- boron ions are injected.
- a first damage layer 4 is formed by inactive borons (Fig. 4B).
- the oxide film 2 on the p-well region is removed using ammonium fluoride liquid (NH4F) and using the photoresist 3 as a mask. Thereafter, the photoresist 3 is removed (Fig. 4C).
- a p-type well 6 is formed through thermal diffusion of boron ions under oxidation atmosphere.
- an oxide film 5 is formed at the same time on the p-type well so that a step or a level difference between oxide films is formed on the surface of the silicon substrate 1, of which the step is used as the alignment mark (Fig. 4D).
- a photoresist 7 is selectively patterned on the p-type well region.
- phosphorus ions are injected.
- a second damage layer 8 is formed by inactive phosphorus ions (Fig. 4E).
- a trench capacitor is formed on the semiconductor substrate by using suitable conventional manufacturing methods.
- OSFs occur more often in the p-type boron ion injection region than the n-type phosphorus ion injection region, and increase in proportion with the ion injection dose.
- a process of patterning a photoresist is required to be carried out twice in forming a twin well, thereby posing an increased number of manufacturing processes.
- a semiconductor device having a first well of a first conductivity type formed on the entire surface of a semiconductor substrate and having a higher impurity concentration than that of the semiconductor substrate and a second well of a second conductivity type opposite to the first conductivity type formed within a desired region of the first well, wherein the depth of the first well is greater than that of the second well.
- a method of manufacturing a semiconductor device comprising the steps of: forming an oxide film on the surface of a semiconductor substrate, and thereafter injecting ions of a first conductivity type on the entire surface of the semiconductor substrate; forming a first well through a first thermal diffusion; injecting ions of a second conductivity type through the oxide film into a region where a second well is to be formed within the first well; and removing the oxide film formed on the second well region, and thereafter forming a second well having a depth smaller than that of the first well.
- a method of manufacturing a semiconductor device comprising the steps of: forming an oxide film on the surface of a semiconductor substrate, and thereafter injecting ions of a first conductivity type on the entire surface of the semiconductor substrate; selectively inujecting ions of a second conductivity type into a predetermined region, the injection of the second conductivity type ions being shallower than that of said first conductivity type ions; removing the oxide film formed on the surface of said predetermined region; and forming through thermal diffusion a second well of the second conductivity type ions within a first well of the first conductivity type ions, the depth of the first well being greater than that of the second well.
- Semiconductor devices according to the present invention can considerably reduce leakage between trenches of trench capacitors. According to the method of manufacturing a semiconductor device of this invention crystalline defects in the formation of a twin well can be effectively suppressed.
- FIG. 1E A semiconductor according to an embodiment of this invention is shown in Fig. 1E.
- the surface of the substrate is formed with an oxide film 5 (SiO2).
- the depth of the first well is about 10 microns, and that of the second well is about 5 microns.
- the depth of the first well is two times that of the second well.
- a trench capacitor formed in such semiconductor device e.g., DRAM
- a p-type silicon substrate 1 is subjected to thermal oxidation under oxygen atmosphere to form an oxide film 2 having a thickness of 1000 angstroms. Thereafter, boron ions are injected over the entire surface of the p-type silicon substrate 1 through the oxide film 2, under the conditions that the injection energy is 150 keV and the dose is 1.5 ⁇ 1013 cm ⁇ 2. In this case, a damage layer 4 is formed by boron ion injection (Fig. 1A).
- first well 6 p-type well region
- thermal diffusion (1190°C, 200 minutes) is carried out under oxygen atmosphere.
- the surface of the first damage layer 4 on the silicon substrate 1 is covered with the oxide film 2 so that OSFs will not occur even during the thermal oxidation under oxygen atmosphere (Fig. 1B).
- a photoresist 3 is selectively patterned to cover the region other than the region where a well is to be formed.
- phosphorus ions are injected, under the conditions that the injection energy is 150 keV and the injection dose is 2.5 ⁇ 1013 cm ⁇ 2.
- a damage layer 8 is formed by inactive phosphorus (Fig. 1C).
- the oxide film 2 on the n-well region is etched using ammonium fluoride liquid (NH4F) and using the patterned photoresist 3 as a mask. Thereafter, the photoresist is removed (Fig. 1D).
- ammonium fluoride liquid N4F
- thermal diffusion (1190°C, 480 minutes) is carried out for the purpose of activation of impurities and obtaining a desired diffusion depth, to thereby form a second well 9 (n-type well region) and thus a twin well.
- a twin well can be formed while suppressing occurrence of OSFs particularly in the region where p-type ions are injected.
- the first thermal diffusion is carried out for forming a deep p-type well in a DRAM having a trench capacitor.
- the first thermal diffusion is omitted and the second thermal diffusion is used for both p-type and n-type well diffusion.
- Fig 2A boron ions
- Fig. 2B phosphorus ions are selectively injected
- thermal diffusion is carried out to thereby realize the structure (Fig. 2D) same as shown in Fig. 1E.
- this invention is applicable to forming a triple threefold well by forming the third well after forming the second well 9 in the similar manner described above.
- a multiple well such as quadruple-well, quintuple-well and so on, may also be formed.
- the invention is applicable to an n-type silicon substrate.
- the first well is of p-type and the second well is of n-type, this conduction type may be reversed.
- the profile of impurities in n-type well substantially the same as conventional can be realized by properly setting the first thermal diffusion time, phosphorus ion injection conditions (acceleration energy, dose) for the formation of an n-type well region, and second thermal diffusion time.
- the profile of impurity concentration in an n-type well according to this invention is shown in Fig. 3, and the profile of impurity concentration in a conventional n-type well is shown in Fig. 5.
- both the profiles are substantially the same.
- thermal diffusion is carried out while covering the surface of the silicon substrate 1 with the oxide film 2 so that the occurrence of OSFs can be suppressed in the order of 0.2/cm2 and the pn-junction leakage can also be suppressed, allowing the formation of a semiconductor device of high quality and reliability.
- a conventional method requires two processed of patterning a photoresist, whereas the present invention requires one photoresist patterning process thereby reducing the number of processes.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
- The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a complementary MOS integrated circuit with wells and a method of manufacturing the same.
- As integrated circuits are miniaturized more and more, memories such as DRAM memories introduce a vertical structure more often than a conventional planar structure. Capacitors of a trench structure are therefore used in such DRAM memories. Various problems are encountered in the manufacture of memories with trench capacitors. One of the problems is that a well is made deep in order to suppress leakage between trenches of shallow wells.
- A conventional method of forming a twin well in a complementary CMOS integrated circuit (hereinafter simply called CMOS IC) will be described with reference to Figs. 4A to 4F.
- A p-
type silicon substrate 1 having impurity condition of 1 × 10¹⁵ to 5 × 10¹⁵ cm⁻³ is subjected to thermal oxidation under an oxygen atmosphere to form afirst oxide film 2 having a thickness of 1000 angstroms (Fib. 4A). - A
photoresist 3 is deposited on thefirst oxide film 2 is selectively patterned so as to remain on an region where an n-type well is to be formed in order to form a p-type well. By using thisphotoresist 3 as a mask, boron ions are injected. In this case, afirst damage layer 4 is formed by inactive borons (Fig. 4B). - Next, in order to form an alignment mark to be used at the succeeding photoetching process, the
oxide film 2 on the p-well region is removed using ammonium fluoride liquid (NH₄F) and using thephotoresist 3 as a mask. Thereafter, thephotoresist 3 is removed (Fig. 4C). - In order to form the alignment mark for the photoetching process, a p-
type well 6 is formed through thermal diffusion of boron ions under oxidation atmosphere. In this case, anoxide film 5 is formed at the same time on the p-type well so that a step or a level difference between oxide films is formed on the surface of thesilicon substrate 1, of which the step is used as the alignment mark (Fig. 4D). - Next, a
photoresist 7 is selectively patterned on the p-type well region. By using the patternedphotoresist 7 as a mask, phosphorus ions are injected. In this case, asecond damage layer 8 is formed by inactive phosphorus ions (Fig. 4E). - Next, after removing the
photoresist 7, thermal diffusion is carried our for the purpose of activation of impurities and obtaining a desired diffusion depth, to thereby form an n-type well 9 and thus a twin well (Fig. 4F). Thereafter, a trench capacitor is formed on the semiconductor substrate by using suitable conventional manufacturing methods. - In the above conventional technique, thermal diffusion under an oxygen atmosphere for the exposed p-type well region on the
silicon substrate 1, for example, at step shown in Fig. 4C, may cause Oxidation-induced Staking Faults (OSF). OSFs occur more often in the p-type boron ion injection region than the n-type phosphorus ion injection region, and increase in proportion with the ion injection dose. In addition, in forming trench capacitors in DRAM memories as described previously, it is necessary to form a deep p-type well region in order to suppress leakage between trenches. In order to form a deep p-type well, it is necessary to increase the boron ion injection dose and form at first a p-type well, so that OSFs are likely to occur. - Furthermore, a process of patterning a photoresist is required to be carried out twice in forming a twin well, thereby posing an increased number of manufacturing processes.
- It is therefore an object of this invention to provide a twin well of novel structure.
- It is another object of this invention to provide a semiconductor device of high reliability by suppressing occurrence of crystalline defects in the formation of a twin well.
- it is a further object of this invention to provide a method of manufacturing a semiconductor device of high reliability by reducing the number of manufacturing steps.
- According to the present invention, there is provided a semiconductor device having a first well of a first conductivity type formed on the entire surface of a semiconductor substrate and having a higher impurity concentration than that of the semiconductor substrate and a second well of a second conductivity type opposite to the first conductivity type formed within a desired region of the first well, wherein the depth of the first well is greater than that of the second well.
- According to the present invention, there is also provided a method of manufacturing a semiconductor device comprising the steps of: forming an oxide film on the surface of a semiconductor substrate, and thereafter injecting ions of a first conductivity type on the entire surface of the semiconductor substrate; forming a first well through a first thermal diffusion; injecting ions of a second conductivity type through the oxide film into a region where a second well is to be formed within the first well; and removing the oxide film formed on the second well region, and thereafter forming a second well having a depth smaller than that of the first well.
- According to the present invention, there is further provided a method of manufacturing a semiconductor device comprising the steps of: forming an oxide film on the surface of a semiconductor substrate, and thereafter injecting ions of a first conductivity type on the entire surface of the semiconductor substrate; selectively inujecting ions of a second conductivity type into a predetermined region, the injection of the second conductivity type ions being shallower than that of said first conductivity type ions; removing the oxide film formed on the surface of said predetermined region; and forming through thermal diffusion a second well of the second conductivity type ions within a first well of the first conductivity type ions, the depth of the first well being greater than that of the second well.
- Semiconductor devices according to the present invention can considerably reduce leakage between trenches of trench capacitors. According to the method of manufacturing a semiconductor device of this invention crystalline defects in the formation of a twin well can be effectively suppressed.
-
- Figs. 1A to 1E are cross sections illustrating the manufacturing processes for a semiconductor device according to the present invention;
- Figs. 2A to 2D are cross sections illustrating the manufacturing processes according to a second embodiment of this invention;
- Fig. 3 shows the profile of impurities in an N-type well according to the present invention;
- Figs. 4A to 4F are cross sections illustrating the manufacturing processes for a conventional semiconductor device; and
- Fig 5 shows the profile of impurities in a conventional N-type well.
- A semiconductor according to an embodiment of this invention is shown in Fig. 1E.
- On a p-type silicon substrate (1 to 5× 10¹⁵ cm⁻³ impurity concentration), there are formed a first well 6 (p=type well region, 3 × 10¹⁶ cm⁻³) and a second well 9 (n-type well region, 6 × 10¹⁶ cm⁻³). The surface of the substrate is formed with an oxide film 5 (SiO₂). The depth of the first well is about 10 microns, and that of the second well is about 5 microns. The depth of the first well is two times that of the second well. A trench capacitor formed in such semiconductor device (e.g., DRAM) has a depth of 3 to 5 microns so that leakage between trenches is considerably small.
- The method of manufacturing such a semiconductor device of this embodiment will be described with reference to Figs. 1A to 1E.
- A p-
type silicon substrate 1 is subjected to thermal oxidation under oxygen atmosphere to form anoxide film 2 having a thickness of 1000 angstroms. Thereafter, boron ions are injected over the entire surface of the p-type silicon substrate 1 through theoxide film 2, under the conditions that the injection energy is 150 keV and the dose is 1.5 × 10¹³ cm⁻². In this case, adamage layer 4 is formed by boron ion injection (Fig. 1A). - In order to form a first well 6 (p-type well region), thermal diffusion (1190°C, 200 minutes) is carried out under oxygen atmosphere. During this thermal diffusion, the surface of the
first damage layer 4 on thesilicon substrate 1 is covered with theoxide film 2 so that OSFs will not occur even during the thermal oxidation under oxygen atmosphere (Fig. 1B). - Next, a
photoresist 3 is selectively patterned to cover the region other than the region where a well is to be formed. By using thisphotoresist 3 as a mask, phosphorus ions are injected, under the conditions that the injection energy is 150 keV and the injection dose is 2.5 × 10¹³ cm⁻². Adamage layer 8 is formed by inactive phosphorus (Fig. 1C). - Next, in order to form an alignment mark to be used at the succeeding photoetching process, the
oxide film 2 on the n-well region is etched using ammonium fluoride liquid (NH₄F) and using the patternedphotoresist 3 as a mask. Thereafter, the photoresist is removed (Fig. 1D). - Next, thermal diffusion (1190°C, 480 minutes) is carried out for the purpose of activation of impurities and obtaining a desired diffusion depth, to thereby form a second well 9 (n-type well region) and thus a twin well.
- In the above manner, a twin well can be formed while suppressing occurrence of OSFs particularly in the region where p-type ions are injected.
- In the above embodiment of this invention, the first thermal diffusion is carried out for forming a deep p-type well in a DRAM having a trench capacitor. For a DRAM without a trench capacitor (using a stacked capacitor or a planar capacitor), the first thermal diffusion is omitted and the second thermal diffusion is used for both p-type and n-type well diffusion. Specially, after injecting boron ions (Fig 2A), phosphorus ions are selectively injected (Fig. 2B) and thermal diffusion is carried out to thereby realize the structure (Fig. 2D) same as shown in Fig. 1E.
- Furthermore, a although a twin well is formed in the embodiment, this invention is applicable to forming a triple threefold well by forming the third well after forming the second well 9 in the similar manner described above. By repeating the above steps, a multiple well such as quadruple-well, quintuple-well and so on, may also be formed.
- Although a p-type silicon substrate is used, the invention is applicable to an n-type silicon substrate.
- Furthermore, although the first well is of p-type and the second well is of n-type, this conduction type may be reversed.
- As described in detail, according to the present invention, the profile of impurities in n-type well substantially the same as conventional can be realized by properly setting the first thermal diffusion time, phosphorus ion injection conditions (acceleration energy, dose) for the formation of an n-type well region, and second thermal diffusion time. The profile of impurity concentration in an n-type well according to this invention is shown in Fig. 3, and the profile of impurity concentration in a conventional n-type well is shown in Fig. 5. As understood from Figs. 3 and 5, both the profiles are substantially the same.
- According to the present invention, in forming the p-type well, thermal diffusion is carried out while covering the surface of the
silicon substrate 1 with theoxide film 2 so that the occurrence of OSFs can be suppressed in the order of 0.2/cm² and the pn-junction leakage can also be suppressed, allowing the formation of a semiconductor device of high quality and reliability. - Furthermore, in forming a twin well, a conventional method requires two processed of patterning a photoresist, whereas the present invention requires one photoresist patterning process thereby reducing the number of processes.
- Reference signs in the claims are intended for better understanding and shall not limit the scope.
Claims (6)
forming an oxide film (2) on the surface of a semiconductor substrate (1), and thereafter injecting ions of a first conductivity type on the entire surface of said semiconductor substrate;
forming a first well (6) through a first thermal diffusion;
injecting ions of a second conductivity type through said oxide film into a region where a second well is to be formed within said first well; and
removing said oxide film formed on said second well region, and thereafter forming a second well (9) having a depth smaller than that of said first well.
forming an oxide film (2) on the surface of a semiconductor substrate (1), and thereafter injecting ions of a first conductivity type on the entire surface of said semiconductor substrate;
selectively injecting ions of a second conductivity type into a predetermined region, said injection of said second conductivity type ions being shallower than that of said first conductivity type ions;
removing said oxide film formed on the surface of said predetermined region; and
forming through thermal diffusion a second well (9) of said second conductivity type ions within a first well (6) of said first conductivity type ions, the depth of said first well being greater than that of said second well.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1232904A JPH081930B2 (en) | 1989-09-11 | 1989-09-11 | Method for manufacturing semiconductor device |
JP232904/89 | 1989-09-11 |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0417715A1 true EP0417715A1 (en) | 1991-03-20 |
EP0417715B1 EP0417715B1 (en) | 1997-11-12 |
Family
ID=16946660
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP90117452A Expired - Lifetime EP0417715B1 (en) | 1989-09-11 | 1990-09-11 | Method of manufacturing a semicondcutor device |
Country Status (5)
Country | Link |
---|---|
US (2) | US5460984A (en) |
EP (1) | EP0417715B1 (en) |
JP (1) | JPH081930B2 (en) |
KR (1) | KR940004454B1 (en) |
DE (1) | DE69031702T2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0764983A2 (en) * | 1995-09-19 | 1997-03-26 | Siemens Aktiengesellschaft | Semiconductor device and method of manufacturing the same |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2682425B2 (en) * | 1993-12-24 | 1997-11-26 | 日本電気株式会社 | Method for manufacturing semiconductor device |
JPH0878776A (en) * | 1994-09-06 | 1996-03-22 | Fuji Xerox Co Ltd | Semiconductor laser device |
US5573963A (en) * | 1995-05-03 | 1996-11-12 | Vanguard International Semiconductor Corporation | Method of forming self-aligned twin tub CMOS devices |
KR0146080B1 (en) * | 1995-07-26 | 1998-08-01 | 문정환 | Manufacturing method of twin well |
US5573962A (en) * | 1995-12-15 | 1996-11-12 | Vanguard International Semiconductor Corporation | Low cycle time CMOS process |
KR100189739B1 (en) * | 1996-05-02 | 1999-06-01 | 구본준 | Method of forming well for semiconductor wafer |
US5776816A (en) * | 1996-10-28 | 1998-07-07 | Holtek Microelectronics, Inc. | Nitride double etching for twin well align |
CN1067800C (en) * | 1996-11-14 | 2001-06-27 | 联华电子股份有限公司 | Method for making IC |
US6017787A (en) * | 1996-12-31 | 2000-01-25 | Lucent Technologies Inc. | Integrated circuit with twin tub |
DE19752848C2 (en) * | 1997-11-28 | 2003-12-24 | Infineon Technologies Ag | Electrically decoupled field effect transistor in triple well and use of the same |
KR100263909B1 (en) * | 1998-06-15 | 2000-09-01 | 윤종용 | Method for forming multiple well of semiconductor integrated circuit |
FR2826507B1 (en) * | 2001-06-21 | 2004-07-02 | St Microelectronics Sa | PROCESS FOR TREATING COMPLEMENTARY AREAS OF THE SURFACE OF A SUBSTRATE AND SEMICONDUCTOR PRODUCT OBTAINED BY THIS PROCESS |
JP6216142B2 (en) * | 2012-05-28 | 2017-10-18 | キヤノン株式会社 | Manufacturing method of semiconductor device |
CN106653599B (en) * | 2015-11-02 | 2021-03-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method for manufacturing the same |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1987005443A1 (en) * | 1986-03-04 | 1987-09-11 | Motorola, Inc. | High/low doping profile for twin well process |
US4729964A (en) * | 1985-04-15 | 1988-03-08 | Hitachi, Ltd. | Method of forming twin doped regions of the same depth by high energy implant |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3212162A (en) * | 1962-01-05 | 1965-10-19 | Fairchild Camera Instr Co | Fabricating semiconductor devices |
JPS5737877A (en) * | 1980-08-20 | 1982-03-02 | Seiko Epson Corp | Semiconductor device |
DE3149185A1 (en) * | 1981-12-11 | 1983-06-23 | Siemens AG, 1000 Berlin und 8000 München | METHOD FOR THE PRODUCTION OF NEIGHBORS WITH DOPE IMPLANTED TANKS IN THE PRODUCTION OF HIGHLY INTEGRATED COMPLEMENTARY MOS FIELD EFFECT TRANSISTOR CIRCUITS |
US4567644A (en) * | 1982-12-20 | 1986-02-04 | Signetics Corporation | Method of making triple diffused ISL structure |
JPS60105267A (en) * | 1983-11-14 | 1985-06-10 | Toshiba Corp | Manufacture of semiconductor device |
JPS60138955A (en) * | 1983-12-27 | 1985-07-23 | Toshiba Corp | Manufacture of semiconductor device |
JPS60194558A (en) * | 1984-03-16 | 1985-10-03 | Hitachi Ltd | Manufacture of semiconductor device |
JPS63207169A (en) * | 1987-02-24 | 1988-08-26 | Toshiba Corp | Semiconductor storage device and manufacture thereof |
US4795716A (en) * | 1987-06-19 | 1989-01-03 | General Electric Company | Method of making a power IC structure with enhancement and/or CMOS logic |
US5260226A (en) * | 1987-07-10 | 1993-11-09 | Kabushiki Kaisha Toshiba | Semiconductor device having different impurity concentration wells |
US4983534A (en) * | 1988-01-05 | 1991-01-08 | Nec Corporation | Semiconductor device and method of manufacturing the same |
-
1989
- 1989-09-11 JP JP1232904A patent/JPH081930B2/en not_active Expired - Lifetime
-
1990
- 1990-09-10 US US07/580,319 patent/US5460984A/en not_active Expired - Lifetime
- 1990-09-11 KR KR1019900014302A patent/KR940004454B1/en not_active IP Right Cessation
- 1990-09-11 DE DE69031702T patent/DE69031702T2/en not_active Expired - Fee Related
- 1990-09-11 EP EP90117452A patent/EP0417715B1/en not_active Expired - Lifetime
-
1997
- 1997-05-19 US US08/858,879 patent/US6011292A/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4729964A (en) * | 1985-04-15 | 1988-03-08 | Hitachi, Ltd. | Method of forming twin doped regions of the same depth by high energy implant |
WO1987005443A1 (en) * | 1986-03-04 | 1987-09-11 | Motorola, Inc. | High/low doping profile for twin well process |
Non-Patent Citations (5)
Title |
---|
ELECTRONIC DESIGN. vol. 32, no. 24, November 1984, HASBROUCK HEIGHTS, N pages 73 - 100; F. GOODENOUGH: "ADVANCES IN PROCESSING GRAB MOST OF THE ATTENTION AS IEDM'S PROGRAM UNFOLDS" * |
ELECTRONICS. vol. 56, no. 15, July 1983, NEW YORK US pages 47 - 48; M. A. HARRIS: "SCALED-DOWN C-MOS MAY CATAPULT GE TO CHIP FOREFRONT" * |
PATENT ABSTRACTS OF JAPAN vol. 9, no. 255 (E-349)(1978) 12 October 1985, & JP-A-60 105267 (TOSHIBA) 10 June 1985, * |
PATENT ABSTRACTS OF JAPAN vol. 9, no. 298 (E-361)(2021) 26 November 1985, & JP-A-60 138955 (TOSHIBA) 23 July 1985, * |
VLSI AND COMPUTERS - FIRST INTERNATIONAL CONFERENCE ON COMPUTER TECHNOLOGY May 1987, HAMBURG pages 650 - 655; H. IIZUKA et al.: "EVOLUTION OF DRAM IN SILICON MOS TECHNOLOGY" * |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0764983A2 (en) * | 1995-09-19 | 1997-03-26 | Siemens Aktiengesellschaft | Semiconductor device and method of manufacturing the same |
EP0764983A3 (en) * | 1995-09-19 | 1997-04-02 | Siemens Aktiengesellschaft | Semiconductor device and method of manufacturing the same |
US5962901A (en) * | 1995-09-19 | 1999-10-05 | Siemens Aktiengesellschaft | Semiconductor configuration for an insulating transistor |
Also Published As
Publication number | Publication date |
---|---|
EP0417715B1 (en) | 1997-11-12 |
KR910007132A (en) | 1991-04-30 |
DE69031702D1 (en) | 1997-12-18 |
US6011292A (en) | 2000-01-04 |
US5460984A (en) | 1995-10-24 |
JPH0397261A (en) | 1991-04-23 |
DE69031702T2 (en) | 1998-04-02 |
JPH081930B2 (en) | 1996-01-10 |
KR940004454B1 (en) | 1994-05-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2795565B2 (en) | Method for manufacturing semiconductor storage element | |
CA1086868A (en) | Method of manufacturing a semiconductor device utilizing doped oxides and controlled oxidation | |
EP0417715A1 (en) | Semiconductor device and method of manufacturing the same | |
US4808555A (en) | Multiple step formation of conductive material layers | |
EP0369336A2 (en) | Process for fabricating bipolar and CMOS transistors on a common substrate | |
KR100480593B1 (en) | Semiconductor device having align key for defining active region and method for manufacturing the same | |
EP0391561A2 (en) | Forming wells in semiconductor devices | |
KR940003379B1 (en) | Method of making semiconductor device | |
JPH07142419A (en) | Fabrication of semiconductor device | |
KR0179794B1 (en) | Well-forming method of semiconductor device | |
US5994737A (en) | Semiconductor device with bird's beak | |
JPH10308448A (en) | Isolation film of semiconductor device and formation method thereof | |
KR100325596B1 (en) | Method of suppressing the formation of crystal defects in silicon wafers after arsenic ion injection | |
KR100259586B1 (en) | Method for manufacturing semiconductor device | |
KR0150671B1 (en) | Manufacturing method of semiconductor having a different isolation structure between peripheral circuit area and cell area | |
US4771009A (en) | Process for manufacturing semiconductor devices by implantation and diffusion | |
KR910008978B1 (en) | Manufacturing method of semiconductor device | |
KR0169599B1 (en) | Semiconductor device and manufacturing thereof | |
KR100425063B1 (en) | Method for fabricating semiconductor device | |
KR100589493B1 (en) | Method for fabricating gate oxide | |
JPS60240131A (en) | Manufacture of semiconductor device | |
JPH0358430A (en) | Semiconductor device and manufacture thereof | |
JP2926817B2 (en) | Method for manufacturing semiconductor device | |
KR0172545B1 (en) | Method of manufacturing isolation film on the semiconductor | |
KR100218372B1 (en) | Method of manufacturing dual gate of semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
17P | Request for examination filed |
Effective date: 19900911 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): DE FR GB |
|
17Q | First examination report despatched |
Effective date: 19930517 |
|
GRAG | Despatch of communication of intention to grant |
Free format text: ORIGINAL CODE: EPIDOS AGRA |
|
GRAH | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOS IGRA |
|
GRAH | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOS IGRA |
|
GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): DE FR GB |
|
REF | Corresponds to: |
Ref document number: 69031702 Country of ref document: DE Date of ref document: 19971218 |
|
ET | Fr: translation filed | ||
PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
26N | No opposition filed | ||
REG | Reference to a national code |
Ref country code: GB Ref legal event code: 746 Effective date: 19981103 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: D6 |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: IF02 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: FR Payment date: 20020910 Year of fee payment: 13 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: GB Payment date: 20020911 Year of fee payment: 13 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: DE Payment date: 20020918 Year of fee payment: 13 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: GB Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20030911 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: DE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20040401 |
|
GBPC | Gb: european patent ceased through non-payment of renewal fee |
Effective date: 20030911 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: FR Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20040528 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: ST |