EP0390893A1 - Systeme de verification de transmission de donnees par bus - Google Patents

Systeme de verification de transmission de donnees par bus

Info

Publication number
EP0390893A1
EP0390893A1 EP89910715A EP89910715A EP0390893A1 EP 0390893 A1 EP0390893 A1 EP 0390893A1 EP 89910715 A EP89910715 A EP 89910715A EP 89910715 A EP89910715 A EP 89910715A EP 0390893 A1 EP0390893 A1 EP 0390893A1
Authority
EP
European Patent Office
Prior art keywords
data
bus
coupled
output
fault
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP89910715A
Other languages
German (de)
English (en)
Inventor
Larry L. Byers
James H. Scheuneman
Joseba M. Desubijana
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unisys Corp
Original Assignee
Unisys Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unisys Corp filed Critical Unisys Corp
Publication of EP0390893A1 publication Critical patent/EP0390893A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2215—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test error correction or detection circuits

Definitions

  • the present invention is related to a system for checking data parity errors in real time during transmission of data from a transmitter to a " bus and again in real time during transmission of data from a bus to a receiver. More particularly, the present invention is related to novel fault indicating circuits which are placed in series between elements of a high-speed storage unit and the read and write buses for detecting errors in data transmission to and from the elements of the storage unit.
  • the fault indicating circuits are capable of indicating the element at fault, the slice or block of the element at fault and the type of fault even though the elements are hard wired or connected to the read/write buses.
  • Modern high-speed main frame computers employ parity checking circuits and parity , checking systems when accessing information from high-speed cache memories. Such systems are described in U.S. Patent 4,168,541..
  • Main storage units for high-speed main frame computers that employ separate read and write buses also check the parity of the data being transmitted onto the read or write bus.
  • the elements of the main storage units are hardwired or connected to the read or write bus, it is possible to identify the element (card or board) which generated the faulty data but prior art parity check circuits do not identify faults which are generated by the circuitry associated with the board or card.
  • Figure 1 is a block diagram of a main storage unit of a high-speed main frame computer showing the environment of the no-vel fault indicating circuits;
  • Figure 2 is a simplified block diagram of a storage element or card connected between a read bus and a write bus showing the location of the novel fault indicating circuits;
  • Figure 3 is a simplified block diagram of one of the ten logic circuits in a fault indicating circuit;
  • Figure 4 is a detailed block diagram of one of the single bit AND gate circuits in the data path of the AND gates in Figure 3;
  • Figure 5 is a detailed block diagram of a preferred embodiment bit parity comparison circuit in the form of an exclusive OR tree;
  • Figure 6 is a truth table illustrating how the fault indicating latch information in the fault indicating circuits is utilized.
  • FIG. 7 is a detailed schematic block diagram of one of the two logic circuits of a fault indicating circuit.
  • DESCRIPTION OF THE PREFERRED EMBODIMENT Figure 1 is a block diagram of a main storage unit 10 of a main storage complex of a main frame computer.
  • the main storage unit 10 is typical of a sixteen mega word main storage unit of the type which is duplicated in large main frame computers.
  • the main storage unit 10 comprises seven plugable and re oveable card circuit boards or cards which are coupled to a main write data bus 11 and a main read data bus 12.
  • the three left most cards or boards 13, 14 and 15 are input/output interface port cards which communicate with the main processor and peripheral equipment.
  • lines 16, 17 and 18 from port card 13 are lines which connect to instruction processor zero (IPO) , instruction processor 1 (IP1) and one of the input/output processors. Similar lines 19 and 21 are lines coming in from the instruction processors. Other input/output processor (IOP) lines to port card 13 are not shown.
  • line 16B, 17B and 18B from port card 14 are connected to different IPs and IOPs.
  • _ines 16C, 17C and 18C from port card 15 are connected to yet different IPs and IOPs so that lines from port cards 13, 14 and 15 can connect to up to eight instruction processors.
  • a central or pipeline controller 29 occupies one of the seven cards and is connected via control lines to the other six cards or boards to perform sequencing and control functions.
  • Support control card 31 (SO) is basically a utility and auxilliary control card which supplies timing functions and maintenance functions.
  • Support control card 31 also contains error status and logic support functions and is connected to buses 11 and 12 via lines 32 and 33 which have in series therewith the aforementioned fault indicating circuits 22.
  • Storage cards 34 and 35 are preferably dynamic RAM memory cards having four banks of two mega word storage units each for a total of eight mega words each. The individual words are addressed by the central controller 29 via an address bus not shown.
  • Storage card 34 is provided with an input line 36 connected to write bus 11 and an output line 37 connected to a- read bus 12. Connected in series therewith are the novel fault indicating circuits 22.
  • storage card 35 is provided with input line 38 and output line 39 which are also provide ' d with series connected fault indicating circuits 22.
  • the data words on write bus 11 have a parity check bit for each byte of the word which enables the fault indicating circuits 22 to determine faults at the byte level for information being transmitted to the write bus 11.
  • FIG. 2 showing a simplified block diagram of storage card 34 connected to write bus 11 and read bus 12 through fault indicating circuits 22 which comprise a pair of identical bus interface gate arrays 41 (BIGA).
  • Data words on write bus 11 may be designated as an even word which is transmitted on line 36A to the firs gate array 41 •
  • the odd words on line 36B are transmitted to the second gate array 41 for check processing.
  • the output of the processed odd and even words on line 36C ma be stored in any of the banks 42 designated banks 0 to 3.
  • the odd and even words stored in banks 0 to 3 (which ..stor two mega words each) appear as outputs on line 37C.
  • the words from memory are again divided into odd and even data words for processing by first and second gate arrays 41 which comprise the fault indicating circuit 22.
  • FIG. 1 illustrates how the fault indicating circuits are implemented in the form of a pair of identical gate arrays 41 ⁇
  • Figure 3 showing in simplified block diagram one of the five logic circuits which comprise a gate array 41 or one of the ten logic circuits which comprise a fault indicating circuit 22.
  • the data in line 43 comprises one byte of a word which comprises five bytes. With each byte of data on line 43 there is an accompanying parity in check bit on line 44.
  • the parity check bit on line 44 is applied to parity latch 53 and transmitted to AND gate 54 via line 55.
  • the output of AND gate 54 on line 50 is applied as a tenth bit input to the parity check circuit 52 and simultaneously to the read bus 12.
  • the output of the parity check circuit on line 56 is held in the fault indicator latch 57. Five such fault indicating latches 57 are required for each even and each odd word. The information set in these latches is transmitted to the card fault detecting logic (not shown). It will require five logic circuits of the type shown in Figure 3 for each data word and for each gate array 41 •
  • a gate array 41 is capable of handling a complete fi ty bit data wor ..
  • the information produced by the gate array is held in five fault indicating latches 57.
  • the fault indicating circuits 22 shown in Figures 1 and 2 require two gate arrays 41 , thus will require ten of the logic circuits and ten of the fault indicating latches of the type shown in Figure 3-
  • the 50 bits of a data word appearing on lines 43 and 44 are transmitted in parallel to the read bus 12 with one logic switching time delay in register 45 and one delay pulse enable time at gates 47.
  • the parity check circuit and the fault indicating circuit 22 may be operated in real time without any significant delay of data to and from the storage cards.34 and 35.
  • FIG. 4 showing a more detailed block diagram of one of the AND gates 47 and associated logic in the gate array 41 of Figure 2.
  • the data on line 46 and the enable pulse on line ' 49 are applied to one of the nine AND gates 47 to produce an output on line 48A.
  • the output on line 48A is applied to an external driver 59 and an internal driver 61 to produce the aforementioned nine outputs on lines 48 which are applied to the read bus 12 and to produce the input to the parity check circuit 52.
  • the drivers 59, 59A and 61, 61A may be each implemented with a separate driver transistor.
  • the delay time for the data on lines 43 and 46 being transmitted to read bus 12 can be reduced to approximately one nanosecond and the parity check circuits 52 are operated during this real transmission time.
  • the signal on line 48A is coupled through its driver 61 to the parity check circuit 52 before being applied to driver 59•
  • the novel parity check circuits perform their check operation on all portions of the circuitry between the card and the bus except for the single external driver 59.
  • Lines 0 to 8 are the data input lines 48 shown in Figure 3 and 4-
  • the parity input line 55 is shown in Figure 3-
  • the data and parity bit on lines 0 to 9 are applied to high-speed ECL exclusive OR gates 62 to produce a fault indication or NOT fault indication signal on line 56 which is applied to the fault indication latch 57-
  • the logic output on line 56 can be produced in approximately 675 pico seconds after data input, thus, the parity check circuit is operated in real time while the information on line 48 is being applied to the read bus 12.
  • the twelve fault indicating circuits 22 shown in Figure 1 are placed in series in the input and output lines between the six cards and the two data buses and operate in real time without affecting performance of the main storage unit 10.
  • the caption or heading for the two columns indicates that the even word of odd word gate arrays 41 at the transmitter and the receiver may have any one of thei five fault indicating latches 57 locked up indicating an error condition which is capable of isolating the type of error and the location of the error. For example, when a condition C1 occurs, one of the gate arrays 41 has had one of its five latches latched up showing a fault indication at the transmitter and the information that was passed to the bus has been received at one of the receivers. The same even word or odd word being transmitted from the bus to the receiver has one of its five latches in its gate array latched up indicating a fault condition.
  • the fault summary indicates that the transmitted data is at fault.
  • condition C2 When the condition C2 occurs, there was no fault indication of the data being tansmitted to the bus and there was a fault indication of the data being transmitted from the bus to the receiver.
  • the fault summary indicates that the bus or the receiver is at fault.
  • condition C3 When a condition C3 occurs there was a fault indication when the data was transmitted from the transmitter to the bus and no fault indication of the data being transmitted from the bus to the receiver.
  • the fault summary indicates that the transmitted data probably has a multiple bit error. Fault summary data presented in truth table of Figure 6 is sufficient to identify the card or board on which the error occurs because only one transmitter and one receiver operates at the same time with the two buses during any clock cycle.
  • the bus connection is isolated through the aforementioned external driver -59 so that the logic circuitry for each of the gate arrays is individually checked making the assumption that the external driver 59 does not exist in the circuitry. Further, the information stored in fault indicating latches 57 for each of the bytes of each of the words can be locked up and held when a fault indication occurs so that the maintenance controller can read out the information in the latches 57 and determine which portion of a board or card has produced the error indication.
  • FIG. 7 showing a more detailed schematic block diagram of the fault indication circuit gate array * 41 • Por purposes of illustration only, two of the five modules or bytes are being illustrated and all five of the fault indication latches 57 are shown for a data word .
  • Data from the first byte of a data word appears on line 43A and is being applied to the aforementioned nine bit register 45-
  • the second byte of the data word is being applied to line 43B and its nine bit register 45*
  • the parity bit on lines 44A and 44B for the first and second bytes of the data word are shown being applied to their latches 53-
  • the data output from registers 45 on lines 46 are applied to the bank of AND gates 47 to produce the data word on output line 48 which is applied to either the read or write bus.
  • parity data in register 53 and on output line 55 is gated through AND gate 54 to produce the parity data bit on line 50 as explained hereinbefore.
  • the data bits and parity bits on lines 48 and 50 are applied to the parity check circuits 52.
  • the output from the parity check circuits 52 on lines 56 is applied to one of the five fault indicating latches 57A through 57E.
  • the inputs to the fault indicating latches 57 on lines 56A to 56E appear as outputs on lines 58 and are applied to OR gates 64 to produce fault indicating signal outputs on line 65-
  • the fault indication signal on line 65 is applied to a fault indicating hold latch 66 during phase two of the clock cycle to produce a hold or enable signal on line 67 which is applied to the enable inputs of the latches 57A to 57E.
  • the signal on line 67 indicates that a fault or error has occurred in one of the latches and is also indicative of a card error.
  • the signal on line 67 is applied to the fault detection logic (not shown).
  • the maintenance controller of the central processing unit can then scan the latches 57A to 57E to determine which of the bytes of the data word generated the error signal on line- 67. Thus if a single error occurs in one of the latches 57A to 57E when the latches are scanned the byte where the error occurred will be indicated. When two errors occur in two different bytes, the novel error detecting and verification circuit still indicates an error on line 67 and both errors may be detected when the latches 57A to 57E are scanned by the maintenance controller.
  • a plurality of cards or boards are connected to read and write buses 12, 11 and when errors occur it is possible to detect not only the board but the latch associated with the error within the board or card. Even though the individual cards are plugged or hard wired board into the buses it is still possible to isolate individual cards and their associated circuitry from other cards and their associated circuitry. It is possible that single bit errors being generated by the transmitter or the receiver may be corrected without having to block out the portion of a card generating the error.
  • the maintenance controller maintains a history of all errors generated including correctable single bit errors whose causes are corrected during subsequence maintenance. Such maintenance controllers capable of interfacing with the present invenntion are well known and have been used with large main frame computers sold by the Sperry Corporation under models 1100/80 and 1100/90.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

Plusieurs éléments émetteurs et récepteurs sont couplés entre des bus de lecture et d'écriture. Les chemins de communication qui relient les éléments émetteurs et récepteurs aux bus sont pourvus en série, d'un circuit indicateur de fautes. Chaque circuit indicateur de fautes possède des moyens de porte logique qui comprennent un registre de bits pour chacun des bits d'un byte de données et un bit de parité. Les sorties des registres de bits sont couplées aux circuits de commande d'isolement qui, à leur tour, sont connectés à des circuits de vérification de parité et aux bus pour indiquer les erreurs qui se produisent dans les bytes d'un mot de donnée sans dégrader ou retarder la transmission de données vers ou depuis les bus de lecture et d'écriture.
EP89910715A 1988-09-13 1989-09-12 Systeme de verification de transmission de donnees par bus Withdrawn EP0390893A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/244,187 US4962501A (en) 1988-09-13 1988-09-13 Bus data transmission verification system
US244187 1988-09-13

Publications (1)

Publication Number Publication Date
EP0390893A1 true EP0390893A1 (fr) 1990-10-10

Family

ID=22921717

Family Applications (1)

Application Number Title Priority Date Filing Date
EP89910715A Withdrawn EP0390893A1 (fr) 1988-09-13 1989-09-12 Systeme de verification de transmission de donnees par bus

Country Status (4)

Country Link
US (1) US4962501A (fr)
EP (1) EP0390893A1 (fr)
JP (1) JPH03501305A (fr)
WO (1) WO1990002999A1 (fr)

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US5177747A (en) * 1989-10-16 1993-01-05 International Business Machines Corp. Personal computer memory bank parity error indicator
US5235602A (en) * 1991-06-11 1993-08-10 International Business Machines Corporation Synchronous/asynchronous i/o channel check and parity check detector
US5517514A (en) * 1992-11-12 1996-05-14 Amdahl Corporation Parity checking system with reduced usage of I/O pins
US5701313A (en) * 1995-02-24 1997-12-23 Unisys Corporation Method and apparatus for removing soft errors from a memory
US5666371A (en) * 1995-02-24 1997-09-09 Unisys Corporation Method and apparatus for detecting errors in a system that employs multi-bit wide memory elements
US5511164A (en) * 1995-03-01 1996-04-23 Unisys Corporation Method and apparatus for determining the source and nature of an error within a computer system
US5596716A (en) * 1995-03-01 1997-01-21 Unisys Corporation Method and apparatus for indicating the severity of a fault within a computer system
US5966416A (en) * 1996-11-21 1999-10-12 Dsp Group, Inc. Verification of PN synchronization in a spread-spectrum communications receiver
US6535028B1 (en) 2001-11-12 2003-03-18 Deere & Company Data bus fault detection circuit and method
JP2003162673A (ja) * 2001-11-27 2003-06-06 World:Kk 稼動状況に基づく商品選別システム
US7310766B2 (en) * 2004-10-07 2007-12-18 International Business Machines Corporation End-to-end data integrity protection for PCI-Express based input/output adapter
US8230275B2 (en) * 2005-05-26 2012-07-24 Hewlett-Packard Development Company, L.P. Use of parity bits to detect memory installation defects
US7472332B2 (en) * 2005-07-26 2008-12-30 International Business Machines Corporation Method for the reliability of host data stored on fibre channel attached storage subsystems
TWI343753B (en) * 2007-08-09 2011-06-11 Novatek Microelectronics Corp Data slicer having an error correction device
GB201507495D0 (en) * 2015-04-30 2015-06-17 Cooper Technologies Co Bus network terminator

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US4360917A (en) * 1979-02-07 1982-11-23 The Warner & Swasey Company Parity fault locating means
US4414669A (en) * 1981-07-23 1983-11-08 General Electric Company Self-testing pipeline processors
NL8400358A (nl) * 1984-02-06 1985-09-02 Philips Nv Inrichting voor de pariteitsbewaking van pariteitsbits bevattende bitgroepen.
US4670876A (en) * 1985-05-15 1987-06-02 Honeywell Inc. Parity integrity check logic

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Also Published As

Publication number Publication date
WO1990002999A1 (fr) 1990-03-22
US4962501A (en) 1990-10-09
JPH03501305A (ja) 1991-03-22

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