EP0371034A1 - Procede et appareil permettant la gestion de tampons de donnees - Google Patents

Procede et appareil permettant la gestion de tampons de donnees

Info

Publication number
EP0371034A1
EP0371034A1 EP88905495A EP88905495A EP0371034A1 EP 0371034 A1 EP0371034 A1 EP 0371034A1 EP 88905495 A EP88905495 A EP 88905495A EP 88905495 A EP88905495 A EP 88905495A EP 0371034 A1 EP0371034 A1 EP 0371034A1
Authority
EP
European Patent Office
Prior art keywords
block
data
buffer
blocks
scheduling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP88905495A
Other languages
German (de)
English (en)
Other versions
EP0371034A4 (en
Inventor
Kelly J. Beavers
E. Christopher Pisciotta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Exabyte Corp
Original Assignee
Exabyte Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Exabyte Corp filed Critical Exabyte Corp
Publication of EP0371034A1 publication Critical patent/EP0371034A1/fr
Publication of EP0371034A4 publication Critical patent/EP0371034A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level
    • G06F11/1435—Saving, restoring, recovering or retrying at system level using file system or storage system metadata
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements

Definitions

  • This invention pertains to method and apparatus for managing the buffering of informational data between devices, such as the buffering of data between a host computer system and a peripheral storage device. 2. PRIOR ART AND OTHER CONSIDERATIONS.
  • coded informational data is often transmitted in data blocks between a first device (such as a host computer) and a second device (such as a peripheral device which handles a storage medium) , with each data block having a fixed length such as a selected number of data bytes.
  • a first device such as a host computer
  • a second device such as a peripheral device which handles a storage medium
  • each data block having a fixed length such as a selected number of data bytes.
  • Many modern peripheral devices have the capability of determining whether one or more errors occur in the transmission of a block of data between the devices, and of providing an indication that an erroneous or "bad" block has been transmitted.
  • some contemporary magnetic tape handling devices e.g. "tape drives” are able to write a block of data during a first pass and then to read the just-written block during a second pass.
  • Error detection circuitry associated with the tape handling device examines the block read during the second pass to determine whether the block as written on the storage medium is properly readable. If the block as read during the second pass is deemed by the error detection circuitry to contain errors, a signal indicative of the occurrence of the error is generated.
  • an object of the present invention to provide method and apparatus for rewriting blocks of coded data to a storage medium when the block, as initially or earlier written to the storage medium, has been determined to be bad.
  • An advantage of the present invention is the provision of method and apparatus for controlling the physical locations on storage media whereat blocks are rewritten.
  • Another advantage of the present invention is the provision of method and apparatus for increasing the usable storage density of storage media without sacrificing data integrity.
  • a further advantage of the present invention is the provision of method and apparatus for reading a storage medium in a manner whereby rewritten blocks are properly considered in the transmission of data between devices.
  • the data transmission occurs on a buffer data bus which is connected to the first device, the data buffer, and the second device.
  • Data transmission occurs in two modes. In a first mode, also known as an output or write mode, a block of data is transmitted from the first device to a memory location in the data buffer, and thence from that location in the data buffer to the second device. In a second mode, also known as an input or read mode, a block of data is transmitted from the second device to a memory location in the data buffer, and thence from that location in the data buffer to the first device.
  • the micro-controller uses the IPORT circuitry and the DPORT circuitry to generate the addresses of the particular memory locations in the data buffer involved in the transmission of a data block.
  • Both the IPORT circuitry and the DPORT circuitry include, in addition to a sequencer, a set of registers and address generators.
  • the set of registers includes a control register and a plurality of header registers.
  • the header registers are employed, inter alia, in connection with the generation or retrieval of a block header which is included as part of the data block.
  • the address generators included in the IPORT circuitry and the DPORT circuitry utilize information stored in the header registers in order to generate addresses for the particular memory locations in the data buffer at which the header associated with a data block and the data associated with the data block are to be stored. The gating of information between the various registers and generators is governed by the sequencer.
  • the micro-controller sends information to the header registers comprising the IPORT so that a header can be generated for the data block.
  • the micro-controller also sets bits in the IPORT control register to enable the IPORT sequencer to gate information from the IPORT header registers to the IPORT address generators.
  • the IPORT address generators develop values correponding to the addresses in the data buffer at which the data block and the block header are to be stored.
  • the IPORT sequencer then gates the block header to the address in the data buffer at which the block header is to be stored and applies the block data on the buffer data bus to the address in the data buffer at which the data is to be stored.
  • the micro ⁇ controller reschedules the transmission of the block so that the block is also written at an alternate physical location on the tape which is not the orginally- intended location.
  • the alternate physical location is chosen such that, if a tape defect occurred at the originally-intended physical location, it will not be likely that the same tape defect will extend to the alternate physical location. If, for example, a number M of blocks is written across the width of a tape, the number N of blocks written between the originally-intended physical location of the block and the alternate location is chosen such that N differs from M and is not related by an integer.
  • FIG. 1 is a schematic view of a data buffer management system according to an embodiment of the invention
  • FIG. 3 is a schematic view of an interface port (IPORT) included in the system of the embodiment of FIG. 1;
  • IPORT interface port
  • FIG. 4 is a schematic view of a device port (DPORT) included in the system of the embodiment of FIG. 1;
  • DPORT device port
  • FIG. 6A is a schematic view showing steps executed in a first stage of a read mode according to the invention.
  • FIG. 6B is a schematic view showing steps executed in a second stage of a read mode according to the invention
  • FIG. 7 is a schematic view of steps executed to determine whether blocks of data obtained from a storage device used with the embodiment of FIG. 1 are valid blocks;
  • FIG. 8A is a schematic view of a READOUT queue which exists in a memory associated with the micro-computer of FIG. 2;
  • FIG. 8B is a schematic view of a BAD BLOCK queue stored in the memory of the micro-controller of FIG. 2
  • FIG. 8C is a schematic view of addresses included in a buffer memory connected to the management system of FIG. 1 and showing memory pointers when the invention is in a write mode;
  • FIG. 9 is a schematic view of addresses included in the buffer memory connected to the management system of FIG. 1 and showing memory pointers when the invention is in a read mode;
  • FIG. 10 is a schematic view illustrating a block of data on a magnetic tape
  • FIG. 10B is a table showing the format of a block header according to an embodiment of the invention
  • FIG. 11 is a schematic view of blocks of data recorded on magnetic tape according to an embodiment of the invention.
  • FIG. 12 is a schematic view depicting various memory locations of a random access memory included in the micro-controller of FIG. 2.
  • Fig. 1 shows a data buffer management system
  • a micro-controller 12 comprising a micro-controller 12; a host interface port (IPORT) 16; a device port (DPORT) 18; and, a dynamic random access memory (DRAM) controller buffer interface 20.
  • a first device such as host computer system 21, is connected to the IPORT 16.
  • a data buffer 24 is connected to the buffer interface 20.
  • the data buffer 24 comprises a bank of DRAM chips configured as 256K by 9 bits wide.
  • a second device 26, such as a helical scan tape drive, has a channel connected to the DPORT 18.
  • a communication channel, disc drive, or other type device may be substituted for the tape drive as the second device 26.
  • the first (host) device 21, the second device 26, and the data buffer management system 10 are each connected to a bi-directional buffer data bus 28 and a buffer address bus 30.
  • Priority access lines 31 and 32 connect the buffer interface 20 with the IPORT 16 and DPORT 18, respectively.
  • the SCSI interface 22 is a conventional device such as a type WD33C93 SCSI chip manufactured by Western Digital, for example.
  • the DRAM chips used in one embodiment are type 41256 RAM chips such as those manufactured by Texas Instruments. Such chips are fabricated as 256 K bytes by 1 bit wide and may be linked together to produce a 9 bit wide data bus. In the illustrated embodiment, 9 bits are used: 8 bits contain data while the 9th bit is used for parity checking.
  • the data buffer or buffer memory 24 (illustrated in Figs. 8C and 9) comprises 8K addresses whereat block header information is storable and 248K wherein block information is storable.
  • the 248K are partitioned into 248 blocks, labelled blockO to block247 (Fig. 8C) .
  • Each block contains 1024 bytes (IK) of memory.
  • IPORT 16 In the illustrated embodiment, IPORT 16,
  • DPORT 18 and buffer interface 20 are fabricated as a custom LSI chip. If desired, these functions can also be duplicated using discrete components. It should also be understood that alternative interface modules can be substituted for the SCSI interface 22 associated with the host 21 and that electrical hardware circuits can be substituted for the micro-controller 12 without affecting the scope of the invention.
  • Fig. 10A illustrates that a block of data is conceptualized as having a header 33 and informational data 34.
  • the header 33 comprises 16 bytes; the informational data 34 comprises 1024 bytes.
  • the format of the header 33 for the illustrated embodiment is understood with reference to Fig. 10B.
  • Control interface 45 includes an external data bus 46 (8 bits); an external address bus 48 (8 bits); and, a plurality of other lines generally depicted by reference numeral 50. Examples of lines included in the group 50 are an address latch enable signal line; a chip select signal line; a write signal line; a read signal line; a reset signal line; interrupt signal lines; and interrupt acknowledge signal lines. These group 50 lines are connected to specific pins on the CPU 36. An address decoder built into the CPU 36 directs signals to registers of the IPORT 16 and DPORT 18.
  • the IPORT 16 (Fig * 3) comprises a plurality of header registers, including a "A" PAGE ID register 60; a "B” PAGE ID register 62; an "A" BLOCK ID register 64; a “B” BLOCK ID register 66; two DATA BYTE COUNT registers HI 68 and LO 70; and, three LOGICAL BLOCK ID registers HI, MD, LO, labelled 72,74,76, respectively.
  • the IPORT 16 also comprises an IPORT sequencer 77; an IPORT data address generator 78; an IPORT header address generator 80; and, an IPORT control register 84.
  • the registers included in IPORT 16 are connected to a plurality of busses, to be discussed below.
  • the PAGE ID registers 60,62 are each 1 byte long and are used to inform the management system 10 of the size of the buffer memory 24. Valid values for this register are 0,1,2 or 3. With 256K memory, the register has a value of 0. If larger memory (i.e., 1 megabyte) is used for the buffer 24, the value in this register is adjusted to reflect which bank of 256K memory is being accessed. The correct memory page address is loaded by the micro-controller 12 into "A" PAGE ID register 60 and then transferred into "B" PAGE ID register 62 so as to increase the speed of the data buffer management system 10.
  • the BLOCK ID registers 64,66 are each 1 byte long and are used to construct the address of a block of data in the buffer memory 24. This value is written to the tape device 26 and tells the device 26 where in the buffer memory 24 to place data on a subsequent read operation of the device to the buffer.
  • the "A" BLOCK ID register 64 is loaded by the micro-controller 12 and then transferred into "B" BLOCK ID register "B” 66 so as to increase the speed of the data buffer management system 10.
  • the DATA BYTE COUNT registers 68,70 total 10 bits. These registers inform the micro-controller 12 on a subsequent read operation of the device to the buffer how much data is in each 1024 memory block that is written to the device 26. If a data block is full, these registers contain the value 1024. If, for example, only 500 bytes of data are in a data block, the data byte count register 68,70 contains the value 500.
  • the LOGICAL BLOCK ID registers 72,74,76 total 24 bits and are used for logical operations of the buffer memory 24. For example, if the host 21 transfers data to the device 26 in 16K bytes per block segments, whereas the buffer memory 24 is arranged as IK blocks, the actual number of blocks per transfer is sixteen.
  • the LOGICAL BLOCK ID registers 72, 74, 76 assign a unique number to this group of sixteen IK blocks to identify them as belonging to one 16K block of data received from the host 21. The next group of sixteen IK blocks received from the host 21 are then assigned another unique identifying LOGICAL BLOCK ID.
  • the IPORT header address generator 80 and the IPORT data address generator 78 generate buffer addresses for each data block, the blocks being labelled from blockO to block 278.
  • the data address generator 78 generates a 20-bit value by concatenating the "B" BLOCK ID register 66 (in the most significant position) and the 10-bit value in the DATA BYTE COUNT registers 68,70.
  • the IPORT header address generator 80 generates a 20-bit value by concatenating of a string of five "l"'s (in bits 13 to 17), the value in the "B" BLOCK ID register 66, and a "0" (as the fourth bit).
  • Bits 18 and 19 of each generator selects which page of memory to use if more than 256K of memory is used for the buffer 24.
  • the IPORT control register 84 contains 8 bits which are used by the IPORT sequencer 77 to control the operation of the IPORT 16. The bits in the control register 84 are set by the CPU 36.
  • bit seven of control register 84 indicates that the system 10 is in read mode; otherwise bit seven indicates a write mode.
  • TRUE bit six enables the IPORT 16; when bit six is FALSE the IPORT 16 is disabled and reset.
  • Bit five enables IPORT 16 to execute the mode (either read or write) specified by bit seven.
  • Bit four is used to inform the CPU 36 of the status of the IPORT 16.
  • Bit three informs the CPU 36 whether the IPORT 16 is busy or not.
  • Bit two indicates when a parity error occurs. Bit one prevents data collision on the busses.
  • the IPORT sequencer 77 also receives indications from the host device 21 as to whether the host device 21 is requesting a block of data (in a read mode) or making a block of data available (in a write mode); apprises the micro-controller 12 of such indication (via an interrupt line included in the control interface 45); and, requests access to the buffer interface 20.
  • the IPORT sequencer 77 thus comprises a plurality of switches and gates for performing the gating and signalling operations in the sequence and manner described herein. In view of the nature and sequence of IPORT operations described herein, the man skilled in the art will well understand how to connect gating and switch elements to accomplish the herein- described functions performed by the IPORT sequencer 77.
  • the control interface 45 from the micro ⁇ controller 12 is connected to the "A" PAGE ID register 60; "A" BLOCK ID register 64; DATA BYTE COUNT registers 68,70; LOGICAL BLOCK ID registers 72,74,76; and, the IPORT control register 84.
  • the output of the "A" PAGE ID register 60 is connected to the input of the "B" PAGE ID register 62.
  • the output of the "A" BLOCK ID REGISTER 64 is connected to the input of the "B" BLOCK ID register 66.
  • Bus 30 carries the IPORT-generated addresses to the buffer interface 20.
  • the DPORT 18 (Fig. 4) comprises a plurality of header registers, including two BLOCK TYPE ID registers 100,102; three PAGE ID registers 104,106,108; three BLOCK ID registers 110,112,114; two DATA BYTE COUNT registers 116,118; three LOGICAL BLOCK ID registers 120,122,124; and, six PHYSICAL BLOCK ID registers 126,128,130,132,134,136.
  • the DPORT 18 includes a DPORT sequencer 137; a DPORT control register 140; a DPORT data address generator 142; and, a DPORT header address generator 144.
  • the PAGE ID; BLOCK ID; DATA BYTE COUNT; LOGICAL BLOCK ID registers; and, CONTROL register are similar to correspondingly-denominated registers in the IPORT 16 and thus their description is not repeated.
  • the PHYSICAL BLOCK ID registers describe the physical block location of data in the second device 26.
  • the PHYSICAL BLOCK ID registers are loaded with a 24-bit value by the micro ⁇ controller 12, which value is later transferred as part of the header to the device 26.
  • these registers are loaded with a value received from the device 26 which may then be retrieved by the micro-controller 12.
  • the DPORT control register 140 is connected to the control interface 45 and by line 32 to the buffer interface 20.
  • the format and function of the DPORT control register 140 is analogous to that of the IPORT control register 84, it being understood that the DPORT control register 140 concerns the operation of DPORT elements rather than analogously-denominated IPORT elements.
  • a device read header bus 146 connects the second device 26 with DPORT registers 100,104,110,116,118,120,122, 124,126,128 and 130. Under control of the DPORT sequencer 137, the bus 146 serves to load these registers with information from the block header obtained from the device 26. The output ports of the registers are connected to the control interface 45.
  • the BLOCK ID register 110 and the PAGE ID register 104 are also connected to the DPORT data address generator 142 via line 147A and 147B, respectively.
  • PHYSICAL BLOCK ID registers 132,134,136 As with the IPORT 16, the output of the "A" PAGE ID register 106 is connected to the "B" PAGE ID register 108 and the output of the "A" BLOCK ID register 112 is connected to the "B" BLOCK ID register 108 for the purpose of facilitating the operation of the management system 10.
  • the output of registers 102,108,114,132,134 and 136 are connected to a device write header bus 148.
  • the device write header bus 148 is connected to the device 26 so that certain header information carried on bus 148 can be written as part of a block, header (Fig. 10) to a storage medium (such as a magnetic tape) handled by the second device 26.
  • the output of the "B" PAGE ID register 108 is also connected to the DPORT data address generator 142 and to the DPORT header address generator 144 via line 150.
  • the output of the "B" BLOCK ID register 114 is connected to the DPORT data address generator 142 and to the DPORT header address generator 144 via line 152.
  • the DPORT sequencer 137 is shown in Fig. 4 as being connected by a DPORT sequencer communication bus 155 to each of the DPORT header registers, to the DPORT control register 140, and to the DPORT address generators 142,144.
  • the DPORT sequencer 137 is also connected by a DPORT/DEVICE communication bus 137a to the second device 26 and by a DPORT/BUFFER communication bus 137b to the buffer interface 20.
  • the DRAM controller buffer interface 20 (Fig. 1) is capable of simultaneously interfacing in an asynchronous mode of operation with the IPORT 16 and DPORT 18.
  • the buffer interface 20 is responsible for several functions including the determination of the priority of processing simultaneous requests.
  • the buffer interface 20 determines which request is to be processed first and acts accordingly to allow one operation to precede the other.
  • the buffer interface 20 also performs a memory refresh operation DRAM chips comprising buffer 24 when memory accesses are not occurring with respect to the IPORT 16 or DPORT 18.
  • the buffer interface 20 is also responsible for turning on a write enable pin to the buffer memory 24, and for activating address strobes associated with the DRAM memory 24.
  • the buffer interface 20 is connected to the buffer address bus 30 and to the bi-directional buffer data bus 28.
  • the buffer address bus 30 connects the buffer interface 20 to the address generators 78,80 of the IPORT 16 and to the address generators 142,144 of the DPORT.
  • the buffer data bus 78 connects the buffer interface 20 to the IPORT 16, to device 26, and to the SCSI port 22 included in the host 21.
  • the buffer memory 24 is divided into 8K addresses whereat block header information is storable and 248K addresses wherein block informational data is storable.
  • the 248K addresses are logically partitioned into 248 segments of 1,024 (IK) bytes each, which segments have loaded therein the blocks labelled blockO through block 247.
  • the addresses of the buffer memory are managed by the IPORT address generator 78,80 and DPORT address generators 142,144.
  • a first mode also known as an output or write mode
  • a block of data is transmitted in a first stage from the first device 21 to a memory location in the data buffer 24, and thence in a second stage from the location in the buffer 24 to the second device 26.
  • a second mode also known as an input or read mode
  • a block of data is transmitted in a first stage from the second device 26 to a memory location in the data buffer 24, and thence in a second stage from that location in the data buffer 24 to the first device 21.
  • header data generated in the micro-controller 12 is transferred on control interface 45 to the IPORT header registers.
  • IPORT sequencer 77 data stored in various ones of the IPORT 16 header registers is gated to The IPORT address generators 78,80 for the generation of a buffer data address data and a buffer header address.
  • the IPORT sequencer 77 also supervises the construction of a block header by gating the information in the IPORT 16 header registers, in a predetermined sequence, to the buffer data bus 28 to the address generated by the IPORT header address generator 80.
  • Block informational data from the host device 21 is applied on the buffer data bus 28 to the address generated by the IPORT data address generator 78.
  • informational data and header information for each data block is stored in the buffer memory 24.
  • a block of data is transferred from physical addresses within the buffer memory 24 to the device 26 over the buffer read data bus 28.
  • the DPORT header address generator 144 generates the address in buffer memory 24 from whence the block header is extracted; the DPORT data address generator 142 generates the address in buffer memory 24 from whence the block informational data is extracted.
  • the block is written in an originally-intended sequence to the second device 26. If the block is determined to be a "bad" block, the block is rewritten in an alternate sequence.
  • N number of blocks must undergo write mode first stage processing before the second stage of the write mode commences.
  • N number of blocks must undergo the write mode first stage processing to substantially "prime" the management system 10.
  • N number of BLOCK IDs are entered into a circular READOUT queue 184 (maintained in RAM 38) at addresses specified by a revolving pointer RDQwr.
  • the second stage of the write mode can commence.
  • BLOCK ID values are extracted from locations in the READOUT queue 184 pointed to by a revolving pointer ROQrd.
  • block header information is transferred from the device 26 over the device read header bus 146 and stored in the header registers of the DPORT 18. The contents of these header registers are applied to the micro ⁇ controller 12 via the control interface 45.
  • the micro ⁇ controller 12 examines the block header information associated with each received block and determines whether the block is valid, e.g. determines that the block is not a duplicate block.
  • the micro-controller 12 also stores the block header information for valid blocks in an allocation table in RAM 38. Invalid blocks are not transmitted to the data buffer 24.
  • Block informational data for valid blocks is transferred directly from the device 26 to the buffer memory 24 and stored at physical addresses therein as specified by the DPORT Data Address Generator 142.
  • block informational data from the data buffer 24 is applied to the buffer data bus 28 for transmission to the first (host) device 21.
  • a block is transferred from the host 21 and stored temporarily in the buffer memory 24.
  • a block is read from the buffer memory 24 and transferred to the device 26. Steps associated with the write mode of the invention are shown in Figs. 5A and 5B.
  • N has the value 11.
  • the two stages of the write mode can occur concurrently for different blocks.
  • BLOCK IDs are numbered 0 through 247, corresponding to the 248 memory segments available in the data buffer 24.
  • the BLOCK ID is generated by the micro-controller 12.
  • the micro-controller 12 For each block of data, the micro-controller 12 generates data for the IPORT header registers and the IPORT control register 84 (step 204), including the BLOCK ID and PAGE ID data. This data is applied (at step 206) to the IPORT header registers and the IPORT control register 84 on the control interface 45.
  • the BLOCK ID data and PAGE ID data are applied to the "A" BLOCK ID and to the "A" PAGE ID registers 60 and 64, respectively.
  • the IPORT sequencer 77 thereafter takes over the supervision of IPORT functions. At step 208 the sequencer 77 directs that data in "A" registers 60 and 64 be gated into respective "B” registers 62 and 66.
  • the sequencer 77 gates data from the IPORT header registers 62 and 66 into the IPORT header address generator 80 and data from the IPORT header registers 62, 64, 68, and 70 into the IPORT data address generator 78.
  • the generators 80 and 78 generate values corresponding to the addresses in the data buffer 24 whereat the block data and the block header associated with the block are to be stored.
  • the sequencer 77 gates the header address generated by the IPORT header generator 80 to the buffer interface 20 via buffer address bus 30.
  • the sequencer 77 gates the contents of IPORT registers 68,70,72,74 and 76 to the data buffer controller buffer interface 20 via the buffer data bus 28.
  • the sequencer 77 gates the IPORT registers in a predetermined order as dictated by a pre-established header format such as that depicted in Fig. 10B.
  • the sequencer 77 gates the data address generated by the IPORT address generator 78 to the buffer interface 20 via the buffer address bus 30.
  • the block data from the first (host) device 21 is loaded into the buffer interface 20 via the buffer data bus 28.
  • the buffer interface 20 uses the header address generated by IPORT address generator 80 and the block data address generated by IPORT address generator 78 to write the block header and block data into the data memory 24 in the manner depicted by Fig. 8C.
  • block headers are stored in memory locations addressable in the last 8K of the memory 24, while the block data is stored in partitioned segments (i ⁇ each) in a lower 248K of memory 24.
  • the block data is written into the DRAM comprising the buffer memory 24 at the address pointed to by the pointer WRptr, which pointer WRptr is related to the address generated by the IPORT data address generator 78.
  • the IPORT 16 continues to accept blocks from the SCSI Module Interface 22, to associate Block IDs with each block, and to store the blocks and headers in the buffer memory 24 in sequence to the BLOCK ID (BLOCK IDs sequence from 0,1,2...246,247,0,1,2, ..., 246,247,...) until the buffer 24 is full.
  • BLOCK ID BLOCK IDs sequence from 0,1,2...246,247,0,1,2, ..., 246,247, etc.
  • a 'Buffer Full' condition exists when there are no unused Block IDs available, which occurs when there are no unused segments in the buffer memory 24.
  • the Buffer Full condition causes the SCSI interface 22 to suspend data input until sufficient buffer space is available.
  • the micro-controller 12 increments the pointer ROQrd associated with the READOUT queue 184 maintained in RAM 38 (step 232).
  • the pointer ROQrd is used to point to the BLOCK ID for the next block scheduled to be transmitted from the data memory 24 and the second device 26.
  • the value of ROQrd will be "1" to point to the first block acquired from the host 21.
  • the micro-controller 12 generates data for the DPORT header registers and the DPORT control register 140 (step 234), including the BLOCK ID and PAGE ID data. This data is applied (at step 236) on the control interface 45 to the DPORT header registers and the DPORT control register 140.
  • the BLOCK ID data and PAGE ID data are applied to the "A" BLOCK ID and to the "A" PAGE ID registers 106 and 112, respectively.
  • the sequencer 137 gates the header address generated by the DPORT header generator 144 to the buffer interface 20 via buffer address bus 30.
  • the buffer interface applies to the buffer data bus 28, and thus to second device 26, the partial block header obtained from a location corresponding to the address generated by the DPORT generator 144.
  • the sequencer 137 gates the remainder of the block header to the second device on the device write header bus 148.
  • the address in the buffer memory 24 from which the block was extracted can be written over by another block received from the first (host) device 21. This ultimately occurs at step 253 by incrementing the pointer ROQwr and entering the BLOCK 10 of the block most recently transmitted from the host 21 to the buffer interface 2D into the READOUT queue 184.
  • a block is not processed correctly, i.e., it is determined (at step 252) to be a bad block (for example, due to a recording or transmission error), the address in the data buffer 24 from which the block was extracted cannot yet be written over by another block received from the first device 21.
  • the BLOCK ID of the bad block is placed into a BAD BLOCK queue 186 if it has not already been so.
  • the pointer ROQwr is incremented and the BLOCK ID of the bad block is re-entered into the READOUT queue at the location now pointed to by ROQwr.
  • the BAD BLOCK queue 186 is located in RAM 38 of the micro-controller 12 (see FIG. 12). BLOCK IDs of bad blocks are only once entered into the BAD BLOCK queue 186, but can be repeatedly entered into the READOUT queue if necessary.
  • the bad blocks are not recalled or erased as in prior art devices, but are instead, later rewritten, a plurality of times if necessary, at alternate physical locations on the storage medium.
  • the rewritten blocks are identified with a Retry Count that is incremented each time the block is rescheduled in the READOUT queue until either the device 26 processes the block correctly or a maximum permissible number of retries is exceeded.
  • the device 26 is a helical-scan magnetic tape recorder wherein blocks are written in helical stripes as shown in Fig. 11.
  • rewritten blocks are scattered across a tape 170 to avoid tape defects which tend to lie in horizontal patterns in the direction of the tape travel.
  • the bad block should be rewritten N number of blocks away from its originally-intended physical location.
  • N has the value 11 or greater, and more preferably that N be exactly 11 so that the alternate location will be 11 blocks away from the originally-intended location of the block. This combination insures that rewritten bad blocks will be positioned at least three blocks over from the previous copy of the bad block, reducing susceptibility to common tape defects.
  • other tape formats other combinations of parameters are usable.
  • Block 5 is a bad block as indicated by shading in Fig. 11B.
  • block 5 must be retransmitted to the tape 170 for writing at an alternate physical location.
  • the BLOCK ID for block 5 is re-entered into the READOUT queue 184 and entered into BAD BLOCK queue 186 in the manner aforedescribed.
  • Block 6 to Block 15 are then processed onto original block locations 6 to 15.
  • the next original block location (location 16) is separated eleven blocks from the bad original block 5.
  • the contents of block 5 are retrieved from the buffer 24 and re-recorded on the tape 170 at physical position 16.
  • Physical position 16 is thus referred to as an alternate physical location of block 5. If block 5 is successfully retransmitted, it is removed from the BAD BLOCK queue 186. This process repeats for the entire data transfer operation. Whenever a bad block is detected, it is re-recorded at an alternative location which, in the illustrated embodiment, is eleven blocks away from its originally-intended bad block location. BLOCK IDs and Retry Counts may be entered into the BAD BLOCK queue 186 until it is full, which causes the micro-controller 12 to temporarily suspend the data flow output from the buffer memory 24 until the bad blocks are correctly processed by the device 26.
  • the BAD BLOCK queue 186 also controls which buffer segments may be written by the IPORT 16, since bad blocks cannot be removed from the buffer 24 or overwritten by new blocks until the bad blocks are correctly processed by the device.
  • the WRITE operation is complete when the READOUT queue 184 is empty and all bad blocks have been removed from the BAD BLOCK queue 186.
  • a completed WRITE operation is indicated to the device 26 by an • Out of data' signal, which terminates the transmission of a block to the device 26.
  • blocks of data are transferred from the device 26 to the host 21 in two stages.
  • a block of data is read from the device 26 and temporarily stored in the buffer memory 24.
  • a block of data is removed from the buffer memory 24 and transferred to the SCSI Module Interface 22 associated with the host 21.
  • the block is removed from the buffer memory 24, which vacates the addresses occupied by the block for receiving additional data from the device 26. Steps associated with the read mode are depicted in Figs. 6A and 6B.
  • blocks of data are streamed from the second device 26 into the buffer 24 in the order that the blocks are stored on the device 26.
  • blocks may not be stored in strict BLOCK ID sequence on the storage medium.
  • blocks stored on the helically-recorded tape 170 may be out of sequence as a result of interleaved bad data blocks, good data blocks, and rewritten blocks.
  • the blocks Prior to transmission to the first device 21 the blocks must be placed into a correct sequence regardless of the order in which they were read from the storage medium.
  • a "valid" block is a block of data obtained from the storage medium which is transmissable to the data buffer 24 and from thence to the first (host) device 21. Thus, neither "bad" blocks or duplicate blocks are considered to be valid blocks.
  • Valid data blocks are temporarily stored in the buffer memory 24 until processed by the IPORT 16. By providing temporary buffer storage and real-time processing of data blocks read from the device 26, the data blocks can be restored to the correct order without frequent interruptions of the read process.
  • the DPORT sequencer 137 receives a signal from the second device 26 that a block of data is available. If the DPORT 18 is ready to handle a new block from the second device, i.e. if the DPORT 18 is finished writing the previous block to the data buffer 24, the DPORT sequencer 137 informs the micro ⁇ controller 12 that a new block is to be processed (step 260).
  • step 262 As a data block arrives from the device 26, at step 262 (see Fig. 6A) its associated header is transmitted on the device read header bus 146 for storage in the appropriate DPORT 18 registers.
  • the DPORT sequencer 137 gates information into the header registers comprising the DPORT in a predetermined order in accordance with the pre- established format of the header (see FIG. 10B) .
  • the block header information is transmitted to the micro-controller 12.
  • step 268 the micro ⁇ controller applies data to the DPORT control register 140.
  • the DPORT sequencer 137 examines this register for instructions as to how the sequencer 137 is to govern the DPORT functions.
  • the DPORT sequencer 137 thereafter takes over the supervision of DPORT functions.
  • the sequencer 137 gates data from the DPORT header registers 110 and 104, into the DPORT data address generators 142 and 144.
  • the generator 142 generates values corresponding to the addresses in the data buffer 24 whereat the block data is to be stored.
  • the sequencer 137 gates the data address generated by the DPORT address generator 142 to the buffer interface 20 via the buffer address bus 30.
  • the buffer interface receives the block data information applied on the buffer data bus 28 and stores the same at the location corresponding to the value generated by the DPORT data address generator 142, which address corresponds to the pointer WRptr shown in Fig. 9.
  • the first device 21 requests a block of data, which request is received at step 302 by the IPORT sequencer 77.
  • IPORT sequencer 77 informs the micro ⁇ controller 12 that the host device 21 has requested further data from the buffer management system 10.
  • the micro-controller 12 obtains the next BLOCK ID for the next block.
  • the next BLOCK ID is obtained by transformching the allocation table 281 and selecting therefrom the next BLOCK ID corresponding to the next value in an increasing monotonic sequence.
  • the micro-controller 12 generates data for the IPORT header registers and the IPORT control register 84 (step 308), including the BLOCK ID and PAGE ID data.
  • the IPORT sequencer 77 thereafter takes over the supervision of IPORT functions.
  • the sequencer 77 directs that data in "A" registers 60 and 64 be gated into respective "B" registers 62 and 66.
  • the sequencer 77 gates data from the IPORT header registers 62,64,68, and 70 into the IPORT data address generator 78.
  • the generator 78 generates a value corresponding to the addresses in the data buffer 24 whereat the block data associated with the block is stored. This value corresponds to the pointer RDptr.
  • the sequencer 77 gates the data address generated by the IPORT address generator 78 to the buffer interface 20 via the buffer address bus 30.
  • block data from the buffer interface 20 is applied to the first device 21 via the buffer data bus 28.
  • the micro-controller 12 determines whether the block is valid, i.e. whether the block belongs to a current buffer BLOCK ID group. Valid blocks are stored, whereas invalid blocks are immediately discarded.
  • Fig. 7 represents a flow chart of the steps performed to determine whether blocks obtained from the device 26 are valid.
  • the micro-controller 12 first examines the buffer read address pointer RDptr and buffer write address pointer WRptr to produce a difference value DBID (Step 350).
  • the micro-controller 12 computes a physical distance DPID, the equation for which is discussed below.
  • the difference value DBID is compared to a constant Buffer threshold, BTHRESH. An equation for calculating BTHRESH is discussed below. This comparison at step 352 determines the relative "distance" between the current IPORT BLOCK ID read position and the BLOCK ID of the block in question.
  • the buffer 24 is full if the physical distance DPID is greater than or equal to a Maximum Buffer Block ID (MAXBUFID) .
  • MAXBUFID Maximum Buffer Block ID
  • the micro-controller 12 halts the device 26 read operation while the host 21 continues to remove data from the buffer 24 (Step 354). When sufficient space is available in the buffer 24, the read operation is resumed.
  • the micro-controller 12 determines whether the block has already been stored in the buffer 24 by examining the allocation table 281 maintained in RAM 38. If the block has already been stored, then it is a redundant copy and is discarded (Step 358). Otherwise the block is stored in the data buffer 24 (step 360).
  • the micro-controller 12 compares the value of BTHRESH with the physical distance DPID (the equation for which is given below). If this physical distance DPID is greater than or equal to BTHRESH, the block in question is a new block ahead of the current buffer read address pointer RDptr and Buffer Block ID Group. In this case, at Step 364 the micro-controller 12 examines the allocation table 281 in RAM 38 to determine whether the block has already been stored in the data buffer 24. If the block has been stored, it is discarded (step 358); otherwise it will be stored in the buffer 24 (step 360).
  • Step 362 If at Step 362 it is determined that the physical distance DPID is less than BTHRESH, then the block is behind the current buffer read address pointer RDptr. In this case the block in question is a redundant copy of a block within the current Buffer Block ID Group, and is discarded (Step 358).
  • the physical distance DPID must be adjusted by the block's Retry Count to reflect the PHYSICAL BLOCK ID of the original copy.
  • An equation for calculating the physical distance DPID is:
  • BTHRESH (Maximum BLOCK ID) - (Maximum Block Offset)
  • N ll
  • Maximum Retry Count 12
  • Maximum Block ID 248 (actual physical values range from 0 through 247).
  • a BTHRESH value of 128 is used.
  • a "Buffer Empty" condition exists when the micro-controller 12 requires the next BLOCK ID to schedule into the IPORT 16 registers and there are no segments in the buffer memory 24 containing data. This condition will cause 15 the SCSI interface 22 to suspend data output to the host 21 until a sufficient amount of data is available in the buffer memory 24.

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Abstract

Système de gestion (10) de tampons de données supervisant la transmission de blocs de données entre un premier dispositif (21), un tampon de données (24), et un second dispositif (26). Dans un mode d'écriture, des blocs sont transmis au second dispositif (26) dans une séquence de conception originale. Si le second dispositif (26) détermine qu'un bloc défectueux a été inscrit dans celui-ci, le système de gestion réécrit le bloc dans une séquence de remplacement. Dans un mode de lecture, le système de gestion (10) ignore les blocs défectueux et duplique les blocs obtenus à partir du second dispositif (26) afin de transmettre des blocs de données au premier dispositif (21) dans la bonne séquence.
EP19880905495 1987-07-02 1988-05-27 Method and apparatus for data buffer management Withdrawn EP0371034A4 (en)

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US6913287A 1987-07-02 1987-07-02
US69132 1987-07-02

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EP0371034A4 EP0371034A4 (en) 1993-02-24

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JP2864741B2 (ja) * 1990-12-19 1999-03-08 株式会社日立製作所 データインテグリティを保証する通信システム
EP0957484B1 (fr) 1998-05-12 2005-10-05 Hewlett-Packard Company, A Delaware Corporation Procédé de lecture et écriture simultanées dans un dispositif de stockage de données
JP2000285616A (ja) * 1999-03-30 2000-10-13 Matsushita Electric Ind Co Ltd 映像信号記録再生装置

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EP0371034A4 (en) 1993-02-24
WO1989000312A1 (fr) 1989-01-12

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