VIDEO MAPS GENERATOR
1. Presentation of the apparatus
The DC-VM-01 apparatus produces video maps suited for display on visualization units of the PPI and SCAN CONVERTED BRIGHT DISPLAY types normally supplied with independent video entry. One may associate the DC-VM-01 with a Video Distributor (VC-VD-01) thus allowing for the multiplication and the mixing of videos exiting the system and for their appropriate distribution to the RADAR indicators. The main features of the DC-VM-01 system are the following:
a) Technical characteristics; totally digital apparatus; this leads to the following advantages: 1 - reduction of maintenance costs;
2 - simplicity of installment;
3 - compactness of the system; 4 - low-tension use (TTL and CMOS circuits)
- no mechanical parts in motion ( scanners, discs, tapes, etc. ) - memorization capacity of data related to Video Maps CVM) for at least 12 months without feeding
- availability of cm internal simulator RADAR HEAD (Trigger generator, ACP, NP) for AUTOTESTING OFF-LINE; synchronization possibilities, E
through internal simulator, of a RADAR indicator.
b) Operational characteristics:
- The construction or modification of VM's may be operated simply and directly by the user. .
This means: 1 - shorter time needed for the operative availability of new VMs; 2 - the possibility to employ information exclusively reserved for the user. - the capacity to generate simultaneously four different Video Naps (VM) for the same radar.
- capacity, to represent approximately 260.000 video points (vp) with maximum memory extension.
- high quality presentation! especially for that which involves:
1 - stable and constant definition no matter what choice of scale factor, range or distance from RADAR origin.
2 - extreme accuracy in the correspondence between VM points and RADAR information both in distance and azimuth.
- ON LINE autodiagnosis on the correctness of data to be presented and on errors of formulation; alfanumeric signalling of various types malfunction.
2) General Description
The entry signals into the DC-VM are :
1 ) ACP (409G linear increments/antenna rotation )
2) NORTH PULSE
3) RADAR TRIGGER
The exit signals from the DC-VM-01 are:. 4 video independents (VM.1, VM2, VM3, VM4) .
The user may construct the VM's employing the "STRAIGHT LINE" and "CIRCUMFERENCE" equations memorized in the system. In order to do so, he will supply the processor with the distinctive parameters (without any positional or size limitation to the plane at issue) of the "SEGMENT ", "CIRCUMFERENCE ARC"' and "CIRCUMFERENCE" equations.
Thus willbe produced the basic elements with which to represent the VM to the most accurate detail, the only limitation residing in the maximum number of memorizable, p.v. The intersection points between the aforementioned functions and the SWEEPS RADAR, when computed by the system, will represent the memorized pv's and will then be displayed on the visualization unit. The overall architecture of the system (refer fig. 1) is as follows: the DC-VM-01 apparatus consists of 2 fundamental units which allow for the distinction between the phases construction and operative of VM's
use
1 - Video Map Programmer 2 - Video Map Generator
The Video Map Programmer consists of a functional/alfanumeric keyboard and a Display both employed by the user to introduce the DISTINCTIVE PARAMETERS OF THE SEGMENT, CIRCUMFERENCE ARC AND CIRCUMFERENCE equations which form the VM.
The Video Map Generator (see fig. 2) is, on the other hand, constituted by: 1 - Microprocessor Module CLZ-80S (CPU, EPROM, RAM, I/O) which:
- elaborates, the DISTINCTIVE PARAMETERS of the VM equations received by the VM Programmer, storing them in the Video Function memory (FV); - computes the pv's obtained as intersection between the FV's and every SWEEP RADAR, storing them in the p.v. memory (MEM);
- generates control signals for the LDCB, MBA, MEM modules;
- runs the LED command key situated in the front panel;
- runs the VM Programmer (Keyboard and Display);
- executes diagnostic on its internal and external memories (MEM, MBA).
2 - LDCB Module (DMA Logic and BUFFER CONTROL), which:
- runs video exit BUFFERS from MEM in synchronization with the TRIGGER RADAR and the current number of ACP's.
- allows, through 3 STATE METERS (A, B, N), all operations and logical sequences related to meters, summators, comparators, etc.
- signals malfunctions of the azimuth error, lack of TRIGGER and meter error types.
3 - MBA Module (Low Absorbancy Memory) containing the constituent parameters of the VM equations in correct order, data concerning
VM maximum range and accuracy chosen for the RADAR indicator, computed programmes recalled into the CPU central memory when the system calculates the pv's. 4 - MEM Module ( PV Memory) containing the computed pv's to be displayed. For this purpose, it may be written and read by the
CPU and read by the LDCB module so as to transfer the exiting VIDEO DATA. 5 - ISRC Module (INTERFACE RADAR SIGNALS AND CONTROLS), which:
- produces the ACP, NP TEST TRIGGER signals and computes various control signals for the MEM, MBA and LDCB received by the CLZ-80S module. - allows for the extension of the I/O lines to and from the CPU.
- adapts video signals exiting toward the RADAR indicator.
3. Presentation of the DC-VM-01 general block outline (see fig. 3)
CLZ-80S Module
Constitutes the heart of the system together with the ZSOB (4MHz) microprocessor.lt has a capacity of 64 RAM KBYTE and 8 EPROM KBYTE, 32 I/O Tines with 4. PIO doors. The signals featured on the frontal connectors are the following: PA 0 : 7 = I/O lines for the KEYBoard (through the ISRC) PB 0 : 5 = " " " " " ( " " " ) PB 0 : 7 = " " " " Key ( " " " ) PC 0 : 3 = for MEM Chip selection (through the ISRC)
PC.4 : 6 = for external memory type selection: MEM and MBA memories (RAM or EPROM) . (through the ISRC). PC 7 = for qualification and dequalification of LDCB chart and its reading into MEM (through ISRC) PD 0 : 6 = (through ISRC), subdivided into: - 0 : 1 for LED ERROR and REDY
- 2 for R/W qualification external memory to CLZ-80S - 3 : 5 for error reading from LDCB
- 6 for RESET of error indication in LDCB. BD 0 : 7 = bidirectional data lines for MEM and MBA
BAD 0 : 12 = for MEM and MBA directioning (both EPROM and RAM) BAD 11 : 12 = for ISRC generation of the following signals: CSMB 0 : 3 and CSEP 0 : 3;
(CSMB 0 : 3 for MBA-RAM Chip qualification) CSEP 0 : 3 fro EPROM Chip qualification) BAD 13 :15 = for RESET CPU generation in case of FETCH condition on memory areas destined for data. HM1 : BMREQ = CPU control signals.
PMM 0 = in combination, with other control signals, qualifies, for CPU, external memory to CLZ-80S (MEM, MBA) BRESET = RESET signal from ISRC to CLZ-80S. BRD = generates MEM R/W qualification signals BWR = MEM and MBA write qualification signal
Low Absorbancy Memory (MBA). Includes: - 4 Low Absorbancy RAM Chips with a capacity of 8 KBYTE - 4 EPROM Chips with a capacity of 16 KBYTE
- 3 Stopper Batteries and a recharge circuit for data retention. Within the RAM are stored.:
- the indicator parameters associated to the system (VM maximum range, Accuracy) - distinctive parameters of the equations constituting the 4 VM's
(maximum of 511 Equations)
Within the EPROM. are stored and memorized programmes transferred into the CPU central memory at the moment of computation aimed at pv production.
A data BUS and directional BUS, both with an 8 BIT capacity, togetherwith the control signals, allow communication with CLZ- 80S.
Data retention through Stopper Batteries allows for: - automatic restoration of pv's in case of a lack of network
- the employment of "n" different Video Maps with the. simple insertionof different MBA Modules in the DC-VM-01 Generator.
p.v. Memory (MEM). The system is provided with a maximum of 4 MEM modules, written and read by CPU and read by LDCB.
Each MEM contains: 16 RAM Chips for p.v. memorization with a capacity of 128 KBYTE and a multiplexer network for the selection of directioning operated by CPU or LDCB,
Interface Radar Signals and Controls (ISRC).
May be divided into two sections/:
- EXTENDED I/O: for I/O CPU line connection with other modules, decodification or generation of some CLZ-80S control signals for external memories.
- RADAR: for adaption of external RADAR signals, regeneration of VM 1 : 4 Videos, generation of TEST RADAR signals.
The signals present on the back connectors are the following: BAD 13 ÷ 15 BAD 11÷12 BRD
BMREQ BMM O BREBET
VM 1 ÷ 40 = video Signals in balanced line of the 4 VM's for the external indicator. VM 1 ÷ 4 = video signals in balanced line from LDCB.
ACP = signal in balanced line for LDCB NP = signal in balanced line for LDCB
TRIGGER = signal in balanced line for LDCB
PID 3 ÷ 5 = error states from LDCB for CPU
PID 6L = RESET of ERROR state
MCCT = qualifies LDCB chart (a result of PC 7 signal elaboration)
CK3 = Trigger and Test ACP generation Clock.
PIA ∅ ÷ 7 = continuation of PA 0 : 7 signals. PIB ∅ ÷5 = " " PB 0 : 5
PIB 6 ÷.7 PB6 : 7
MCB ∅÷ 3 = MEM selectors to CPU or to LDCB generated with PC7 signal.
PIC ∅ ÷3 = continuation of PC 0 : 3 signals. BANC∅ ÷ 3 = qualification MEM Bank n° when entered by CPU ABLWR ∅ ÷ 1 = Write qualification for banks 0 and 1
ABLWR 2÷ 3 = 2 and 3
ABLBUS = connects the 8 BIT BUS of one row to 8 Chips of the other row CSEP ∅ ÷ 3 = qualifies EPROM Chips (MBA)
CSMB ∅÷ 3 RAM (MBA)
(On front connectors receives all J6 and J7 front connector signals of CLZ-80S).
Keyboard-Display (ATD).
Resolvable, as a man-system interface, into:
- INPUT section : Keys
- OUTPUT section: 7 segment Display, LED.
Allows the operator to: - insert, read and erase Distinctive Parameters of Video Function on
MBA.
- insert Range and Accuracy Parameters. - visualize any error in the VM system.
DMA Logic. and Buffer Control (LDCB).
Executes MEM high-speed reading related to azimuthal position of SUEEP indicator, presenting exiting video impulses synchronized with the Trigger. For memory scan (reading) the chart includes:
- a 16.BIT data BUS
- a 17 BIT direction Meter
- an ENCODER for the selection of the 4 MEM's - a distance "METER" synchronized with the TRIGGER - a 12 BIT comparator
- three Meters of State
- an error revealing circuit for:
- azimut errors - lack of TRIGGER
- OVERFLOW direction Meter - State A error Meter
- State N error Meter
The signals present are the following: ADDR 00 : 16 = for directioning within MEM when LDCB control chart is
qualified DM 00 : 15 = for data from MEM when control chart is qualified ABLC 0 : 13 = for qualification of MEM banks upon control chart entrance.
VM 1 = video on exiting balanced line.
PID 3 : 5 = signal for error reading. PID6L = reset error indication signal MCCT = balanced line signal for LDCB qualification, NP = balanced line North signal. TRIG = balanced line radar trigger signal. ACP = balanced line Azimuth Change Pulse signal.
Level Adaptor Tops ACP, NP, TRIGGER signals to TTL level accepting 3V to 50V entry signals.
Front Panel includes:
Tri-positional key switch for the selection of the system's functioning modes:
OPERATIVE, KEYBOARD QUALIFICATION, CALCULATION;
STATE- SYSTEM LED: REDY, ERROR.
4. VIDEO POINT Memory Configuration (MEM modules) (64K - 256K 16 BIT words)
The Video Points Memory has been structured in accordance with a logic which facilitate its reading related to the current ACP.
The amount of memory, .employed by the user to construct his VM's is subdivided into 4096 blocks, thus obtaining a biderectional correspondence between the ACP and the memory segments. Each block is composed of' a Head Word, also called Word ofSynchronization (PS), and of a variable number of words each identifying a PV to be represented.
If for a given ACP, p.v. are not produced, the memory segment involved is reduced to the single Word of Synchronization (see fig. 4).
The significance of the BIT in the Word of .Synchronization is as follows:
DM 12 : 15 = 0 identify the PS DM 00 : 11 = n° of PV + 1 of the block
The significance of the BIT in the "Video Words" (PV)is the following:
DM 12 : 15 = VM 1 : 4, the BIT situated between 12 and 15 which are equal to "1" indicate to which VM belongs the PV under scrutiny.
DM 00 : 11 = n° of RBC (RANGE BIN CLOCK), expressing the distance from the TRIGGER of the PV one wishes to represent.
Note: An RBC = 1/32 NM or 1/16 NM or 1/8 NM, all values selectionable by the user as semioperative variables of the system.
5. DC-VM Software (brief outline).
The totality of all the procedure running the DC-VM System is partly a ermanent resident in EPROM (8 KBYTE) of the CLZ-80S and partly in
EPROM (16 KBYTE) of the MBA module.
The EPROM MBA content is transfered on to the RAM CLZ-803 upon execution of p.v. computation.
Software Activities
The fundamental operations undertaken by the software are:
- management of commands coming from the front panel Key switch; the command positions of the control key are: OPERATIVE, KEYBOARD QUALIFICATION, CALCULATION.
- management of front panel LED READY and ERROR signals;
- construction of VM's subdivided into following steps: a) charging within the MBA module of the equations which make up the VM's coming from the KEYBOARD-DISPLAY PROGRAMMER;
b) computation of p.v. and their ordering; c) writting of Synchronism PV's into MEM - qualification of VM visualization.
- diagnostics execution on:
1) RAM resident in CLZ-80S with read/write controls for all locations upon commencement of operations and on two location simultaneously, in ciclical-sequential manner; during operative functionement. 2) MEM with read/write controls if not containing data, or with CK-SUM controls at every data transfer from RAM to CLZ-8QS memory and viceversa.
- configuration control upon commencement of operations (that is, number of present MEM- modules). - control and writting on KEYBOARD-DISPLAY of reached OVERFLOW ofVideo Functions and available memory. - writting on Display-keyboard 'of error messages; these are:
- CPU Err - MBA Err
- EPR Err - CAR 4, 5, 6, 7 (MEMO, 1, 2, 3) Err. - MEM FULL.