EP0348895B1 - Halbleiterspeichervorrichtung, die mit einer Niederrausch-Spannungsversorgung ausgestattet ist - Google Patents

Halbleiterspeichervorrichtung, die mit einer Niederrausch-Spannungsversorgung ausgestattet ist Download PDF

Info

Publication number
EP0348895B1
EP0348895B1 EP19890111678 EP89111678A EP0348895B1 EP 0348895 B1 EP0348895 B1 EP 0348895B1 EP 19890111678 EP19890111678 EP 19890111678 EP 89111678 A EP89111678 A EP 89111678A EP 0348895 B1 EP0348895 B1 EP 0348895B1
Authority
EP
European Patent Office
Prior art keywords
memory cell
wiring
column
voltage
selection circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP19890111678
Other languages
English (en)
French (fr)
Other versions
EP0348895A2 (de
EP0348895A3 (en
Inventor
Hiroyuki Kobatake
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP15873388A external-priority patent/JPH0738275B2/ja
Priority claimed from JP15874188A external-priority patent/JP2822391B2/ja
Application filed by NEC Corp filed Critical NEC Corp
Publication of EP0348895A2 publication Critical patent/EP0348895A2/de
Publication of EP0348895A3 publication Critical patent/EP0348895A3/en
Application granted granted Critical
Publication of EP0348895B1 publication Critical patent/EP0348895B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
    • G11C17/123—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops

Definitions

  • the present invention relates to a semiconductor memory device and, more particularly to a semiconductor read-only memory (ROM) fabricated on a semiconductor substrate.
  • ROM read-only memory
  • a semiconductor memory device such as a ROM is constructed with a memory cell array of memory cells arranged in a matrix form of rows and columns, and peripheral circuit blocks such as a row selection circuit block for operatively selecting one of the rows of the memory cell array, a column selection circuit block for selecting the columns of the memory cell array, a sense amplifier circuit block for amplifying a signal or signals read out from the memory cell array and an output buffer section for outputting a read-out signal.
  • Each of the circuit blocks are supplied with a power voltage (Vcc) and a reference voltage (Vss) such as a ground voltage (GND) by a power voltage wiring and a reference voltage wiring connected thereto, respectively.
  • the power voltage wiring and the reference voltage wiring are connected to external terminals through bonding pads and bonding wires, in a known way. Therefore, predetermined values of stray impedances are present between the bonding pads and the sources of the power voltage and the reference voltage. This means that potentials at the power voltage wiring and the reference voltage wiring are affected by current amount flowing into the circuit blocks. While, some of the circuit blocks such as the output buffer block or the row selection circuit block causes a large peak current flowing therethrough when the state thereof is changed. Such peak current flowing into the certain circuit block causes a potential change at the power voltage wiring or the reference voltage wiring and therefore the value of the power voltage or the reference voltage actually supplied to the circuit blocks is affected, resulting in erroneous operation of the circuit block or blocks.
  • EP-A-0081368 describes a semiconductor memory device according to the preamble of claim 1 wherein ground supply lines connected to capacitors of memory cells are independent and physically separated of other ground supply lines connected to peripheral circuits.
  • the potential change in the first voltage at the one peripheral circuit due to the peak current thereof is hardly transmitted to the first voltage terminal because of the impedance element. Therefore, the other peripheral circuit is not affected by the potential change in the first voltage caused by the other peripheral circuit so that the other peripheral circuit can operate stably.
  • a conventional semiconductor memory device comprises a memory cell array 1 formed by arranging a plurality of memory cells M00 - M33 in both column and row directions; a plurality of column lines D0 - D3 for connecting the memory cells M00 - M33 in the column direction; a plurality of row (word) lines W0 - W3 for connecting the memory cells M00 - M33 in the row direction; a column selection circuit for receiving address signal and selecting the column lines D0 - D3; a row selection circuit 3 for receiving row address signals and selecting one of the row lines W0 - W3; a sense amplifier 4 for reading out data stored in the selected memory cell in the memory cell array 1; and an output buffer 5 for driving a load connected to an output terminal OUT.
  • Ground wirings GC of the memory cells M00 - M33, a ground wiring GY of the column selection circuit 2, a ground wiring GX of the row selection circuit 3, a ground wiring GS of the sense amplifier 4 and a ground wiring GO of the buffer 5 are connected to a ground terminal TGND formed as a bonding pad, and a power source wiring VY of the column selection circuit 2, a power source wiring VX of the row selection circuit 3, a power source wiring VS of the sense amplifier 4 and a power source wiring VO of the buffer 5 are connected to a power source terminal TVCC formed as a bonding pad.
  • the sense amplifier 4 is comprised of an N-channel MOSFET N11 whose drain and gate are connected to the sense amplifier output SOUT and to the output of an inverter IN1, respectively.
  • a load resistor RL is connected between the power source wiring VS of the sense amplifier and its output SOUT and if the input of the inverter IN1 and the power source and the ground are connected tothe sense amplifier input SIN, to the power source wiring VS of the sense amplifier and to the ground wiring GS of the sense amplifier, respectively.
  • the sense amplifier input SIN and the selected column line DS are biased to a logical threshold voltage Vth of the inverter INV 1 as the operating voltage of the sense amplifier and the output of the inverter IN1 is below Vth + VTN (where VTN is a logical threshold voltage of the N-channel MOSFET) so that the N-channel MOSFET 11 is turned OFF, too, and the sense amplifier output SOUT is pulled up by the load resistor RL to the potential of the power source wiring VS of the sense amplifier, thereby outputting a high level.
  • the ground wiring GS and power source wiring VS of the sense amplifier 4 and the ground wiring GO and power source wiring VO of the buffer 5 are commonly connected to the ground terminal TGND and to the power source terminal TVCC, respectively, as shown in Fig. 1. Therefore, if a heavy load is connected to OUT and driven by the buffer 5, a large current flows through the ground wiring GO or the power source wiring VO and thus noise is applied (for the periods ⁇ t1 and ⁇ t2) to the ground terminal TGND and the power source terminal TVCC as shown in Fig.
  • the logical threshold voltage Vth of the inverter IN1 drops as shown in Fig. 3B and the output of the inverter IN1 drops, too. Accordingly, when the selected memory cell MS is conductive, the N-channel MOSFET N11, which should be ON, is turned OFF and the high level as the erroneous output is outputted from the sense amplifier output SOUT for the period t2.
  • the column lines under the non-selection state enter erroneously the selection state if the rise of the potential of the ground terminal TGND exceeds the threshold voltage of the N-channel MOSFET forming the column selection circuit 2. Since the ground wiring GX of the row selection circuit 3 is directly connected to the ground terminal TGND, the memory cells under the non-selection state enter erroneously the selection stage because the potential of the non-selected word lines reaches substantially the same potential as the potential of the ground terminal TGND if the rises of the potential of the ground terminal TGND is above the threshold voltage of the memory cells.
  • This memory device is the so-called series-connection type read-only memory.
  • the series-connection type ROM comprises memory cell blocks MCB each including a series circuit of four memory cells MCi0 - MCi3 constituted by N-channel MOSFETs as shown in Fig. 6A, for example, and an N-channel block select MOSFET MSi; a memory cell array 1 formed by arranging a plurality of memory cell blocks MCB in row and column directions; an column selection circuit 2, connected to a plurality of column lines D0 - D3 for selecting the memory cell blocks in the column direction, a plurality of row lines WO0 - WO33 for connecting the memory cells MCi0 - MCi3 forming the memory cell block MCB in the row direction, a column decoder 2-1 for inputting address signals AY0 - AY1 and a column selector 2-2 having N-channel MOSFETS YS0 - YS3 driven by the outputs YD0 - YD3 of the decoder 2-1, for selecting the column lines D0
  • each NOR gate 11 forming the decoder 2-1 and the memory cell block selection circuit 3-2 includes P-channel MOSFETs P01, P02 and N-channel MOSFETs N01, N02 as shown in Fig. 15 and is interposed between a power source terminal Vcc and a ground terminal Vss.
  • Each NAND gate 12 in the row selection circuit 3-1 in Fig. 5 includes P-channel MOSFETs P11, P12 and N-channel MOSFETs N11, N12, as shown in Fig. 16.
  • the operation of this memory will be described briefly. If, for example, the address signals AY0 and AY1 are at the high level, the output YD0 of the decoder 2-1 is at the high level with the outputs YD1 - YD3 being at the low level, the N-channel MOSFETs YS0 forming the selector 2-2 is ON with the transistors YS1 - YS3 being OFF and the column line D0 is selected.
  • the output BS0 of the memory cell block selection circuit is at the high level with the outputs BS1 - BS3 being at the low level and the selection MOSFETs forming the memory cell block driven by the output BS0 of the selected memory cell block selection circuit are turned ON. Accordingly, they are connected to the selected column line D0 and the memory cell block where the selection MOSFET driven by the selected memory cell block circuit exists is selected.
  • the row lines W00, W10, W20 and W30 are at the low level and are selected while the row lines W01 - W03, W11 - W13, W21 - W23 and W31 - W33 are at the high level and are not selected, and the memory cell which exists inside the selected memory cell block and is moreover driven by the selected row line is under the selection state.
  • the selected memory cell is an N-channel depletion MOSFET, it is ON even at a low gate potential level. Accordingly, the selected column line D0 and the ground terminal Vss are connected electrically to each other through the selection MOSFET.
  • the selected memory cell is an N-channel enhancement MOSFET, on the other hand, it is turned OFF because the gate potential is at the low level so that the selected column line D0 and the ground terminals Vss are electrically cut off.
  • the sense amplifier 4 detects whether or not the selected column line D0 and the ground terminal Vss are electrically connected, and reads out the data stored in the memory cell.
  • the selected row line Wi0 is connected to the ground terminal Vss through the N-channel MOSFETs NXO0 and NXO forming the row selection circuit and the non-selected row lines Wi1, Wi2 and Wi3 are connected to the power source terminal Vcc through the P-channel MOSFETs PX1, PX2 and PX3, as shown in Fig. 6A.
  • an equivalent circuit such as shown in Fig.
  • 6B can be obtained by replacing the N-channel MOSFETs NXO0 and NXO by resistors RNXO0 an RNXO, the P-channel MOSFETs PX1, PX2 and PX3 by resistors RPX1, RPX2 and RPX3, expressing the gate capacitances of the non-selected memory cells MCi1, MCi2 and MCi3 to the gate of which the power source voltage is applied by Ci1, Ci2 and Ci3 and expressing the ON resistances by RMCi1, RMCi2 and RMCi3.
  • the gate capacitance and ON resistance of the selected memory cell MCi0 are not shown in Fig. 6B.
  • the selected memory cell MCi0 is of the N-channel enhancement MOSFET, it is turned OFF because the gate is at the ground potential. If the selected memory cell MCi0 is of the N-channel depletion MOSFET, it is turned ON and the ON resistance is connected to the ground terminal Vss through the gate capacitance and the resistors RNXO0 and RNXO. However, the operation in this case is substantially the same as that of the N-channel enhancement MOSFET, the explanation of the N-channel depletion MOSFET as the selected memory cell MCi0 will be omitted.
  • an equivalent circuit shown in Fig. 6C can be obtained by connecting parallel the resistors RPX1, RPX2 and RPX3 of Fig. 6B and replacing them by a resistor RPX, connecting the gate capacitances Ci1, Ci2 and Ci3 and replacing them by a capacitance CC and connecting in series the ON resistances RMCi1, RMCi2 and RMCi3 and replacing them by a resistor RMC.
  • RPX 1.0 ⁇
  • CC 10,000 pF
  • RMC 0.1 ⁇ , for example.
  • parasitic impedances ZVCC and ZGND exist between the power source and the power source terminal Vcc and between the ground power source and the ground terminal Vss and they are, for example,
  • 10 ⁇ and
  • 10 ⁇ , and
  • the parasitic impedances ZVCC and ZGND existing between the power source v and the power source terminal VCC and between the power source v and the ground terminal VSS are compared, the power source terminal VCC and the ground terminal VSS are coupled by an impedance as low as 1.1 ⁇ .
  • VNGND 1.0 V x
  • 0.9 V
  • the noise at the power source terminal VCC is transmitted substantially completely to the ground terminal VSS and the ground of the sense amplifier or the like, too, is connected to the ground terminal VSS. Accordingly, the sense amplifier or the like operates erroneously due to the noise transmitted to the ground terminal VSS.
  • VNVCC 1.0 V x
  • 0.9 V Therefore, the noise at the ground terminal VSS, too, is transmitted substantially completely to the power source terminal VCC, and since the power source of the sense amplifier or the like is connected to this power source terminal VCC, the sense amplifier or the like often operates erroneously due to the noise transmitted to the power source terminal VCC.
  • FIG. 7 With reference to Figs. 7 and 8, the memory device according to a first embodiment of the present invention will be explained. This embodiment relates the case where the conventional memory device of Fig. 1 is improved according to the present invention.
  • the memory device comprises a memory cell array 1 formed by arranging a plurality of memory cells M00 - M33 in both column and row directions; a plurality of column lines D0 - D3 for connecting the memory cells M00 - M33 in the column direction; a plurality of row lines W0 - W3 for connecting the memory cells M00 - M33 in the row direction; a column selection circuit for receiving column address signals and selecting the column lines D0 - D3; a row selection circuit 3 for receiving row address signals to select one of the row lines W0 - W3; a sense amplifier 5 for reading out data stored in the selected memory cell in the memory array 1; and an output buffer 5 for driving a load.
  • a memory cell array 1 formed by arranging a plurality of memory cells M00 - M33 in both column and row directions; a plurality of column lines D0 - D3 for connecting the memory cells M00 - M33 in the column direction; a plurality of row lines W0 - W3 for connecting the memory cells M00 -
  • the semiconductor memory device of the present embodiment is characterized in that the ground wirings GC of the memory cells M00 - M33 forming the memory cell array 1 are connected to the ground wiring GS of the sense amplifier and then to the ground terminal TGND formed as a bonding pad on the semiconductor substrate through a first resistance element RGSC and the power source wiring VS of the sense amplifier 4 is connected to the power source terminal TVCC formed in the form of a bonding pad through a third resistance element RVS.
  • the ground wirings GY, GX and GO of the column selection circuit 2, the row selection circuit 3 and the buffer 5 are directly connected to the ground terminal TGND and to the powder source terminal TVCC.
  • the ground terminal TGND is connected to the ground voltage source through a parasitic impedance ZGND and the power source terminal TVCC is connected to the power source VCC through the parasitic impedance ZVCC.
  • CGSC contains the junction capacitance between MOSFET forming the sense amplifier and the P-type substrate and the parasitic capacitance between the wirings and the P-type substrate.
  • the parasitic capacitance CVS exists also between the power source wiring VS of the sense amplifier 4 and the P-type substrate.
  • the buffer output OUT changes from the low level to the high level in the period ⁇ t2 and a large current flows through the power source wiring VO of the buffer 5, the noise is carried to the power source terminal TVSS because a parasitic impedance ZVCC exists between the power source terminal TVCC and the power source VCC, as shown in Fig. 8.
  • the power source wiring VS of the sense amplifier 4 is connected to the power source terminal through a third resistance element RVS and moreover, a capacitance CVS exists between the power source wiring VS of the sense amplifier 4 and the P-type substrate. Accordingly, the noise carried to the power source terminal TVCC is not transmitted to the power source wiring VS of the sense amplifier 4 so that the potential of the power source wiring VS of the sense amplifier 4 does not change and the sense amplifier 4 does not either operate erroneously.
  • Fig. 9 is a circuit diagram showing the second embodiment of the present invention.
  • the ground wiring GY of the column selection circuit 2 and the ground wiring GX of the row selection circuit 3 are connected and they are then connected to the ground terminal TGND through a second resistance element RGXY.
  • a parasitic capacitance CGXY exists between the junction of the ground wiring GY of the column selection circuit 2 with the ground wiring GX of the row selection circuit 3 and the P-type substrate. Since the rest of portions are the same as those in the first embodiment shown in Fig. 7, like reference numerals are put to them and their explanation will be hereby omitted.
  • the second embodiment provides the following effects. Namely, since the second resistance element RGXY and the parasitic capacitance CGXY exist, the noise applied to the power source terminal TVCC is not transmitted to the ground wiring GY of the column selection circuit 2 and to the ground wiring GX of the row selection circuit 3 so that the potential of the ground wiring GY of the column selection circuit 2 and the potential of the ground wiring GX of the row selection circuit 3 do not change and the erroneous operation in which the non-selected column lines and memory cells are brought into the selection state does not occur.
  • Fig. 10 is a circuit diagram showing the third embodiment of the present invention.
  • each memory cell R00 - R33 is a static memory cell having P-channel MOSFETs P1, P2 and N-channel MOSFETs N1, N2, N3, N4 and includes the power source wiring VC in addition to the ground wirings GS, and these memory cells R00 - R33 together constitute the memory cell array 1.
  • the ground wirings GC of these memory cells R00 - R33 are connected to the ground wiring GS of the sense amplifier 4 and are then connected to the ground terminal TGND through an N-channel type first MOSFET M1 whose gate receives the power source VCC.
  • the power source wirings VC of the memory cells R00 - R33 and the power source wiring VS of the sense amplifier 4 are connected and are then connected to the power source terminal TVCC through a P-channel type third MOSFET M3 whose gate is connected to the ground. Since the power source VCC is applied to the gate of the first MOSFET M1 and this transistor M1 is ON, it operates as a resistor and is equivalent to the first resistance element RGSC of the first embodiment. Accordingly, the similar effect to that of the first embodiment can be obtained obviously and its explanation will be hereby omitted.
  • the gate of the third MOSFET M3 Since the gate of the third MOSFET M3 is connected to the ground and this transistor M3 is ON, it operates as a resistor and furthermore, since the power source wirings VC of the memory cells R00 - R33 are connected to the sources and N-wells of the P-channel MOSFETs P1, P2 constituting the memory cells R00 - R33 (as shown in Fig. 12), the junction capacitance between the N-well and the P-type substrate exists between the power source wirings VC of the memory cells R00 - R33 and the P-type substrate.
  • the power source wirings VC of the memory cells R00 - R33 are connected to the power source wiring VS of the sense amplifier 4. Accordingly, the capacitance CVSC is greater than the capacitance CVS existing between the power source wiring VS and the P-type substrate in the first embodiment and transmission of the noise becomes more difficult.
  • This embodiment relates to the case where the present invention is applied to the memory device of Fig. 5.
  • the memory device of this embodiment comprises a memory cell array 1 formed by arranging a plurality of memory cell blocks MCB both row and column directions each of the memory cell blocks MCB having a series circuit of four memory cells MCi0 - MCi3 consisting of N-channel MOSFETs and an N-channel selection MOSFET MSi for selecting them, as shown in Fig.
  • a column selection circuit 2 selecting one of a plurality of column lines D0 - D3 for connecting the memory cell blocks MCB in the column direction, a plurality of row lines W00 - W33 for connecting the memory cells MCi0 - MCi3 constituting the memory cell blocks MCB in the row direction, a column decoder 2-1 for receiving column address signals AY0 - AY1 and a column selector 2-2 having N-channel MOSFETs YS0 - YS3 driven by the outputs YD0 - YD3 of the column decoder 2-1, for selecting the column lines D0 - D3; a row selection circuit 3-1 receiving the row address signals AX0 - AX1 and selecting the row lines W00 - W33; a memory cell block selection circuit 3-2 receiving the address signals AB0 - AB1 to drive the selection MOSFET MSi and selecting the memory cell blocks 1; and a sense amplifier 4 for reading out data stored in the selected memory cell in the memory cell array 1.
  • NAND gates 12 forming the row selection circuit 3-1 are connected to the power source terminal VCC through the resistance element RX.
  • the structure of NOR gates 11 forming the column decoder 2-1 and the memory cell block selection circuit 3-2 is shown in Fig. 15 and the structure of the NAND gates 12 forming the row selection circuit 3-1 is shown in Fig. 16.
  • the NAND gates 12 forming the row selection circuit 3-1 are connected to the power source terminal VCC through the resistance element RX. Therefore, an equivalent circuit which is equivalent to the P-channel MOSFETs forming the power source terminal VCC - the resistor element RX - the row selection circuit 3-1 and which consists of the resistor RPX - memory cell gate capacitance CC - memory cell ON resistance RMC - ground terminal VSS is shown in Fig. 18. Furthermore, parasitic impedances ZVCC and ZGND exist between the power source and the power source terminal VCC and between the ground source and the ground terminal VSS.
  • VNGND 1.0 V x
  • 0.09 V
  • the noise existing at the power source terminal VCC is below 1/10 and is hardly transmitted to the ground terminal VSS. Accordingly, the sense amplifier or the like does not operate erroneously due to the nosie transmitted to the ground terminal VSS.
  • 0.09 V Accordingly, the noise applied to the ground terminal VSS is hardly transmitted, either, to the power source terminal VCC and the sense amplifier or the like does not operate erroneously due to the noise transmitted to the power source terminal VCC.
  • the output of one selected NAND gate among the four NAND gates 12 forming the row selection circuit 3-1 changes from the high level to the low level and the output of one non-selected NAND changes from the low level to the high level but the outputs of the remaining two NANDs are kept at the high level. Since the gate capacitance of the memory cells connected to the outputs of these NANDs keeping the high level operate as the smoothing capacitance, any adverse influences are not exerted on the operation of the row selection circuit 3-1 even though the NAND gates constituting the row selection circuit 3-1 and the power source terminal VCC are connected to each other through the resistance element RX of about 100 ⁇ .
  • each memory cell block consists of eight or sixteen memory cells and among the NAND gates 12 forming the row selection circuit, six among eight or fourteen among sixteen keep the high level even if the address signal changes.
  • the gate capacitances of the memory cells connected to the outputs of these NAND gates 12 keeping the high level become an extremely great smoothing capacitance and the resistance element RX of about 100 ⁇ or so does not at all affect adversely the operation of the row selection circuit.
  • the similar effect can be obtained by connecting an N-channel MOSFET whose gate is connected to the power source terminal VCC in place of the resistance element RX.
  • Fig. 19 is a circuit diagram showing the fifth embodiment of the present invention.
  • the circuit of this embodiment has the structure wherein the NAND gates forming the row selection circuit 3-1 of the forth embodiment shown in Fig. 13 are replaced by three-input NAND gates 13 shown in Fig. 17.
  • the NAND gate 13 for driving the column lines W00 - W13 and the NAND gate 13 for driving the column lines W20 - W33 are disposed, and the address signals AB1 and AB1 inputted to the memory cell block selection circuit 3-2 are applied to the NAND gates for driving the column line W00 - W13 and to the NAND gates for driving the column lines W20 - W33 so that either one of the NAND gates for driving the column lines W00 - W13 and the NAND gates for driving the column lines W20 - W33 are selected.
  • the NAND gates 13 forming the row selection circuit 3-1 are connected to the power source terminal VCC through the resistor element RX. Therefore, the similar effect to that of the fourth embodiment can be obtained obviously and the description is therefore omitted.
  • the four column lines i.e., W00, W10, W20 and W30, in the embodiment shown in Fig. 13, change from the low level to the high level and enter the non-selection state and the four column lines W01, W11, W21 and W31 change from the high level to the low level and enter the selection state. Furthermore, the column lines W02, W03, W12, W13, W22, W23, W32 and W33 keep the high level. In the embodiment shown in Fig.
  • the power source is connected to the buffer or the row selection circuit through the resistance element and therefore it provides the effect of preventing the erroneous operation of the other circuit blocks such as sense amplifier or the like due to the noise transmitted from the power source terminal to the ground terminal or vice versa.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Dram (AREA)

Claims (6)

  1. Halbleiterspeichervorrichtung mit einem Speicherzellenfeld (1) mit einer Anzahl von Speicherzellen, einem ersten Spannungsanschluß (TGND) zum Empfang einer ersten Spannung, einer ersten Peripherieschaltung (2, 3) zum operativen Auswählen zumindest einer der Speicherzellen, einer zweiten Peripherieschaltung (4) zum operativen Auslesen eines Signals aus der ausgewählten Speicherzelle, einer ersten Versorgungsverdrahtung (GX, GY) zum Verbinden der ersten Peripherieschaltung mit dem ersten Spannungsanschluß, einer zweiten Verdrahtung (GS) zum Verbinden der zweiten Peripherieschaltung mit dem ersten Spannungsanschluß, dadurch gekennzeichnet, daß die Speichervorrichtung ferner ein erstes Impedanzelement (RGSC, M1) aufweist, das zwischen die zweite Verdrahtung (GS) und den ersten Spannungsanschluß (TGND) geschaltet ist, und daß die erste Verdrahtung die erste Peripherieschaltung mit dem ersten Spannungsanschluß ohne Zwischenfügung des ersten Impedanzelementes verbindet.
  2. Speichervorrichtung nach Anspruch 1,
    dadurch gekennzeichnet, daß die zweite Peripherieschaltung einen Leseverstärker zum Verstärken des Signals aus der ausgewählten Speicherzelle aufweist.
  3. Speichervorrichtung nach Anspruch 1 oder 2,
    gekennzeichnet durch ferner eine dritte Verdrahtung (GS) zum Verbinden des Speicherzellenfeldes (1) mit dem ersten Spannungsanschluß über das erste Impedanzelement.
  4. Speichervorrichtung nach Anspruch 2,
    mit ferner einer Ausgangspufferschaltung (5) zum Empfangen eines Ausgangssignals von dem Leseverstärker und zum Erzeugen eines Ausgabedatensignals und mit einer vierten Verdrahtung (GO) zum Verbinden der Ausgangspufferschaltung mit dem ersten Spannungsanschluß ohne Zwischenschaltung des ersten Impedanzelementes.
  5. Vorrichtung nach Anspruch 1, 2 oder 3,
    mit ferner einem Zweitspannungsanschluß (TVCC) zum Empfang einer zweiten Spannung, einer zusätzlichen ersten Verdrahtung (VX, VY) zum Verwenden der ersten Peripherieschaltung mit dem zweiten Spannungsanschluß und einer zusätzlichen zweiten Verdrahtung (VS) zum Verbinden der zweiten Peripherieschaltung mit dem zweiten Spannungsanschluß,
    dadurch gekennzeichnet, daß die Speichervorrichtung ferner ein zweites Impedanzelement (RVS) aufweist, das zwischen die zusätzliche zweite Verdrahtung und den zweiten Spannungsanschluß geschaltet ist.
  6. Nur-Lese-Halbleitervorrichtung mit einem Speicherzellenfeld (1) aus einer Anzahl von Speicherzellblöcken (MCB), die in Matrixform aus Reihen und Spalten angeordnet sind, wobei jeder der Speicherzellblöcke eine Reihenschaltung aus einer Anzahl von Speicherzellen aufweist, mit einer Anzahl von Spaltenleitungen (D0-D3) zum Verbinden der Speicherzellblöcke in Spaltenrichtung, einer Anzahl von Zeilenleitungen (W00-W33) zum Verbinden der Speicherzellen, die die Speicherzellblöcke bilden, in Zeilenrichtung, einer Spaltenauswahlschaltung (2) mit einem Spaltendekoder (2-1) zum Empfangen von Spaltenadressignalen und einem Spaltenselektor (2-2), der durch das Ausgangssignal des Spaltendekoders betrieben wird, zum Auswählen der Spaltenleitungen, einer Zeilenauswahlschaltung (3-1) zum Empfangen von Zeilenadressignalen und zum Auswählen von Zeilenleitungen, einer Speicherzellblock-Auswahlschaltung (3-2) zum Empfangen von Adressignalen zur Auswahl der Speicherzellblöcke, einem Leseverstärker (4) zum Auslesen von in einer ausgewählten Speicherzelle des Speicherzellfeldes gespeicherten Daten, einem ersten und einem zweiten Spannungsanschluß (TVCC, TGND) zum Empfangen einer ersten bzw. einer zweiten Spannung, einer ersten und einer zweiten Verdrahtung (VS, GS) zum Verbinden des Leseverstärkers mit dem ersten bzw. dem zweiten Spannungsanschluß, einer dritten und einer vierten Verdrahtung (VY, GY) zum Verbinden der Spaltenauswahlschaltung mit dem ersten bzw. dem zweiten Spannungsanschluß, einer fünften und einer sechsten Verdrahtung (VX, GX) zum Verbinden der Zeilenauswahlschaltung mit dem ersten bzw. dem zweiten Spannungsanschluß, und einer siebten und einer achten Verdrahtung (VP, GB) zum Verbinden der Speicherzellblock-Auswahlschaltung mit dem ersten bzw. dem zweiten Spannungsanschluß, wobei die Speichervorrichtung ferner ein Impedanzelement (RX) aufweist, das zwischen die Spaltenauswahlschaltung (3, 1) und die fünfte Verdrahtung (VX) geschaltet ist, um die erste Spannung am ersten Spannungsanschluß dadurch zur Spaltenauswahlschaltung zu liefern.
EP19890111678 1988-06-27 1989-06-27 Halbleiterspeichervorrichtung, die mit einer Niederrausch-Spannungsversorgung ausgestattet ist Expired - Lifetime EP0348895B1 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP158741/88 1988-06-27
JP15873388A JPH0738275B2 (ja) 1988-06-27 1988-06-27 読出専用半導体記憶装置
JP15874188A JP2822391B2 (ja) 1988-06-27 1988-06-27 半導体記憶装置
JP158733/88 1988-06-27

Publications (3)

Publication Number Publication Date
EP0348895A2 EP0348895A2 (de) 1990-01-03
EP0348895A3 EP0348895A3 (en) 1990-08-22
EP0348895B1 true EP0348895B1 (de) 1995-05-17

Family

ID=26485761

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19890111678 Expired - Lifetime EP0348895B1 (de) 1988-06-27 1989-06-27 Halbleiterspeichervorrichtung, die mit einer Niederrausch-Spannungsversorgung ausgestattet ist

Country Status (2)

Country Link
EP (1) EP0348895B1 (de)
DE (1) DE68922659T2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2557553B2 (ja) * 1990-05-28 1996-11-27 株式会社東芝 スタティック型半導体メモリ
FR2695752B1 (fr) * 1992-09-16 1994-11-10 Matra Mhs Mémoire de programme à semi-conducteur protégée en lecture.
CN1040809C (zh) * 1994-07-11 1998-11-18 凌阳科技股份有限公司 高密度掩模式只读存贮体

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5780828A (en) * 1980-11-07 1982-05-20 Hitachi Ltd Semiconductor integrated circuit device
JPS58114392A (ja) * 1981-12-07 1983-07-07 Fujitsu Ltd 半導体記憶装置
JPS60152039A (ja) * 1984-01-20 1985-08-10 Toshiba Corp ＧａＡｓゲ−トアレイ集積回路
JPH0693497B2 (ja) * 1986-07-30 1994-11-16 日本電気株式会社 相補型ｍｉｓ集積回路

Also Published As

Publication number Publication date
EP0348895A2 (de) 1990-01-03
DE68922659T2 (de) 1995-12-21
EP0348895A3 (en) 1990-08-22
DE68922659D1 (de) 1995-06-22

Similar Documents

Publication Publication Date Title
KR930006843B1 (ko) 반도체 집적회로
US4651304A (en) EPROM memory device having a test circuit
US5761148A (en) Sub-word line driver circuit for memory blocks of a semiconductor memory device
US5157280A (en) Switch for selectively coupling a power supply to a power bus
EP0199501A2 (de) CMOS-Stromdetektorverstärker
EP0814484A1 (de) Nichtflüchtiger Speicher mit Einzelzellenreferenzsignalgeneratorschaltung zum Auslesen von Speicherzellen
US5132933A (en) Bias circuitry for nonvolatile memory array
US6069838A (en) Semiconductor memory device having sub-word line driving circuit
US6525967B1 (en) Fast-sensing amplifier for flash memory
US4903237A (en) Differential sense amplifier circuit for high speed ROMS, and flash memory devices
US5933373A (en) Semiconductor memory device having constant potential generator for clamping digit lines at constant level allowing precharge transistor to slightly turn on
US5120999A (en) Output-buffer noise-control circuit
US5499212A (en) Semiconductor memory device having a bias control circuit for erase voltage blocking transistor
US5038327A (en) Decoder circuit of erasable programmable read only memory for avoiding erroneous operation caused by parasitic capacitors
US5677889A (en) Static type semiconductor device operable at a low voltage with small power consumption
EP0348895B1 (de) Halbleiterspeichervorrichtung, die mit einer Niederrausch-Spannungsversorgung ausgestattet ist
US6407957B2 (en) Semiconductor memory
EP0443777B1 (de) Schreibeschaltung für eine nichtflüchtige Speicheranordnung
JPH0722939A (ja) 論理回路
US20090116271A1 (en) Memory
KR0126908B1 (ko) 스태틱형 반도체 메모리 디바이스
US6151259A (en) Semiconductor memory device
KR970006194B1 (ko) 집접 메모리 회로
JP2822391B2 (ja) 半導体記憶装置
KR100189693B1 (ko) 논리게이트를 포함하는 반도체 집적회로

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 19890627

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): DE FR GB

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

RHK1 Main classification (correction)

Ipc: G11C 5/00

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): DE FR GB

17Q First examination report despatched

Effective date: 19930218

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB

REF Corresponds to:

Ref document number: 68922659

Country of ref document: DE

Date of ref document: 19950622

ET Fr: translation filed
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
REG Reference to a national code

Ref country code: GB

Ref legal event code: IF02

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20020626

Year of fee payment: 14

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20020702

Year of fee payment: 14

REG Reference to a national code

Ref country code: GB

Ref legal event code: 732E

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20030610

Year of fee payment: 15

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20030627

REG Reference to a national code

Ref country code: FR

Ref legal event code: TP

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20040101

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20030627

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20050228

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST