EP0300433A2 - Verfahren zum Herstellen eines Halbleiterverbundkörpers - Google Patents

Verfahren zum Herstellen eines Halbleiterverbundkörpers Download PDF

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Publication number
EP0300433A2
EP0300433A2 EP88111617A EP88111617A EP0300433A2 EP 0300433 A2 EP0300433 A2 EP 0300433A2 EP 88111617 A EP88111617 A EP 88111617A EP 88111617 A EP88111617 A EP 88111617A EP 0300433 A2 EP0300433 A2 EP 0300433A2
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EP
European Patent Office
Prior art keywords
surface roughness
bonded
semiconductor substrate
semiconductor
bonded semiconductor
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP88111617A
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English (en)
French (fr)
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EP0300433A3 (de
EP0300433B1 (de
Inventor
Tadahide Hoshi
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Toshiba Corp
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Toshiba Corp
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Publication of EP0300433A3 publication Critical patent/EP0300433A3/de
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Publication of EP0300433B1 publication Critical patent/EP0300433B1/de
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding

Definitions

  • This invention relates to a method for manufactur­ing bonded semiconductor bodies, and more particularly to a method for manufacturing semiconductor bodies by directly bonding silicon substrates together, or direct­ly bonding a substrate of Si, GaAs or other semiconduc­tor material with a substrate of the same material or different semiconductor material.
  • pn junctions and heterojunctions which have been considered difficult to form in a prior art can be easily formed in a short period of time.
  • the cost will be high when conven­tional epitaxial method is used, and it takes as long as three to ten days if a triple diffusion method is used.
  • the pn junction can be obtained in a period of as short as two hours by directly bonding the n ⁇ -type and p ⁇ -type layers together.
  • the both surfaces of Si substrates 1 and 2, facing at bonding interface 3, are cleaned and polished to make a mirror surface with a surface roughness (maximum height) of less than 500 ⁇ .
  • the mirror surfaces are physically brought into contact with each other in a clean atmosphere with no dust, and then the two substrates are subjected to a heat treatment at a temperature of higher than 200°C, nor­mally at a temperature of 1100°C, for two hours in an N2 gas atmosphere so as to increase the chemical bonding strength between the two substrates (Japanese Patent Disclosure 60-51700 and U.S. Patent Application No. 824,100 which was filed on Jan. 30, 1986 and is now abandoned).
  • the bonding strength between the two contacted substrates prior to the heat treatment is approx. 5 kg/cm2, but the bonding strength can be increased to 100 kg/cm2 after the heat treatment.
  • the outer surface of the bonded semiconductor body, which is different from the bonded surface, is subjected to rough polishing and finish polishing in this order, and then semiconductor elements and electrodes are formed in and on the bonded semiconductor body in the same manner as in case of using a single semiconductor substrate.
  • a bonded semiconductor body (4) having the above-mentioned large bonding strength (100 kg/cm2) can be obtained in a manner that a pair of semiconductor wafers, each having less than 500 ⁇ of a surface roughness and less than 5 ⁇ m of a total thickness variation range for the bond­ing area, are prepared, and they are contacted with each other in a clean atmosphere condition by which an interference fringe of voids due to dust can be removed.
  • the inventor of the present patent application has known that when bonded semiconductor body 4 obtained by the above manner is observed by the infrared topography, dark portions like the surface of the moon or Mars may sometimes be observed, as is shown in Fig. 1A.
  • the inventor does not know anyone who has investigated a specific relation between the dark por­tions as shown in Fig. 1A and defect of the resultant bonded semiconductor body. This is probably because the dark portions like the surface of Mars disappear after suitable heat treatment, as is shown in Fig. 1B and, after such heat treatment, the final product of bonded semiconductor body 4 has a large bonding strength as mentioned above.
  • the defect of the bonded semiconductor body can be found after the final product of the bonded semiconduc­tor body, on which many circuit elements are formed, is diced into small pieces or chips.
  • Bonded semiconduc­tor body 4 shown in Fig. 1B seems to be non-defective. Many circuit elements are formed on body 4 and then body 4 is diced into small chips (0.5 ⁇ 0.5 mm or 0.5 mm ⁇ ).
  • Fig. 1C shows an example of the resultant diced body 4 (observed by photograph, not by infrared topography).
  • the vertical and horizontal lines indicate the dicing lines with pitch of 0.5 mm
  • the slant lines indicate the defective portions in which parts of bonded 0.5 mm ⁇ chips are peeled off from their bonding interfaces, as is shown in Fig. 1D. Even if such peeling off does not happen, insufficient bonding of the chips causes to abnormally increase the electrical resistance thereof and, there­fore, such chips are also defective. In critical cases, bonded semiconductor body 4 itself is cracked and broken during the process of polishing or manufacturing the device (dicing).
  • Another object of this invention is to provide a method for manufacturing bonded semiconductor bodies which can provide substantially uniform image when observed by use of infrared topography.
  • a method for manufacturing bonded semiconductor bodies according to this invention comprises the steps of bringing the mirror surfaces of semiconductor sub­strates of the same type or different types, which may be chemical compound semiconductor substrate of GaAs, InP or GaP, silicon substrates and germanium substrates, into close contact with each other; and then subjecting the semiconductor substrates to a heat treatment at a temperature of higher than 200°C to bond the contacted mirror surfaces together.
  • the surface roughness of the mirror surfaces of the semiconductor substrates used is set equal to or less than 130 ⁇ in its maximum height for a measured range of 1 mm which is the length defined on a reference plane provided in a predetermined area on the mirror surface.
  • the surface roughness is set less than 130 ⁇ in its maximum height for the measured range of 1 mm on the reference plane provided in an area to be observed, dark portions like a sea in the surface of the moon or Mars will not appear in the image observed by use of infrared topography.
  • Fig. 2 shows the dependency of the bonding property on the surface roughness. As is clearly seen from Fig. 2, the bonding property is abruptly lowered when the surface roughness exceeds 130 ⁇ (indicated by one-dot-dash line).
  • the measured range in the reference plane provided on the surface is set to be 1 mm and set the maximum surface roughness to 130 ⁇ . Further, the total thickness vari­ation (TTV) of the entire surface of the wafer used here is set less than 5 ⁇ m.
  • N-type silicon wafers were prepared, each of which has a diameter of 100 mm and the resistivity of 20 to 30 ⁇ cm, each of whose total thick­ness variation (TTV) is less than 5 ⁇ m, and each of whose surface roughness ranges from 30 ⁇ to 280 ⁇ .
  • the measurement of the surface roughness was effected by use of non-bonded surface roughness measuring device, Model "Surfcom 920A" (spot diameter of 1.6 ⁇ m) manufactured by Tokyo Seimitsu Co. Ltd., Japan, and the maximum height was measured in five areas on the wafer with a magnifi­cation factor of 1,000,000 and a measurement distance of 1 mm. The average of the measurements was used to determine the surface roughness.
  • 500 wafers having the surface roughness of less than 130 ⁇ were selected as one lot from the origi­nally prepared and measured wafers, and 250 sets of con­tact wafers were formed by respectively contacting together two wafers selected out of the lot.
  • the 250 sets of contact wafers were subjected to bonding heat treatment at a temperature of 1100°C (lower than the melting point of the wafer) in an N2 gas atmosphere (the melting point of the Si wafer is approx. 1400°C).
  • Fig. 4 shows the state of void of the bonded wafers of the sample-1 and the comparison sample when observed by means of infrared topography.
  • the void in the comparison sample includes void, which is caused by dust and is indicated by interference fringes, and void due to the roughness indicated by dark portions similar to a sea on the moon or Mars.
  • the void in the sample-1 includes only void caused by dust and the amount thereof is substantially the same as the comparison sample, and includes no void due to the roughness.
  • Fig. 5 is a graph showing the yield of bonded semi­conductor bodies with respect to the comparison sample and sample-1, both of which have been subjected to the same device forming process.
  • the yield of the sample-1 is higher than that of the comparison sample by 13 %, and it has been de­termined that the improvement in the yield could be attained because the surface roughness was set less than 130 ⁇ to thereby completely prevent occurrence of crack or breakage of the semiconductor substrates.
  • wafers with the roughness of less than 130 ⁇ can be easily available from various wafer makers. Further, complete mirror surface wafers with the surface roughness of 130 ⁇ or less can be obtained by use of the polishing method disclosed in the follow­ing Japanese documents:
  • the infrared topography is used for observation of the bonding interface. How­ever, it is possible to use ultrasonic waves with a fre­quency of 10 to 30 MHz or higher frequency.
  • methods utilizing the ultrasonic waves there are a method using Computer Tomography which is well known in the art and another method utilizing the reflection of the ultrasonic waves at the bonding interface. The latter method utilizing the reflection of the ultrasonic waves is disclosed in, for example, Japanese Patent Disclosure No. 62-122141. (According to this Japanese Patent Disclosure, an ultrasonic waves of higher than 30 MHz are used).
  • Fig. 6 shows the bonding condition of a bonded semiconductor substrate wafer (sample A) according to this invention.
  • the surface roughness of sample A is less than 130 ⁇ .
  • Sample A is diced into 0.5 mm ⁇ pieces, and is observed by use of infrared topography.
  • Figs. 6A to 6C show the results of measurement of the surface roughness (92 ⁇ , 124 ⁇ , and 106 ⁇ ) in three preset points in Fig. 6.
  • Fig. 6 indicates that no void is observed on the entire surface of the wafer.
  • the white ring illustrated at the outer periphery of the disk-like wafer sample A shown in Fig. 6 indicates a non-bonded area.
  • the width of such a non-bonded area is generally about 2 mm for the wafer of 100 mm ⁇ diameter, and occurrence of such area, due to inevitable round-off at the edge of a disk-like wafer, cannot be avoided in practice.
  • such a non-bonded area causes no problem because it is removed during the manufacturing process thereof, and it is not relevant to the content of the present invention.
  • Fig. 7 shows the bonding condition of a bonded semiconductor substrate wafer (sample B) to which this invention is not applied.
  • Sample B includes not only areas having a surface roughness of less than 130 ⁇ , but also those having a surface roughness of more than 130 ⁇ .
  • Sample B is diced into 0.5 mm ⁇ pieces, and is observed by use of infrared topography, wherein a cross-­hatching portion indicates incomplete bonding portions.
  • Figs. 7A to 7C show the results of measurement of the surface roughness (286 ⁇ , 124 ⁇ , and 146 ⁇ ) in three preset points in Fig. 7. In Fig.
  • the white area indicates that the surface roughness (124 ⁇ ) is less than 130 ⁇ and there is no void, and the cross-hatching portion indicates that the surface roughness (286 ⁇ and 146 ⁇ ) is more than 130 ⁇ and incomplete contact due to void has occurred.
  • the surface roughness of the semiconductor substrate prior to the bonding is set less than 130 ⁇ so that incomplete con­tact due to the roughness of the substrate surface can be effectively prevented.
  • variation in the electrical characteristics in the bonding interface can be suf­ficiently suppressed, and therefore the element charac­teristics in the bonded semiconductor body can be made stable.
  • the manufacturing method of this invention contributes to low manufacturing cost and increase in yield of chips by use of bonded semiconduc­tor bodies.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
EP88111617A 1987-07-24 1988-07-19 Verfahren zum Herstellen eines Halbleiterverbundkörpers Expired - Lifetime EP0300433B1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP18351887 1987-07-24
JP183518/87 1987-07-24
JP18351887 1987-07-24

Publications (3)

Publication Number Publication Date
EP0300433A2 true EP0300433A2 (de) 1989-01-25
EP0300433A3 EP0300433A3 (de) 1989-09-13
EP0300433B1 EP0300433B1 (de) 2001-05-02

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EP88111617A Expired - Lifetime EP0300433B1 (de) 1987-07-24 1988-07-19 Verfahren zum Herstellen eines Halbleiterverbundkörpers

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EP (1) EP0300433B1 (de)
DE (1) DE3856465T2 (de)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996013060A1 (de) * 1994-10-24 1996-05-02 Daimler-Benz Aktiengesellschaft Verfahren zum direkten verbinden von planaren körpern und nach dem verfahren aus planaren körpern hergestellte gegenstände
DE10107405A1 (de) * 2001-02-14 2002-09-12 Rainer Schork Direktprozessierbare Halbleiterfolie

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0161740A2 (de) * 1984-05-09 1985-11-21 Kabushiki Kaisha Toshiba Verfahren zur Herstellung eines Halbleitersubstrates
EP0190508A2 (de) * 1985-02-08 1986-08-13 Kabushiki Kaisha Toshiba Verfahren zum Herstellen einer Halbleiterverbundanordnung
EP0190935A2 (de) * 1985-02-08 1986-08-13 Kabushiki Kaisha Toshiba Verfahren zur Herstellung von Halbleiteranordnungen mittels eines Bondierungsverfahrens

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0161740A2 (de) * 1984-05-09 1985-11-21 Kabushiki Kaisha Toshiba Verfahren zur Herstellung eines Halbleitersubstrates
EP0190508A2 (de) * 1985-02-08 1986-08-13 Kabushiki Kaisha Toshiba Verfahren zum Herstellen einer Halbleiterverbundanordnung
EP0190935A2 (de) * 1985-02-08 1986-08-13 Kabushiki Kaisha Toshiba Verfahren zur Herstellung von Halbleiteranordnungen mittels eines Bondierungsverfahrens

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Surface Roughness-Definitions and Designations JISB 0601, 1994, pages 15 - 38 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996013060A1 (de) * 1994-10-24 1996-05-02 Daimler-Benz Aktiengesellschaft Verfahren zum direkten verbinden von planaren körpern und nach dem verfahren aus planaren körpern hergestellte gegenstände
DE10107405A1 (de) * 2001-02-14 2002-09-12 Rainer Schork Direktprozessierbare Halbleiterfolie

Also Published As

Publication number Publication date
EP0300433A3 (de) 1989-09-13
EP0300433B1 (de) 2001-05-02
DE3856465D1 (de) 2001-06-07
DE3856465T2 (de) 2002-01-17

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