EP0294476A1 - N-bit sum-carry accumulator - Google Patents

N-bit sum-carry accumulator

Info

Publication number
EP0294476A1
EP0294476A1 EP88901742A EP88901742A EP0294476A1 EP 0294476 A1 EP0294476 A1 EP 0294476A1 EP 88901742 A EP88901742 A EP 88901742A EP 88901742 A EP88901742 A EP 88901742A EP 0294476 A1 EP0294476 A1 EP 0294476A1
Authority
EP
European Patent Office
Prior art keywords
carry
input
output
register
adder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP88901742A
Other languages
German (de)
French (fr)
Inventor
Iradj Shahriary
Victor S. Reinhardt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Raytheon Co
Original Assignee
Hughes Aircraft Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hughes Aircraft Co filed Critical Hughes Aircraft Co
Publication of EP0294476A1 publication Critical patent/EP0294476A1/en
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/509—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators
    • G06F7/5095—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators word-serial, i.e. with an accumulator-register
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/68—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using pulse rate multipliers or dividers pulse rate multipliers or dividers per se

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Complex Calculations (AREA)

Abstract

Le totalisateur amélioré (110) de la présente invention permet de pallier les insuffisances mises en lumière par l'état actuel de la technique. Ce totalisateur fournit un signal de sortie en réponse à un mot de fréquence d'entrée et comporte un additionneur (112) pour chaque bit du mot de fréquence à ajouter. Chaque additionneur (112) possède des première et seconde entrées (A et B), une sortie totaux représentant le total des première et seconde entrées et une sortie report (Co) représentant le total des première et seconde entrées. Tous les additionneurs (112) sauf le premier comportent une entrée report (Ci). Un premier registre de totalisation (114) permet de mettre en mémoire les sorties totaux desdits additionneurs (112). Les entrées dudit registre (114) sont les sorties totaux desdits additionneurs (112), les sorties du registre (114) étant les secondes entrées desdits additionneurs. Le totalisateur décrit comprend un second registre de report (115) destiné à mettre en mémoire les sorties report (Co) desdits additionneurs (112), les sorties dudit second registre (115) étant les entrées report (Ci) desdits additionneurs (112).The improved totalizer (110) of the present invention overcomes the shortcomings highlighted by the current state of the art. This totalizer provides an output signal in response to an input frequency word and includes an adder (112) for each bit of the frequency word to be added. Each adder (112) has first and second inputs (A and B), a total output representing the total of the first and second inputs and a carry output (Co) representing the total of the first and second inputs. All adders (112) except the first have a carry-over input (Ci). A first totalization register (114) makes it possible to store the total outputs of said adders (112). The inputs of said register (114) are the total outputs of said adders (112), the outputs of register (114) being the second inputs of said adders. The totalizer described comprises a second transfer register (115) intended to store the transfer outputs (Co) of said adders (112), the outputs of said second register (115) being the transfer inputs (Ci) of said adders (112).

Description


  
 



   N-BIT SUM-CARRY ACCUMULATOR
 BACKGROUND OF THE INVENTION
 1. Field of the Invention:
 The present invention relates to frequency synthesizers as used in high frequency communication systems. More specifically, the present invention relates to accumulators used in pulse output direct digital synthesizers and fractional division direct digital synthesizers.



   While the present invention is described herein with reference to an illustrative embodiment in an exemplary application, the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional modifications, embodiments and applications within the scope thereof.



   2. Description of the Related Art:
 High speed accumulators, i.e., those operating on the order of several gigahertz, are useful for many applications. For, example, high speed accumulators make possible direct digital frequency synthesizers. Direct digital frequency synthesizers are used in many applications of which high frequency communication systems are typical. In a communication system, the frequency synthesizer may serve to provide local and/or reference frequencies for the modulation or demodulation of an Incoming signal. Digital synthesizers generate the  output frequency with a digital as opposed to an analog technique.



   Two basic direct digital synthesizers (DDS) are known in the art: 1) pulse output DDSs and 2) fractional divider DDSs. The pulse output DDSs consists of an N bit accumulator set up to add the frequency word K to the accumulator value once every clock period (Tc). The frequency output is merely the carry output of the accumulator for a pulse output or the most significant bit of the accumulator for an approximate square wave output.



   The fractional divider DDS is a variation of the pulse type in which the accumulator carry output is used to drive the n/n+1 control line of a divide by n/n+1 counter so that   nil    division occurs on a carry.



   The heart of both types of DDSs is an N bit accumulator. A conventional accumulator consists of an N bit full adder and an N bit storage register as shown generally in Fig. la and in more detail in Fig.   lb.    The full adder provides the N bit sum, S, of two N bit inputs, A and B, and provides a carry which is the value of the N+lth bit of the sum. The storage register transfers the value S to the B input every time it   receivessa    clock pulse and so sequences the accumulator.



  Thus at each clock pulse, the value A is added to the current value stored in the accumulator.



   An N bit storage register typically consists of N independent D-flip flops clocked simultaneously. As a result, there is no inherent problem in building storage registers for large size words, that is, large values of
N.



   An N-bit full   1    adder typically consists of N 1-bit full adders plus possibly a carry look-ahead circuit. A   l-bit    full adder is shown in Fig. 2. For each bit there are A, B and C (carry) Inputs and S (sum) and C (carry) outputs.  



   As illustrated in Fig.   lb,    ripple carry N-bit adder consists of N 1-bit adders with the carry input of each bit connected to the carry output of the previous bit.



  For the ripple carry N-bit adder to function properly, all the intermediate carry outputs in the individual 1bit adders must have settled to their final value. Thus, an N bit ripple carry adder typically takes N times as long as a single l-bit adder to settle to its final value.



   A look-ahead carry adder provides a carry look-ahead circuit with a l-bit adder which anticipates whether there will be a carry at that bit based on the value of all the bits of lower significance of the A and B inputs.



  The general rule of thumb is that look-ahead circuits grow in complexity (number of gates) as N2 for an N-bit adder since each circuit must take into account all the previous bits.



   The basic problem of building N-bit accumulators for large N is, therefore, that of the carry in the adder.



  One building a DDS using the technology of the related art must tolerate either the slow speed of the ripple adder or the complexity of a look-ahead carry adder.



  There is therefore a need in the related art for a relatively simple, high speed accumulator.



   SUMMARY
 The shortcomings illustrated by the related art are addressed by the improved accumulator of the present invention which provides a periodic output signal in response to an input frequency word and includes one adder for each bit of the frequency word to be added.



  Each adder has first and second inputs, a sum output representing the sum of the first and second inputs, and  a carry output representing the sum of the first and second inputs. All but the first adder includes a carry input. A first sum register is included for storing the sum outputs of said adders. The inputs of said register being the sum outputs of said adders and the outputs of the register the second inputs of said adders. The invention includes a second carry register for storing the carry outputs of said adders. The output of said second register being the carry inputs of said adders.



   BRIEF DESCRIPTION OF THE DRAWINGS
 Fig la is a block diagram representation of a conventional accumulator of the prior art.



   Fig.   lb    is a detailed block diagram representation of the conventional accumulator of Fig. 1.



   Fig. 2 a schematic diagram of a l-bit full adder of the prior art.



   Fig. 3a is a block diagram representation of the Nbit separated sum-carry accumulator -of the present invention.



   Fig. 3b is a detailed block diagram representation of the N-bit separated sum-carry accumulator of the present invention.  



   DESCRIPTION OF THE INVENTION
 The speed, simplicity and advantageous operation of the present invention is illustrated in Figs. la -   3b    taken with reference to the following description. As mentioned above, a conventional accumulator 10 is shown diagrammatically in Fig. la as including an N-bit full adder 12 and an N-bit storage register 14. The adder 12 sums the signals appearing on inputs A and B and provides a sum output S and a carry output C. The sum output S is fed back to the adder via the storage register 14.



   The N-bit full adder 12 is shown in greater detail in Fig.   lb.    The input word K is stored in a serial to parallel latch 16 for input to a plurality of one bit adders 18 as A inputs. (Those of ordinary skill in the art will appreciate that the latch 16 would not be necessary if the input word K is supplied as a parallel word.) The B inputs are provided by the storage register 14 via the bus 19. Thus, each adder 18 has an A input designated as   Aj-AN    and a B input designated as   Bi-BN,    where in this example, N = 6. It is understood that the input word length N may be any number as is known in the art.



   A typical prior art one bit adder 18 is shown schematically in Fig. 2. It includes first and second eXclusive-OR (XOR) gates 20 and 22 respectively. The first gate 20 provides the exclusive-or of the A and B inputs to the adder 18 as a first input to the second XOR gate 22. The second input to the gate 22 is provided by the input carry Ci. Thus, the output of the second XOR gate 22 is the sum output S of the adder 18.



   The carry is generated by two AND gates 24 and 26 and an OR gate 28. Thus, for example, If both A and B are high the output of AND gate 26 is high and a carry  output Co is generated by gate 28. Alternatively, if either A or B is high and the carry input Ci is high, a carry output Co is generated by the OR gate 28.



   Returning now to Fig.   lb,    each adder 18 thus provides a sum output which is input to the storage register 14 and a carry output Co which is input to the next adder 18. The carry output CN of the Nth adder 18 is the output of the accumulator 10. Thus, if the register value is R, once every Tc the accumulator performs the operation:
 R + K - >  R in modulo 2N arithmetic. Note that for this addition process, the accumulator will overflow, on average, once every 2N/K clock periods, so the average frequency of overflows will be:
 fo = (K/2N) fc
 where fc is the clock frequency (fc =   l/Tc).   



   Thus, in order to provide an output, the carry must ripple through this conventional accumulator 10. This places a limitation on the speed of the accumulator.



   The present invention addresses this shortcoming of conventional ripple carry accumulators without significantly adding to the complexity of the overall system. As shown in Fig. 3a, the accumulator 110 of the present invention includes N separate l-bit adders 112, and S register 114 and a separate C register 115. The adders are implemented as shown in Fig. 2 and may be individual gates or purchased as adders, eg. 7480s or 7482s. The registers may be D flip-flops or J-K flipflops, eg. 7474s or 7473s. Other suitable components may be substituted to Implement the functions of the adders and registers as is known In the art.  



   As shown in Fig. 3b, the adder circuit 112 of the present invention 10 cooperates with the S register 114 in a manner similar to that discussed above with reference to a conventional accumulator 10. However, the individual carry outputs of the N-1 adders 118 are input to the second C register 115 instead of being provided as carry inputs to the following adder. Instead, the individual carry outputs are stored and during the next clock period, input to the following adder as a carry input. For example, the carry output of the first adder is stored in the C register 115 during one clock period and input to the carry input of the second adder during the next clock period.



   If the binary value of Co (represented by   CoN#1    -   Col)    is shifted left one digit so the value Col appears at the 2nd bit place, etc., the modulo 2N sum of A, B, and Ci can be written as:
 S = S' + Co = A + B + Ci
 Thus, when the frequency word K is input to the accumulator 110 at A and the accumulator 110 is clocked n times, the S' + Co will represent the true modulo 2N value of nK. Thus, the accumulator 110 of the present invention will output as many carries on the average as the conventional accumulator 10 (though the carries will not be in the same places in both sequences).



   Assume for example that the three bit frequency word
K is 1 1 1 and is input to the conventional ripple carry accumulator 10 of Fig. 1. Thus, A3A2A1 = 1 1 1 and
B3B2B1 = 0 0 0. Thus, the conventional accumulator 10 will operate as follows for three clock periods:  
 A3A2A1   B38281    0 0 0
 + B3B2B1 equals + A3A2A1 = >  + 0 1 1
 011 during the second clock pulse, B = 0 1 1 so - >  0 1 1
 110 during the third clock pulse, B = 1 1 0 so - >  0 1 1 so that an output carry is generated:

   1 0 0 1
 To   illustrate    the operation of the accumulator 110 of the present invention, it is useful to look at the state of the   carry#dynamically:   
Thus, for the first clock period, B is O 0 0
 A is   0    1 1
 and C is O 0 0 yielding a new B value in the accumulator - >  0 1 1 adding a new A on the next clock pulse - >  0 1 1 and the carry from the previous addition - >  0 0 0
 yields a new B of - >  0   O O   
 and a new carry of - >  1 1 0 which when added to A on the next pulse - >  0 1 1
 yields a sum of - >  1 0 1 but, more importantly, a carry output of - >  1 0 0 which is an output carry from the third or Nth adder.



   Thus, while the sum may not be accurate, the carry appears from the same number of clock pulses as the  invention is not limited thereto. Those having ordinary skill in the art and access to the teachings of the present invention will recognize additional modifications, applications and embodiments within the scope thereof. For example, the invention is not limited to the applications mentioned above. It may be used in any suitable application where digital frequency control is desired. In   addition,    as mentioned above, the invention is not limited to any particular implementation for the adders and the registers.



   It is intended to cover any and all such modifications, applications and embodiments within the scope of the invention with the following claims in which what is claimed is:

Claims

CLAIMS I. An improved accumulator for providing a periodic output signal in response to an input signal comprising: at least one adder having a first input, a second input, a carry input, a sum output representing the sum of the first and second inputs and a carry output representing the carry associated with the sum of the first and second inputs; a first register for storing the sum outputs of said adder, the input of said register being connected to the sum output of said adder and the output of the register being connected to the second input to said adder; and a second register for storing the carry outputs of said adder, the input of said second register being the carry output of said adder and the output of said second register being the carry input of said adder.
2. The improved accumulator of Claim 1 including N l-bit adders each having a first input, a second input, a carry input, a sum output representing the sum of the first and second inputs and a carry output representing the carry associated with the sum of the first and second inputs.
3. The improved accumulator of Claim 2 wherein the output of said first register is the second input to a second adder.
4. The improved accumulator of Claim 3 wherein the output of said second register is input to the carry input of said second adder.
5. The improved accumulator of Claim 4 wherein said carry output of said Nth adder is the output of said accumulator.
6. The improved accumulator of Claim 5 responsive to an input signal which is a frequency word of predetermined length.
7. An N-bit separated sum and carry accumulator for providing a periodic output signal in response to an input signal which is a frequency word of predetermined length comprising: N one-bit adders each having a first input, a second input, a carry input, a sum output representing the sum of the first and second inputs and a carry output representing the carry associated with the sum of the first, second, and carry inputs, the carry output of the Nth adder being the output of the accumulator; a first register, for storing the sum of the outputs of said adders, the inputs to said register being provided by the sum outputs of said adders and the output of said register being selectively connected to the second input of selected adders;
and a second register for storing the carry outputs of said adder, the input of said second register being the carry output of the nth adder and the output of said second register being the carry input to the n+lth adder.
8. An improved accumulator for frequency synthesizers for providing a periodic output signal in response to an input signal which is a frequency word of predetermined length comprising: N one-bit adders each having a first input, a second input, a carry input, a sum output representing the sum of the first and second Inputs and a carry output representing the carry associated with the sum of the first and second inputs, the carry output of the Nth adder being the output of the accumulator; a first register, for storing the sum outputs of said adders, the inputs to said register being provided by the sum outputs said adders and the output of said register being selectively connected to the second input of selected adders;
and a second register for storing the carry outputs of said adder, the input of said second register being the carry output of the nth adder and the output of said second register being the carry input of the n+lth adder.
9. A separated sum and carry accumulator for frequency synthesizers for providing a periodic output signal in response to an input signal which is a frequency word of predetermined length comprising: N one-bit adders having a first input, a second input, a carry input, a sum output representing the sum of the first and second inputs and a carry output representing the carry associated with the sum of the first and second inputs, the carry output of the Nth adder being the output of the accumulator; a first register, for storing the sum outputs of said adders, the inputs to said register being provided by the sum outputs of said adders and the output of said register being selectively connected to the second input of selected adders;
and a second register for storing the carry outputs of said adder, the input of said second register being the carry output of the nth adder and the output of said second register being the carry input of the n+lth adder.
10. A method for generating a output signal of a predetermined frequency including the steps of: a) Inputting during a first clock period a first digital signal to a separated sum and carry accumulator comprising at least one adder having a first input, a second input, a carry input, a sum output representing the sum of the first and second inputs and a carry output representing the sum of the first and second inputs; a first register for storing the sum outputs of said adder, the input of said register being connected to the sum output of said adder and the output of the register being connected to the second input to said adder;
and a second register for storing the carry outputs of said adder, the input of said second register being the carry output of said adder and the output of said second register being the carry input of said adder; b) storing signals representing the sum of said first digital signal with a second input in a first register; c) storing signals representing the carry generated by the summing of said first and second input signals in a second register; d) providing the stored sum signal as said second input to said adder; e) providing the stored carry signals to said carry input of said adder; and f) clocking the accumulator to provide an output carry signal.
EP88901742A 1986-12-30 1987-12-07 N-bit sum-carry accumulator Withdrawn EP0294476A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US947786 1978-10-02
US94778686A 1986-12-30 1986-12-30

Publications (1)

Publication Number Publication Date
EP0294476A1 true EP0294476A1 (en) 1988-12-14

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP88901742A Withdrawn EP0294476A1 (en) 1986-12-30 1987-12-07 N-bit sum-carry accumulator

Country Status (4)

Country Link
EP (1) EP0294476A1 (en)
JP (1) JPH01501905A (en)
KR (1) KR890700243A (en)
IL (1) IL84822A0 (en)

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO8805189A1 *

Also Published As

Publication number Publication date
WO1988005189A1 (en) 1988-07-14
JPH01501905A (en) 1989-06-29
KR890700243A (en) 1989-03-10
IL84822A0 (en) 1988-06-30

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