EP0292189B1 - Aufbesserung von kanonischen, mit Vorzeichenziffern behafteten Filterkoeffizienten - Google Patents

Aufbesserung von kanonischen, mit Vorzeichenziffern behafteten Filterkoeffizienten Download PDF

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Publication number
EP0292189B1
EP0292189B1 EP88304271A EP88304271A EP0292189B1 EP 0292189 B1 EP0292189 B1 EP 0292189B1 EP 88304271 A EP88304271 A EP 88304271A EP 88304271 A EP88304271 A EP 88304271A EP 0292189 B1 EP0292189 B1 EP 0292189B1
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Prior art keywords
coefficient
bit
block
values
sign
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French (fr)
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EP0292189A2 (de
EP0292189A3 (en
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Kannan P. Vairavan
Paul Mcleod
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/0223—Computation saving measures; Accelerating measures
    • H03H17/0238—Measures concerning the arithmetic used
    • H03H17/0239—Signed digit arithmetic
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/0223—Computation saving measures; Accelerating measures
    • H03H17/0227—Measures concerning the coefficients
    • H03H17/023—Measures concerning the coefficients reducing the wordlength, the possible values of coefficients
    • H03H2017/0232—Canonical signed digit [CSD] or power of 2 coefficients

Definitions

  • the present invention relates to digital filters and, more particularly, to a method of incrementation and decrementation of Canonic Signed Digit (CSD) filter coefficients.
  • CSD Canonic Signed Digit
  • Digital filters are used in adaptive circuits, such as adaptive subscriber line audio-processing circuits (SLACs), which require periodic updating of the filter coefficients.
  • SLACs adaptive subscriber line audio-processing circuits
  • a SLAC filter should be able to automatically adjust to the subscriber line impedance and the filter coefficients need to be continuously updated to balance the time-varying line impedance.
  • Updating the coefficients is typically done by the use of counters which increment or decrement their value periodically.
  • the coefficients are typically represented by a sign and shift code. It is therefore required that their coded representation be of a decimal sequence which is a monotone strictly increasing or decreasing.
  • Coefficient updating algorithms are known to be complex; requiring lengthy mathematical processes. Because it is desired that SLACs, and the like, operate in real time, simplifications of the update algorithms used is necessary.
  • the present invention provides a method of incrementing and decrementing a decimal-valued digital filter tap coefficient A comprising a plurality of multi-bit coefficients arranged in a most-to-least significant order, each multi-bit coefficient represented in a canonic signed digit (CSD) binary code having a sign portion and a shift code portion, each multi-bit coefficient having a predetermined range and an associated direction indicator, coefficient values within said predetermined range having a predetermined decreasing order whereby said decimal values of A form a monotonically strictly increasing sequence, said incrementation/decrementation method comprising, for each said least-significant to said most-significant multi-bit coefficient, the steps of:
  • each tap coefficient is represented as a number of multi-bit coefficients portions arranged in a most-to-least significant manner.
  • Each multi-bit coefficient portion is represented in a canonic signed digit (CSD) code having a sign portion and a shift code portion.
  • CSD signed digit
  • the method restricts the range of each multi-bit coefficient. By restricting the range of each multi-bit coefficient, the CSD-coded value may be "adjusted" (i.e., incremented, decremented or placed at an endpoint of its range and direction reversed) and the resulting decimal value will be incremented or decremented, accordingly.
  • the method provides for the sign portion and direction to be readily calculated by an exclusive-OR function of the present signs of the multi-bit coefficients.
  • Fig. 1 is a schematic representation of a digital filter, employing eight tap coefficients.
  • Fig. 2 is a signal-flow diagram illustrating the derivation of an error signal as the difference between an actual digital filter and an ideal or desired filter.
  • Fig. 3A is a diagrammatic illustration of the updating method of filter tap coefficients of the instant invention for a 3 nibble CSD format.
  • Fig. 3B is a diagrammatic illustration of the direction of movement through the filter tap coefficients employed by the method of the instant invention for a 3 nibble CSD format.
  • Fig. 4 is a unitary drawing comprising Figs. 4A, 4B, 4C and 4D illustrating in flowchart form the update method of the instant invention for a 3 nibble format.
  • Fig. 1 schematically illustrates an 8 tap digital filter, commonly known as a finite impulse response (FIR) filter 10.
  • FIR finite impulse response
  • Such a filter is commonly known as a transversal or non-recursive filter and includes seven storage or delay units 12, eight multipliers 14 and seven adder units 16.
  • IIR filters infinite impulse response filters
  • SLAC subscriber line audio-processing circuit
  • a particular response Y(nT) will be generated for an input X(nT).
  • the difference between Y(nT) generated by filter 10 and that of an ideal filter or a desired filter 18 is determined by a summation node 20 at which the input X(nT) is applied to actual filter 10 and desired filter 18; their respective outputs applied to a subtractive and additive input, respectively, of node 20.
  • the sum generated by node 20 is an error(nT) signal.
  • Coefficient updating algorithms are known to be complex; requiring lengthy mathematical processes. Because it is desired that SLACs, and the like, operate in real time, simplifications of the update algorithms used is necessary.
  • the filter function is performed by a series of multiplications and accumulations.
  • a multiplication node 14 is implemented by shifting the multiplicand and summing the result with the previous value at a summation node 16.
  • the coefficient updating method of the present invention employs a cannonic signed digit (CSD) binary encoding to represent the filter tap coefficients.
  • CSD cannonic signed digit
  • the CSD encoding will use n binary coefficients C1, C2, ..., Cn, each called a coefficient "nibble".
  • Each binary coefficient having a shift portion Mi so that the decimal value of a filter tap coefficient A is related to its CSD encoding according to the formula A [C1*2 -M1 [1+C2*2 -M2 [1+C3*2 -M3 [1+...[1+Cn*2 -Mn ]...] (3)
  • the tap coefficient A takes on values from +n to -n.
  • Each nibble therefore is representable as a decimal number having a hexadecimal value 0, 1, ..., 8, 9, A, B, C, D, E, F.
  • hexadecimal values 0, 1, 9 and 8 are initially to be excluded from coefficient nibbles. Accordingly, there are (12) n possible combinations to form a tap coefficient A when using n nibbles. Added to this are “end sequences” employing 0, 1, 9 and 8, as will be explained hereinafter, producing 4*(12) n-1 possible end combinations. In addition, there are “tail sequences” employing 0 and 8, producing possible tail combinations.
  • each tap of which has three 4-bit hexadecimal "nibble" coefficients C1, C2 and C3, the most-significant being C1 and the least-significant being C3.
  • the coefficient update method of the present invention mandates the following conditions on the 4-bit coefficients C1, C2 and C3:
  • Fig. 3A A typical incrementation or decrementation sequence is illustrated in Fig. 3A for 3 nibble CSD format.
  • the diagram shows the movement through the coded tap coefficient values for a particular value of C1 and variable value of C2 and C3 in terms of the shift codes M1, M2 and M3.
  • the representative values of M2 equal to 3, 4 and 5 are shown.
  • the pattern shown repeats for all values of M2.
  • the value of M1 is shown in Fig. 2 as "x" which stands for any hexadecimal value that M1 can take on, i.e., "don't care".
  • Figure 3B diagrammatically illustrates how the sign S1 and S2 of the coefficients C1 and C2 determines the direction of movement through the coded tap values C2 and C3.
  • a ⁇ pattern in Fig. 3 indicates movement in the direction from most positive decimal value to most negative decimal value while a ⁇ pattern indicates movement in the direction from most negative to most positive. Selection of the direction of movement is therefore given by the exclusive-OR (exor) function; for example for C3:
  • the coefficient update method described in terms of three nibble coefficients C1, C2 and C3 can be extended to n nibble coefficients C1, C2, ..., Cn in the following manner: the restrictions imposed on coefficient C3 in condition III, supra, also are imposed on coefficients C4, ..., Cn.
  • Condition IV is generalized to: when Cn-1 changes sign, sequence Cn changes direction
  • condition V is generalized to: when C1 changes sign, the C2, C3, ..., Cn sequences change direction.
  • Fig. 4 a unitary drawing illustrating in flowchart form the coefficient update method of the instant invention, the method begins with the current values of the coefficients C1, C2, C3 and the current direction (DIR) of movement through the coded tap values. These values are set at block 100 of Fig. 4A.
  • a variable MASK1 is set to 7 in a block 101 preceding block 100.
  • MASK1 is used in a subroutine COMMON described hereinafter.
  • Block 102 is next entered which calls for splitting the coefficients into their sign and shift code portions and the setting of various flags used later in the method.
  • a FLAG 1 and FLAG2 are initially used to indicate detection of tailend sequence in C3; later FLAG2 and a FLAG 3 are set to ZERO if no coefficient updating is to be performed, set to ONE if coefficient incrementation is to be performed, and set to minus ONE if coefficient decrementation is to be performed.
  • a block 104 is next entered which begins the method by the updating of C3 and accordingly a S3FLAG is set to ZERO in block 104; S3FLAG indicates reversal of direction of movement through the C3 coefficient values.
  • a decision block 106 is next entered which tests whether S1 exor S2 is a ONE. This block implements the exclusive-OR function described above and determines the proper direction of movement through the C3 coefficient values.
  • Block 108 invokes a subroutine called "COMMON” which is illustrated in flowchart form as Fig. 4D.
  • COMMON a subroutine which is illustrated in flowchart form as Fig. 4D.
  • a description of the COMMON subroutine will be given below in connection with Fig. 4D.
  • Block 118 leads to a decision block 120 which tests whether M1 is less than ZERO. If not, the N exit is taken which completes the update of C3 portion; if so, Y-exit is taken and M1 is set to ZERO in a block 122 which then completes the update of C3 portion.
  • a decision block 124 is first entered which tests whether S1 equals ZERO AND S2 equals ZERO. If so, a Y-exit leads to a decision block 126 which tests whether S3 equals ZERO. If so, a Y-exit leads to block 128 which sets FLAG3 to ONE and then to a block 130 which sets S3 to ONE. If S3 does not equal ZERO, a N-exit of block 126 leads to a block 132 which sets FLAG3 to minus one and then to a block 134 which sets S3 to ZERO.
  • a decision block 136 is executed which performs analogous tests of S1 equals ZERO and S2 equals ONE.
  • a decision block 148 is executed which performs analogous tests if S1 equals ONE and S2 equals ONE.
  • a complete descripton of this portion of the flowchart of Fig. 4B, comprising a decision block 150 and blocks 152, 154, 156 and 158 is omitted in the interest of brevity.
  • a decision block 160 is executed which performs analogous tests if S1 equals ONE and S2 equals ZERO.
  • a complete description of this portion of the flowchart of Fig. 4B, comprising a decision block 162 and blocks 164, 166, 168 and 170 is likewise omitted.
  • a block 172 is entered which sets M3 to 2 and then a block 174 is entered which sets S3FLAG to 1.
  • the C3 update portion of the method of the preent invention is completed and a block 178 is entered which begins the update of C2.
  • the sign of C3 (S3) has been set and the shift code of C3(M3) has been set to 2.
  • Block 178 sets S2FLAG to ZERO and thereupon a block 180 is entered which invokes the subroutine "COMMON".
  • COMMON Upon return from COMMON a decision block 182 is entered which tests whether M2 is less than 2. The N-exit of block 182 leads to a block 184 which sets FLAG2 to ZERO.
  • the Y-exit of block 182 leads to a decision block 186 which tests whether FLAG1 equals ZERO AND S2 equals ZERO. This test determines whether the end of region for M1 has been reached with C2 positive. If so, the Y-exit leads to a block 188 which sets FLAG2 to ZERO. The N-exit leads to a block 190 which sets FLAG2 to minus ONE and then on to a decision block 192.
  • Block 192, a decision block 194 and blocks 196, 198, 200 and 202 perform an analogous ex-or function to that performed by blocks 136, 138, 140, 142, 144 and 146 described herein above and will not be described in further detail.
  • a block 204 is entered which sets M2 to 2 and then a block 206 is entered which sets S2FLAG to 1.
  • a decision block 208 (Fig. 4C) is entered which begins the update of C1.
  • the sign of C2(S2) has been set and the shift code of C2 (M2) has been set to 2.
  • decision block 208 tests whether DX equals ONE and S1 equals ONE. This determines a Y-exit of block 208 leads to a block 210 which sets FLAG2 to its opposite value -FLAG2. Upon execution of block 210 or the N-exit of block 208, a block 212 is executed which invokes the COMMON subroutine.
  • a decision block 214 Upon return from COMMON, a decision block 214 is executed which implements the ex-or functions described hereinabove. These ex-or functions set S2 and S3 by portions of the flowchart of Fig. 4C comprising decision blocks 216, 218, 224, 226 and 228 and blocks 220, 222, 230 and 232. In the interests of brevity their descriptions will be omitted.
  • Block 234 sets S3 to the sign portion of S3, a block 236 is next entered which sets S2 to the sign portion of S2 and a block 238 is next entered which sets S1 to the sign portion of S1.
  • a block 240 is next entered which sets C3 to the sign plus shift code portions of M3.
  • a block 242 is next entered which sets C2 to the sign plus shift code portions of M2 and a block 244 is next entered which sets C1 to the sign plus shift code portions of M1.
  • a block 246 is entered which calls for reporting the updated values of C1, C2 and C3.
  • a flowchart of the COMMON subroutine is shown. Entry to COMMON is by the way of a block 248 which leads to a decision block 250 which tests the S parameter, which will be S3, S2 or S1 depending on whether the subroutine is invoked at block 110, block 180 or block 212, respectively, equals ONE. If so, the Y-exit leads to a block 252 which sets the M parameter, which will be M3, M2 or M1, respectively, to 15-M.
  • a block 254 executed which sets the M parameter to M-DIR.
  • the DIR parameter will be DIR, FLAG 3 or FLAG2, respectively, depending on whether the subroutine is invoked at block 110, block 180 or block 212, respectively. This parameter determines whether incrementation, decrementation or no change will be effected in this invokation of COMMON.
  • a block 256 is entered which sets the S parameter to the M parameter.
  • a block 258 is entered which sets the S parameter to the sign portion of S.
  • a block 260 is next entered which forms the logical AND of the M parameter with the MASK1 value and sets M to the result.
  • a decision block 262 is entered from block 260 which tests whether the S parameter equals ONE, if so the Y-exit leads to a block 264 which sets M to MASK1-M. Following execution of block 264 or the N exit of block 262 the COMMON routine exists via a block 266 to return to the envoking block 110, 150 or 212 and the parameters S3 and M3, S2 and M2 or S1 and M1 will have been accordingly modified.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • Theoretical Computer Science (AREA)
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Claims (5)

  1. Verfahren zum Inkrementieren und Dekrementieren eines dezimalwertigen digitalen Filterabgriffskoeffizienten A mit mehreren Mehrfachbit-Koeffizienten, die in einer Reihenfolge vom höchst- zum niederwertigsten angeordnet sind, wobei jeder Mehrfachbit-Koeffizient in einem kanonisch mit Vorzeichenziffer (CSD) versehenen Binärcode wiedergegeben ist, der einen vorzeichenteil und einen Schiebecodeteil aufweist, wobei jeder Mehrfachbit-Koeffizient einen vorbestimmten Bereich und einen zugehörigen Richtungsanzeiger hat, wobei Koeffizientenwerte innerhalb des vorbestimmten Bereichs eine vorbestimmte abnehmende Ordnung aufweisen, wodurch die Dezimalwerte von A eine strikt monoton ansteigende Sequenz bilden, wobei das Inkrementier-/Dekrementierverfahren für jeden der Mehrfachbit-Koeffizienten, vom geringstwertigen bis zum höchstwertigen, die folgenden Schritte umfaßt:
    (a) Einstellen des Vorzeichen- und Schiebecodeteils des Mehrfachbit-Koeffizienten unter Verwendung des Richtungsanzeigers, um in Abhängigkeit davon, ob der Richtungsanzeiger einen ersten oder zweiten vorbestimmten Wert hat, den nächsten verringerten oder erhöhten Wert in der abnehmenden Ordnung anzunehmen, und
    (b) wenn sich der eingestellte Mehrfachbit-Koeffizient außerhalb des vorbestimmten Bereichs befindet, Bestimmen eines neuen Richtungsanzeigers und eines neuen Vorzeichenteils für den Mehrfachbit-Koeffizienten.
  2. Abgriffskoeffizienteninkrementier-/Dekrementierverfahren nach Anspruch 1, bei dem der Abgriffskoeffizient A n Mehrfachbit-Koeffizienten aufweist, die in der Reihenfolge vom höchst- zum geringstwertigen C1, C2, C3, ....., Cn, angeordnet sind, wobei jeder Mehrfachbit-Koeffizient C1 den Schiebecodeteil Mi aufweist, bei dem der Dezimalwert von A mit dem Mehrfachbit-Koeffizienten durch die Formel

    A = [C1*2 -M1 [1+C2*2 -M2 [1+C3*2 -M3 [1+... [1+C n *2 -Mn ]...]]]
    Figure imgb0014

    in Beziehung steht, wobei jeder Mehrfachbit-Koeffizient Ci den vorbestimmten Bereich aufweist, der durch Ausschluß vorbestimmter der Binärcodes bestimmt ist.
  3. Abgriffskoeffizienteninkrementier-/Dekrementierverfahren nach Anspruch 2, bei dem jeder Mehrfachbit-Koeffizient Ci einen Hexadezimal-Binärcode aufweist, jeder Ci einen Ein-Bit-Vorzeichenteil Si und einen Drei-Bit-Schiebcodeteil Mi aufweist, und wobei jeder Mehrfachbit-Koeffizient Ci den die Hexadezimal-Werte umfassenden vorbestimmten Bereich aufweist, in dem vorbestimmte der Hexadezimal-Werte ausgeschlossen sind.
  4. Abgriffskoeffizienteninkrementier-/Dekrementierverfahren nach Anspruch 3, bei dem der C1-Koeffizient den Bereich aufweist, in dem alle sechzehn Hexadezimal-Werte in der vorbestimmten abnehmenden Ordnung 0, 1, 2, 3, 4, 5, 6, 7, F, E, D, C, B, A, 9 und 8 angeordnet sind;
    wobei C2 die Werte 0 und 1 nur annehmen kann, wenn C1=0 oder 8 ist.
  5. Abgrifskoeffizienteninkrementier-/Dekrementierverfahren nach Anspruch 2, bei dem der Schritt (b) ferner erfordert, daß, wenn sich der Vorzeichenteil des Mehrfachbit-Koeffizienten C1 ändert, sich der Richtungsanzeiger des Mehrfachbit-Koeffizienten C1+1 mit i=2, ...,n-1 ändert und daß, wenn sich der Vorzeichenteil des Richtungsanzeigers des höchstwertigen Mehrfachbit-Koeffizienten C1 ändert, sich alle Richtungsanzeiger der Mehrfachbit-Koeffizienten Ci mit i=2, ..., n ändern.
EP88304271A 1987-05-18 1988-05-11 Aufbesserung von kanonischen, mit Vorzeichenziffern behafteten Filterkoeffizienten Expired - Lifetime EP0292189B1 (de)

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AT88304271T ATE91831T1 (de) 1987-05-18 1988-05-11 Aufbesserung von kanonischen, mit vorzeichenziffern behafteten filterkoeffizienten.

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US5209187A 1987-05-18 1987-05-18
US52091 1987-05-18

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EP0292189A2 EP0292189A2 (de) 1988-11-23
EP0292189A3 EP0292189A3 (en) 1989-03-29
EP0292189B1 true EP0292189B1 (de) 1993-07-21

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5012245A (en) * 1989-10-04 1991-04-30 At&T Bell Laboratories Integral switched capacitor FIR filter/digital-to-analog converter for sigma-delta encoded digital audio
KR100248266B1 (ko) * 1994-03-07 2000-03-15 김영환 유한충격응답적응디지탈필터의 탭계수갱신장치
KR0139157B1 (ko) * 1994-09-07 1998-05-15 김광호 정준표시된 필터계수를 이용하는 고스트 제거장치
ES2225325T3 (es) 1995-09-19 2005-03-16 Daiwa Kasei Kogyo Kabushiki Kaisha Pata de retencion flexible para medios de sujecion.
KR100248021B1 (ko) * 1995-09-30 2000-03-15 윤종용 Csd 필터의 신호처리방법과 그 회로
DE19624382C1 (de) * 1996-06-19 1998-01-02 Bosch Gmbh Robert Klemmvorrichtung
US6108681A (en) * 1998-02-27 2000-08-22 Philips Electronics North America Corporation System for sharing resources in a digital filter
US6590931B1 (en) * 1999-12-09 2003-07-08 Koninklijke Philips Electronics N.V. Reconfigurable FIR filter using CSD coefficient representation
JP2003042112A (ja) * 2001-07-26 2003-02-13 Okamura Corp 止め具
CN102314215B (zh) * 2011-09-27 2014-03-12 西安电子科技大学 集成电路系统中小数乘法器的低功耗优化方法

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DE3882435D1 (de) 1993-08-26
EP0292189A2 (de) 1988-11-23
DE3882435T2 (de) 1994-01-27
ATE91831T1 (de) 1993-08-15
JPS6471210A (en) 1989-03-16
EP0292189A3 (en) 1989-03-29

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