EP0279225A3 - Reconfigurable counters for addressing in graphics display systems - Google Patents
Reconfigurable counters for addressing in graphics display systems Download PDFInfo
- Publication number
- EP0279225A3 EP0279225A3 EP19880101078 EP88101078A EP0279225A3 EP 0279225 A3 EP0279225 A3 EP 0279225A3 EP 19880101078 EP19880101078 EP 19880101078 EP 88101078 A EP88101078 A EP 88101078A EP 0279225 A3 EP0279225 A3 EP 0279225A3
- Authority
- EP
- European Patent Office
- Prior art keywords
- counter
- predetermined value
- graphics display
- value
- initial state
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/39—Control of the bit-mapped memory
- G09G5/393—Arrangements for updating the contents of the bit-mapped memory
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/18—Timing circuits for raster scan displays
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Multimedia (AREA)
- Image Generation (AREA)
- Controls And Circuits For Display Device (AREA)
Abstract
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/013,841 US4837563A (en) | 1987-02-12 | 1987-02-12 | Graphics display system function circuit |
US13841 | 1987-02-12 |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0279225A2 EP0279225A2 (en) | 1988-08-24 |
EP0279225A3 true EP0279225A3 (en) | 1991-04-17 |
EP0279225B1 EP0279225B1 (en) | 1994-04-27 |
Family
ID=21762055
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP88101078A Expired - Lifetime EP0279225B1 (en) | 1987-02-12 | 1988-01-26 | Reconfigurable counters for addressing in graphics display systems |
Country Status (5)
Country | Link |
---|---|
US (1) | US4837563A (en) |
EP (1) | EP0279225B1 (en) |
JP (1) | JPH0769969B2 (en) |
BR (1) | BR8800289A (en) |
DE (1) | DE3889240T2 (en) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5070465A (en) * | 1987-02-25 | 1991-12-03 | Sony Corporation | Video image transforming method and apparatus |
US5027291A (en) * | 1987-11-24 | 1991-06-25 | International Business Machines Corporation | Application exit for potentially pickable primitives in a graphics system |
JPH0679339B2 (en) * | 1988-04-11 | 1994-10-05 | 株式会社イーゼル | Image processing method |
US5367680A (en) * | 1990-02-13 | 1994-11-22 | International Business Machines Corporation | Rendering context manager for display adapters supporting multiple domains |
US5218674A (en) * | 1990-09-14 | 1993-06-08 | Hughes Aircraft Company | Hardware bit block transfer operator in a graphics rendering processor |
US5313576A (en) * | 1990-11-23 | 1994-05-17 | Network Computing Devices, Inc. | Bit aligned data block transfer method and apparatus |
US5345555A (en) * | 1990-11-23 | 1994-09-06 | Network Computing Devices, Inc. | Image processor memory for expediting memory operations |
US5293472A (en) * | 1991-04-22 | 1994-03-08 | International Business Machines Corporation | Method of generating lines and curves of user specified thicknesses on a raster device |
EP0623232B1 (en) * | 1992-01-21 | 1996-04-17 | Compaq Computer Corporation | Video graphics controller with improved calculation capabilities |
US5613053A (en) | 1992-01-21 | 1997-03-18 | Compaq Computer Corporation | Video graphics controller with automatic starting for line draws |
US5280571A (en) * | 1992-02-03 | 1994-01-18 | Intel Corporation | Method and apparatus for line drawing by interleaving multiple processors |
US5371518A (en) * | 1992-02-27 | 1994-12-06 | Silicon Graphics, Inc. | Video timing and display ID generator |
JP3210141B2 (en) * | 1993-06-24 | 2001-09-17 | 松下電器産業株式会社 | Straight line drawing device |
US5668941A (en) * | 1995-06-22 | 1997-09-16 | Cirrus Logic, Inc. | Optimum implementation of X-Y clipping on pixel boundary |
KR100207541B1 (en) * | 1996-12-30 | 1999-07-15 | 윤종용 | Device and method for the digital video rom disc interface |
US5929872A (en) * | 1997-03-21 | 1999-07-27 | Alliance Semiconductor Corporation | Method and apparatus for multiple compositing of source data in a graphics display processor |
US6830196B1 (en) * | 1999-05-25 | 2004-12-14 | Silverbrook Research Pty Ltd | Identity-coded surface region |
CN100423081C (en) * | 2004-12-03 | 2008-10-01 | 深圳迈瑞生物医疗电子股份有限公司 | Hardware acceleration display horizontal line section device and method |
US8854383B2 (en) * | 2011-04-13 | 2014-10-07 | Qualcomm Incorporated | Pixel value compaction for graphics processing |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3764790A (en) * | 1972-03-30 | 1973-10-09 | Nasa | Technique for extending the frequency range of digital dividers |
US4272808A (en) * | 1979-05-21 | 1981-06-09 | Sperry Corporation | Digital graphics generation system |
EP0095777A2 (en) * | 1982-05-31 | 1983-12-07 | Kabushiki Kaisha Toshiba | Programmable counter system |
WO1984004832A1 (en) * | 1983-05-25 | 1984-12-06 | Ramtek Corp | Vector attribute generating method and apparatus |
FR2574575A1 (en) * | 1984-12-11 | 1986-06-13 | O Donnell Ciaran | VECTOR TRACE PROCESSOR |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4458330A (en) * | 1981-05-13 | 1984-07-03 | Intergraph Corporation | Banded vector to raster converter |
JPS58205276A (en) * | 1982-05-26 | 1983-11-30 | Hitachi Ltd | Graphic processor |
JPS59149526A (en) * | 1983-01-28 | 1984-08-27 | Fujitsu Ltd | Intra-field document editing processor |
EP0130247B1 (en) * | 1983-06-30 | 1987-03-04 | International Business Machines Corporation | Programmable timing circuit for cathode ray tube |
US4667306A (en) * | 1983-07-20 | 1987-05-19 | Ramtek Corporation | Method and apparatus for generating surface-fill vectors |
JPS6073682A (en) * | 1983-09-30 | 1985-04-25 | 株式会社東芝 | Data transfer system within graphic memory |
US4626839A (en) * | 1983-11-15 | 1986-12-02 | Motorola Inc. | Programmable video display generator |
US4644503A (en) * | 1983-12-30 | 1987-02-17 | International Business Machines Corporation | Computer memory system with integrated parallel shift circuits |
JPS619762A (en) * | 1984-06-25 | 1986-01-17 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Image processor |
JPS6211970A (en) * | 1985-07-09 | 1987-01-20 | Nec Corp | Address generating circuit |
-
1987
- 1987-02-12 US US07/013,841 patent/US4837563A/en not_active Expired - Fee Related
-
1988
- 1988-01-12 JP JP63003277A patent/JPH0769969B2/en not_active Expired - Lifetime
- 1988-01-26 BR BR8800289A patent/BR8800289A/en unknown
- 1988-01-26 DE DE3889240T patent/DE3889240T2/en not_active Expired - Fee Related
- 1988-01-26 EP EP88101078A patent/EP0279225B1/en not_active Expired - Lifetime
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3764790A (en) * | 1972-03-30 | 1973-10-09 | Nasa | Technique for extending the frequency range of digital dividers |
US4272808A (en) * | 1979-05-21 | 1981-06-09 | Sperry Corporation | Digital graphics generation system |
EP0095777A2 (en) * | 1982-05-31 | 1983-12-07 | Kabushiki Kaisha Toshiba | Programmable counter system |
WO1984004832A1 (en) * | 1983-05-25 | 1984-12-06 | Ramtek Corp | Vector attribute generating method and apparatus |
FR2574575A1 (en) * | 1984-12-11 | 1986-06-13 | O Donnell Ciaran | VECTOR TRACE PROCESSOR |
Also Published As
Publication number | Publication date |
---|---|
US4837563A (en) | 1989-06-06 |
JPS63201790A (en) | 1988-08-19 |
BR8800289A (en) | 1988-09-06 |
EP0279225A2 (en) | 1988-08-24 |
DE3889240T2 (en) | 1994-11-24 |
EP0279225B1 (en) | 1994-04-27 |
DE3889240D1 (en) | 1994-06-01 |
JPH0769969B2 (en) | 1995-07-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0279225A3 (en) | Reconfigurable counters for addressing in graphics display systems | |
EP0071747B1 (en) | Self-pacing serial keyboard interface for data processing system | |
US5027330A (en) | FIFO memory arrangement including a memory location fill indication | |
IE822859L (en) | Multi processing interupt arrangement | |
CA2112001A1 (en) | Universal Protocol Programmable Communications Interface | |
WO2002050700A3 (en) | Processor architecture | |
DE3065585D1 (en) | Data processing system comprising a common bus communication system in which the width of the address field is greater than the number of lines on the bus | |
EP0267612A3 (en) | Timer/counter using a register block | |
CA2007690A1 (en) | High speed bus with virtual memory data transfer capability | |
CA2026737A1 (en) | Bus master interface circuit with transparent preemption of a data transfer controller | |
US5640570A (en) | Information handling system for transmitting contents of line register from asynchronous controller to shadow register in another asynchronous controller determined by shadow register address buffer | |
US6289421B1 (en) | Intelligent memory devices for transferring data between electronic devices | |
CA2163850A1 (en) | Bus Arbitration Between an Input/Output Device and a Processing Device Including a First-In First-Out Type Write-In Buffer | |
EP0334103A3 (en) | Data processing unit having a bypass circuit | |
JPS55154851A (en) | Data transmission system | |
KR20030033005A (en) | A circuit arrangement and method for improving data management in a data communications circuit | |
EP0299264A2 (en) | A byte queing/dequeuing apparatus for handling variable-length data words/instructions in a single clock cycle | |
JP2966435B2 (en) | Preset counter | |
JPS5487148A (en) | Data processing system by multiplex processor | |
JPS60180245A (en) | Priority transmission system | |
JPS61236094A (en) | Serial data input memory | |
JPS6277666A (en) | Buffer circuit | |
JPH0313038A (en) | Asynchronous serial data transmitter | |
JPS63113750A (en) | Information processing system | |
FR2551218B1 (en) | METHOD FOR DETERMINING A SPEED AND DEVICE FOR IMPLEMENTING IT |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): DE FR GB IT |
|
17P | Request for examination filed |
Effective date: 19881130 |
|
PUAL | Search report despatched |
Free format text: ORIGINAL CODE: 0009013 |
|
AK | Designated contracting states |
Kind code of ref document: A3 Designated state(s): DE FR GB IT |
|
17Q | First examination report despatched |
Effective date: 19920922 |
|
GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): DE FR GB IT |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRE;WARNING: LAPSES OF ITALIAN PATENTS WITH EFFECTIVE DATE BEFORE 2007 MAY HAVE OCCURRED AT ANY TIME BEFORE 2007. THE CORRECT EFFECTIVE DATE MAY BE DIFFERENT FROM THE ONE RECORDED.SCRIBED TIME-LIMIT Effective date: 19940427 |
|
REF | Corresponds to: |
Ref document number: 3889240 Country of ref document: DE Date of ref document: 19940601 |
|
ET | Fr: translation filed | ||
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: GB Payment date: 19941220 Year of fee payment: 8 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: FR Payment date: 19941223 Year of fee payment: 8 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: DE Payment date: 19950117 Year of fee payment: 8 |
|
PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
26N | No opposition filed | ||
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: GB Effective date: 19960126 |
|
GBPC | Gb: european patent ceased through non-payment of renewal fee |
Effective date: 19960126 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: FR Effective date: 19960930 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: DE Effective date: 19961001 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: ST |