EP0279225A3 - Reconfigurable counters for addressing in graphics display systems - Google Patents

Reconfigurable counters for addressing in graphics display systems Download PDF

Info

Publication number
EP0279225A3
EP0279225A3 EP19880101078 EP88101078A EP0279225A3 EP 0279225 A3 EP0279225 A3 EP 0279225A3 EP 19880101078 EP19880101078 EP 19880101078 EP 88101078 A EP88101078 A EP 88101078A EP 0279225 A3 EP0279225 A3 EP 0279225A3
Authority
EP
European Patent Office
Prior art keywords
counter
predetermined value
graphics display
value
initial state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP19880101078
Other languages
German (de)
French (fr)
Other versions
EP0279225A2 (en
EP0279225B1 (en
Inventor
Robert Lockwood Mansfield
Alexander Koos Spencer
Joe Christopher St. Clair
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of EP0279225A2 publication Critical patent/EP0279225A2/en
Publication of EP0279225A3 publication Critical patent/EP0279225A3/en
Application granted granted Critical
Publication of EP0279225B1 publication Critical patent/EP0279225B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/18—Timing circuits for raster scan displays

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Multimedia (AREA)
  • Image Generation (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

In a graphics display system a counter for performing either a line drawing algorithm or a bit block transfer algorithm where the counter in performing the bit block transfer algorithm includes a first counter circuit counting from a first initial state to a second predetermined value and a second counter circuit counting from a second initial state to a second predetermined value. The second counter counts in response to the first counter reaching to its predetermined value. In support of a line drawing algorithm, the counter circuit reconfigures itself to provide a first counter to count from its first initial state to the first predetermined value and a second counter to compute a parameter value and to conditionally count from a second initial value to a second predetermined value in response to the value of this parameter. These counters are connected to an addressing circuit to increment the addresses in performance of the algorithms. This counter circuit capability increases the speed at which line draw functions and bit block transfer functions can be accomplished in a graphics display system processor.
EP88101078A 1987-02-12 1988-01-26 Reconfigurable counters for addressing in graphics display systems Expired - Lifetime EP0279225B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/013,841 US4837563A (en) 1987-02-12 1987-02-12 Graphics display system function circuit
US13841 1987-02-12

Publications (3)

Publication Number Publication Date
EP0279225A2 EP0279225A2 (en) 1988-08-24
EP0279225A3 true EP0279225A3 (en) 1991-04-17
EP0279225B1 EP0279225B1 (en) 1994-04-27

Family

ID=21762055

Family Applications (1)

Application Number Title Priority Date Filing Date
EP88101078A Expired - Lifetime EP0279225B1 (en) 1987-02-12 1988-01-26 Reconfigurable counters for addressing in graphics display systems

Country Status (5)

Country Link
US (1) US4837563A (en)
EP (1) EP0279225B1 (en)
JP (1) JPH0769969B2 (en)
BR (1) BR8800289A (en)
DE (1) DE3889240T2 (en)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5070465A (en) * 1987-02-25 1991-12-03 Sony Corporation Video image transforming method and apparatus
US5027291A (en) * 1987-11-24 1991-06-25 International Business Machines Corporation Application exit for potentially pickable primitives in a graphics system
JPH0679339B2 (en) * 1988-04-11 1994-10-05 株式会社イーゼル Image processing method
US5367680A (en) * 1990-02-13 1994-11-22 International Business Machines Corporation Rendering context manager for display adapters supporting multiple domains
US5218674A (en) * 1990-09-14 1993-06-08 Hughes Aircraft Company Hardware bit block transfer operator in a graphics rendering processor
US5313576A (en) * 1990-11-23 1994-05-17 Network Computing Devices, Inc. Bit aligned data block transfer method and apparatus
US5345555A (en) * 1990-11-23 1994-09-06 Network Computing Devices, Inc. Image processor memory for expediting memory operations
US5293472A (en) * 1991-04-22 1994-03-08 International Business Machines Corporation Method of generating lines and curves of user specified thicknesses on a raster device
EP0623232B1 (en) * 1992-01-21 1996-04-17 Compaq Computer Corporation Video graphics controller with improved calculation capabilities
US5613053A (en) 1992-01-21 1997-03-18 Compaq Computer Corporation Video graphics controller with automatic starting for line draws
US5280571A (en) * 1992-02-03 1994-01-18 Intel Corporation Method and apparatus for line drawing by interleaving multiple processors
US5371518A (en) * 1992-02-27 1994-12-06 Silicon Graphics, Inc. Video timing and display ID generator
JP3210141B2 (en) * 1993-06-24 2001-09-17 松下電器産業株式会社 Straight line drawing device
US5668941A (en) * 1995-06-22 1997-09-16 Cirrus Logic, Inc. Optimum implementation of X-Y clipping on pixel boundary
KR100207541B1 (en) * 1996-12-30 1999-07-15 윤종용 Device and method for the digital video rom disc interface
US5929872A (en) * 1997-03-21 1999-07-27 Alliance Semiconductor Corporation Method and apparatus for multiple compositing of source data in a graphics display processor
US6830196B1 (en) * 1999-05-25 2004-12-14 Silverbrook Research Pty Ltd Identity-coded surface region
CN100423081C (en) * 2004-12-03 2008-10-01 深圳迈瑞生物医疗电子股份有限公司 Hardware acceleration display horizontal line section device and method
US8854383B2 (en) * 2011-04-13 2014-10-07 Qualcomm Incorporated Pixel value compaction for graphics processing

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3764790A (en) * 1972-03-30 1973-10-09 Nasa Technique for extending the frequency range of digital dividers
US4272808A (en) * 1979-05-21 1981-06-09 Sperry Corporation Digital graphics generation system
EP0095777A2 (en) * 1982-05-31 1983-12-07 Kabushiki Kaisha Toshiba Programmable counter system
WO1984004832A1 (en) * 1983-05-25 1984-12-06 Ramtek Corp Vector attribute generating method and apparatus
FR2574575A1 (en) * 1984-12-11 1986-06-13 O Donnell Ciaran VECTOR TRACE PROCESSOR

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4458330A (en) * 1981-05-13 1984-07-03 Intergraph Corporation Banded vector to raster converter
JPS58205276A (en) * 1982-05-26 1983-11-30 Hitachi Ltd Graphic processor
JPS59149526A (en) * 1983-01-28 1984-08-27 Fujitsu Ltd Intra-field document editing processor
EP0130247B1 (en) * 1983-06-30 1987-03-04 International Business Machines Corporation Programmable timing circuit for cathode ray tube
US4667306A (en) * 1983-07-20 1987-05-19 Ramtek Corporation Method and apparatus for generating surface-fill vectors
JPS6073682A (en) * 1983-09-30 1985-04-25 株式会社東芝 Data transfer system within graphic memory
US4626839A (en) * 1983-11-15 1986-12-02 Motorola Inc. Programmable video display generator
US4644503A (en) * 1983-12-30 1987-02-17 International Business Machines Corporation Computer memory system with integrated parallel shift circuits
JPS619762A (en) * 1984-06-25 1986-01-17 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Image processor
JPS6211970A (en) * 1985-07-09 1987-01-20 Nec Corp Address generating circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3764790A (en) * 1972-03-30 1973-10-09 Nasa Technique for extending the frequency range of digital dividers
US4272808A (en) * 1979-05-21 1981-06-09 Sperry Corporation Digital graphics generation system
EP0095777A2 (en) * 1982-05-31 1983-12-07 Kabushiki Kaisha Toshiba Programmable counter system
WO1984004832A1 (en) * 1983-05-25 1984-12-06 Ramtek Corp Vector attribute generating method and apparatus
FR2574575A1 (en) * 1984-12-11 1986-06-13 O Donnell Ciaran VECTOR TRACE PROCESSOR

Also Published As

Publication number Publication date
US4837563A (en) 1989-06-06
JPS63201790A (en) 1988-08-19
BR8800289A (en) 1988-09-06
EP0279225A2 (en) 1988-08-24
DE3889240T2 (en) 1994-11-24
EP0279225B1 (en) 1994-04-27
DE3889240D1 (en) 1994-06-01
JPH0769969B2 (en) 1995-07-31

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