EP0277952A1 - Procede et dispositif pour determiner la vitesse de transmission de donnees et la distorsion de signaux de lignes de transmission de donnees serielles synchrones et asynchrones - Google Patents

Procede et dispositif pour determiner la vitesse de transmission de donnees et la distorsion de signaux de lignes de transmission de donnees serielles synchrones et asynchrones

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Publication number
EP0277952A1
EP0277952A1 EP19870900248 EP87900248A EP0277952A1 EP 0277952 A1 EP0277952 A1 EP 0277952A1 EP 19870900248 EP19870900248 EP 19870900248 EP 87900248 A EP87900248 A EP 87900248A EP 0277952 A1 EP0277952 A1 EP 0277952A1
Authority
EP
European Patent Office
Prior art keywords
input
line
circuit
group
outputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19870900248
Other languages
German (de)
English (en)
Inventor
Csaba Dani
László HUNYA
József HUNYADI
László KÖVESHEGYI
István MAYER
Endre Szebenyi
Zoltán SZEMEREKI
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MTA KOEZPONTI FIZIKAI KUTATO INTEZETE
Magyar Tudomanyos Akademia Kozponti Fizikai Kutato Intezet
Original Assignee
MTA KOEZPONTI FIZIKAI KUTATO INTEZETE
Magyar Tudomanyos Akademia Kozponti Fizikai Kutato Intezet
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Filing date
Publication date
Application filed by MTA KOEZPONTI FIZIKAI KUTATO INTEZETE, Magyar Tudomanyos Akademia Kozponti Fizikai Kutato Intezet filed Critical MTA KOEZPONTI FIZIKAI KUTATO INTEZETE
Publication of EP0277952A1 publication Critical patent/EP0277952A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/24—Testing correct operation
    • H04L1/248—Distortion measuring systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector

Definitions

  • Subject of the invention is a procedure and a device to determine any or both of data tras,ission rate and signal distortion of serial data transmission lines.
  • data processing equipment which may be for example a line multiplexer, a front-end processor, an intelligent line switching and data processing system, etc) receiving and pre-processing input data be able to carry out baud rate and/or protocol-conversion and transmit data to a central processing unit, be suitable for monitoring input SERiAL DATA AND PROVIDING INFORMATION ON DATA TRANSMISSION rate and distortion (jitter, skew).
  • Characteristic of known solutions and equipment is that data transmission rate and signal distortion is measured and determined by two different circuits or devices, being independent of each other, and because known circuits for determining signal distortion are relatively complicated, in most cases distortion will only be measured, if it is absolultely indispensable. The main point of the known methods for .
  • determining data transmission rate of an asynchronous serial data stream is that the length of the START bit of the first (or the first two) transmitted characters (that is the time interval extending from the leading edge of the START bit until the next strailing edge in the serial data stream) is determined, and from this value, taken as a unity bit time, can be concluded on the actual data rate.
  • Data rate calculated in such a way, is regarded as valid here ⁇ after for the whole data transmission.
  • the first (first two) character, to be sent out at the beginning of the data stream cannot be chosen arbitrarily,, in most cases only "' _ a Carriage Return is allowed. Namely, if the value of the LSB bit (the first data bit after START in the serial bit stream) of the character being examined is not a logical "1", the first signal change will not occur in a unity bit time interval after the leading edge of the START bit, hence the above measurement will result in an erroneous value.
  • the exact value of the length of the START bit determined by using the above method depends on the signal distortion, and therefore it should be rounded (that is: corrected), the information gained in such a way is not enough to determine the exact value of the signal distortion.
  • the following known method is applied.
  • the distorted signal is regenerated, then the regenerated and the distorted signal is sampled in several moments in time, these moments being measured relative to the beginning of the regenerated signal in terms of the percental value of the bit time. Corresponding pairs of sampled values are compared and the time moments are searched, at which the two corresponding samples differ from each other.
  • the per ⁇ centage values determined in such a way are considered as char ⁇ acteristic of the signal distortion.
  • the method necessarily implies signal regeneration, which may only be realized by a relatively complicated circuit itself;
  • the aim of the invention is to develop a device, which
  • the measured values can be read out and evaluated in any phase (that is: not only at the beginning) of the data transmission; - with respect to measuring data rate, imposes no constraints, or at least far less contraints on the transmitted characters to be measured;
  • the basis of the invention is the perception, that the task can easily he solved, if bit time minimum and bit time maximum values are continuously and concurrently measured and determined in the course of the whole data transmission.
  • the procedure according to the invention is an improvement of a known procedure in the course of which at first signal changes are indicated, then the time interval between two suc . ces.ive signal ch aredeterrnined and stored.
  • the improvement lies in that saidtime intervals are continuously measured and the time interval measured between the last two con ⁇ sidered signal changes is compared with • a . previously stored minimu value, and at the same time with a minimum limit postulated and * stored beforehand; the value of time interval just measured will only be stored as a new minimum value, if it is less than the previously stored one, but at the same time it is greater than the postulated minimum limit (in this case the previously stored optionally minimum value will be lost) ; and.
  • the invented device is an improvement of a known device, which comprises a control unit, an address decoder unit, a baud-rate detector unit and a first gating unit, all of them connected to a group of central lines.
  • the device also includes a second gating unit, and instead of a baud- rate detector unit, it comp ⁇ rises a baud-rate and signal distortion detector unit.
  • the inputs of said baud-rate and signal distortion detector unit are con- — nected via a first addressing line and via a second addressing line to respective outputs of said address decoder unit, another input via a third addressing line to a further output of said address decoder unit and to an input of said first gating unit, a further input via a fourth addressing line to a further output of said address decoder unit and to an input of said second gatin unit, further inputs of it to a group of input data lines consti ⁇ tuting the input of the device, the remaining inputs via a group of writing lines being a subset of a group of central lines to th inputs outputs of said control unit; the outputs of said baud- rate and signal distortion detector unit via first bunch of data lines to further inputs of said first g
  • the baud-rate and signal distortion detector unit suitably comprises a time marker circuit, a counter, a minimum limit register, a maximum limit register, a first comparator circuit, a second comparator circuit, a third compa ⁇ rator circuit, a fourth comparator circuit, a first gating circuit, a limited minimum register, a second gating circuit and a limited maximum register.
  • Inputs of said time marker circuit are connected to a group of input data lines, another input of said circuit is connected via a third transit line to an input of said first gating circuit and to the output of said first comparator circuit.
  • the outputs of said time marker circuit are applied via an enabler line to an input of said counter, via a reset line to another input of said counter, via a write line to an input of said first gating circuit and to an input of said second gating circuit, respectively.
  • a further input of said counter is connected to a synchronizer line, constituting part of a group of central lines.
  • the outputs of said counter are applied via a group of internal data lines to inputs of said first, second, third and fourth comparator circuits, furthermore to inputs of said limited minimum register and to those of said limited maximum register.
  • the inputs of said minimum limit register are connected partly to a first addressing line, partly, via a group of data lines, being a subset of a group of central lines to inputs of said maximum limit register.
  • the outputs of said minimum limit register is applied via a first group of transit lines to further inputs of said first comparator circuit.
  • a further input of said maximum limit register is con ⁇ nected to a second addressing line, its outputs are applied via a second group of transit lines to further inputs of said second comparator circuit.
  • a further input of said first gating circuit is applied via a fifth transit line to the output of said third comparator circuit, its output is connected via a first transit line to a further input of said limited minimum register.
  • Further input of said limited minimum register is connected to a third addressing line, its outputs are connected via a first bunch of* data lines to further inputs of said third comparator circuit.
  • Furthe inputs of said second gating circuit are connected via a fourth trans line to the output of said second comparator circuit, and via a sixt transit line to the output of said fourth comparator circuit respecti
  • the output of said second gating circuit is applied via a second transit line to an input of said limited maximum register.
  • a further input of said limited maximum register is connected to a fourth addressing line, its outputs are connected to a second bunch of data lines, and via the second bunch of data lines to further inputs of said fourth comparator circuit.
  • said time marker circuit is suitably a signal change indicator circuit, consisting of edge-triggered onostable multi ⁇ vibrators .
  • said time marker circuit includes a first signal change indicator circuit, a second signal change indicator circuit and a storage.
  • the input of said first signal change indicator circuit comes from a first input data line, being part of said group of input data lines, its output is applied via a transit data line to the input of said storage.
  • the input of said second signal change indicator circuit is connected to a second input data line, also being part of said group of input data lines, the outputs of said second signal change indicator circuit is partly connected via said reset line to a further input of said storage, partly to said write line, respectively.
  • the output of said storage is applied to said enabler line.
  • said time marker circuit comprises a signal change and start/stop bit indicator circuit and a bistable multi ⁇ vibrator.
  • the input of said signal change and start/stop bit indicator circu is connected to an input data line, being part of said group of input data lines, its outputs are connected partly via a reset line to an input of said bistable multivibrator, partly via a stop signal line to another input of said bistable multivibrator, and partly to said write line, respectively.
  • the output of said bistable multivibrator is connected to said enabler line.
  • said time marker circuit comprising a signal change and start bit indicator circuit, a bistable multi ⁇ vibrator circuit and an AND gate.
  • the input of said signal change and start bit indicator circuit is connected to said input data line, being part of said group of input data lines, the outputs are connected partly to said reset line and via said reset line to an input of said bistable multi ⁇ vibrator circuit, partly to said write line and via said write line to an input of said AND gate.
  • Another input of said AND gate comes from said third transit line, its output is connected via a stopping line to another input of said bistable multivibrator circuit.
  • the output of said bistable multivibrator circuit is connected to said enabler line.
  • fig. 1 is a flowchart, illustrating the invented procedure
  • fig. 2 is a block diagram, illustrating the known and invented device
  • fig. 3 is a block diagram illustrating possible embodiments of said baud-rate and signal distortion detector circuit
  • fig. 4 is a block diagram, illustrating a possible embodiment of said time marker circuit
  • fig. 5 is a block diagram, illustrating another possible embodiment of said time marker circuit
  • fig. 6 is a block diagram, illustrating a further possible embodiment of said time marker circuit.
  • first time interval Tl in which the maximum value that theoretically can be stored is taken and stored as the minimum value, and furthermore, the value of the minimum limit is defined and stored.
  • First time interval Tl is then followed by second time interval T2, in which the minimum value, that theoretically can be stored is taken and stored as the maximum value, and furthermore, the value of the maximum limit is defined and stored.
  • Second time interval T2 is followed by third time interval T3, in which time measuring (counting) is stopped and time value is set to zero.
  • Third time interval T3 is followed by first time moment t, .
  • first time moment t it is decided, if on the considered input line a logical signal change has occured, or not. If it has, first time moment t, is followed by second time moment t-,,if not, first time moment t, follo again.
  • second time moment t- it is decided, if time has to be measured continously (bit-by-bit, that is: between every con ⁇ secutive signal change or by sections (that is: between given peculiar signal changes, regerded as start and stop signal edges, ignoring any other signal changes between them) . If time is to be measured by sections, second time moment t.- is followed by third time moment 3 ; if time has to be measured continously, second time moment t ⁇ is followed by fourth time interval T4.
  • third time moment t_- it is invenstigated, if signal change, detected at first time moment t, is to be regarded as a start signal edge (for example, a leading edge of the START bit" of an asynchronous serial character, detected by a START-bit indicator circuit, see fig. 5 and 6) , or not. If it is a start signal edge, third time moment t, is followed by fourth time interval T4, otherwise it is followed by first time moment t,. In fourth time interval T4 previous time value is cleared (that is: time is set to zero) . Fourth time interval T4 is then followed by fifth time interval T5. In time interval T5 time measuring (time counting) is started, T5 is then followed by fourth time moment t ⁇ .
  • a start signal edge for example, a leading edge of the START bit" of an asynchronous serial character, detected by a START-bit indicator circuit, see fig. 5 and 6
  • start signal edge for example, a leading edge of the START bit of an asynchronous serial character
  • fourth time moment t it is investigated, if on the considered input line (since the last invenstigation) a logical signal change has occured or not. If it has, t . is followed by fifth time moment _ _ , otherwise fourth time moment t, follows again.
  • t_ it is invenstigated, if time has to be measured continously or by sections. If time is to be measured continously, t j - is followed by seventh time moment _- , if it has to be measured by sections, sixth time moment t, follows.
  • sixth time moment t fi it is investigated, if the signal change, detected at fourth time moment t ⁇ / is a stoo signal edge, or not.
  • sixth time moment t is followed by sixth time interval T6; otherwise it is followed by seventh time interval T7.
  • sixth time interval T6 it is stored (memorized) , that the last signal change was a stop signal edge.
  • T6 is followed by seventh time moment t ⁇ .
  • the seventh time interval T7 it is stored (memorized) , that the last signal change was not a stop signal edge.
  • T7 is also followed by seventh time moment t- .
  • time moment t 7 it is examined, whether the time value, measured (counted) until the last signal change, is greater than value of the minimum limit, defined and stored in first time interval Tl. If it is, t., is followed by eighth time moment t culinary; if it is not, t-. is followed by ninth time moment t g . In eighth time moment t g it is examined, whether the time value measured (counted) until the last signal change is less than the minimum value stored previously. If it is, t R is followed by eighth time interval T8, if it is not, ninth time moment t-. follows. In eighth time interval T8 the time value being just measured is stored as the actual minimum value
  • T8 is followed by ninth time moment t Q , at which it is examined, whether the time value, measured (counted) until the last signal change is less than value of the maximum limit, defined and stored in second time interval T2. If it is, tgue is followed by tenth time moment tlO, if not, it is followed by eleventh time moment til. At tenth time moment tlO, it is examined, if time value measured until the last signal change is greater than the previously stored maximum value. If it is, t, Q is followed by ninth time interval T9, if it is not, it is followed by eleventh time moment t, , .
  • time interval T9 the time value being just measured is stored as the actual maximum value (the value being stored before is lost)
  • T9 is followed by eleventh time moment t, , .
  • eleventh time moment t it is examined once more, if time has to be measured continously or by sections. If it is to be measured continously, t, is followed by tenth time interval TlO, if it has to be measured by sections, twelfth time moment t, - follows.
  • TlO actual time value is set to zero, however time measuring (counting) is not stopped.
  • TlO is then followed by fourth time moment t, again.
  • twelfth time moment t - it is examined, whether the last signal change was a stop signal edge
  • the operation of a known baud-rate detection device will be explained with reference to fig. 2.
  • the device comprises a control unit 11, an address decoder unit 13, a baud-rate detector unit 12 and a first gating unit 14.
  • An input of said baud-rate detector unit 12 are connected via first address ⁇ ing line b to the output of said address decoder unit 13. Further inputs of said baud-rate detector unit is connected to a group E of input data lines, constituting the input of the device-, its outputs are applied via a first bunch E of input data liens to the inputs of said first gating unit 14.
  • a further input of said first gating unit 14 is connected via a third addressing line e to a further output of said address decoder unit 13, the outputs of said first gating unit 14 are applied via a group B of reading liens constituting a subset of a group A of central lines to inputs/outputs of control unit 11.
  • the inputs of said address decoder unit 13 are connected to a group D of address and central lines, being a subset of a group A of central lines, and being connected to inputs/outputs of control unit 11.
  • Said baud-rate detector unit 12 receives via a group E of input " data lines a serial input data stream (that is: a series of input signal pulses) .
  • a serial input data stream that is: a series of input signal pulses
  • said baud-rate detector unit 12 receives a pulse via said first addressing line b (this pulse is generated by said address decoder unit 13 if so instructed by said control unit 11 via said group A of central lines)
  • said baud rate detector unit 12 generates a binary value being characteristic of the time interval between two consecutive signal changes just appearing on an appropriate line of said group E of input data lines.
  • This value being characteristic of said time interval (which in turn, on certain afore-mentioned conditions characterizes transmission rate of the serial input data stream) , appears on outputs of said baud-rate detector unit 12, and in such a way, on said first bunch F of data lines.
  • This value is then gated by said first gating unit 14 onto said group A of central lines, when a pulse is generated onto said third addressing line e by said address decoder unit 13.
  • Data appearing on said group A of central lines may then be processed by said control unit 11.
  • the invented device will also be explained with reference to fig.2.
  • the device according to the invention differs from that of the known solution in that it* also includes a second gating unit 15, and instead of a baud-rate detector unit, it comprises a baud- rate and signal distortion detector unit 12.
  • the inputs of said baud-rate and signal distortion detector unit 12 are connected via a first addressing line b and via a second addressing line d to respective outputs of said address decoder unit 13, another inp of it via a third addressing line e to a further output of said address decoder unit 13 and to an input of said first gating unit 14, a further input via a fourth addressing line f to a further output of said address decoder unit 13 and to an input of said second gating unit 15, further inputs of said baud-rate and signal distortion detector unit 12 to a group E of input data lines constituting the input of the device; the remaining inputs of it via a group C of writing lines being a subset of said group A of central lines to inputs/outputs of said control unit
  • the invented device determines in the course of a periodically repeated measuring procedure the limited minimum and the limited maximum of time intervals between two signal changes (these two signal changes arriving not necessarily on the same input line, and one signal change not necessarily being immediately followed by the other) .
  • These two values ie. limited minimum and maximum
  • the jitter of signal edges being at various bit distances relative to the given start signal edges can be examined and determined, if measuring is carried out by sections (see description of fig.l Infeo this case, said minimum/maximum limit value has to be suitabl defined according to a relative time position being a half bit time less/greater than the probable position of the signal edge (for example the leading edge of the STOP-bit) to be examined. If measuring is to be made continously, said minimum/maximum limit value is to be chosen according to 0, _, 5 theoretical bit time.
  • Transmission rate can be calculated on the basis of the measured minimum value. Thereafter, either continuous or sectioned measurin mode can be selected, and signal distortion can be measured and calculated as described above.
  • said minimum and maximum limit values can programmably be loaded into said baud-rate and signal distortion detector unit 12, via said group C of writing lines. If a signal is generated by said address decoder unit 13 onto said first addressing line b, said minimum limit value will be loaded, and so it w 11 be equal with data being present on said group C of writing lines.
  • Said baud-rate and signal distortion detector unit 12 comprises a time marker circuit 16, a counter 17, a minimum limit register a maximum limit register 19, a first comparator circuit 20, a second comparator circuit 21, a third comparator circuit 22, a fourth comparator circuit 23, a first gating circuit 24, a restrictive minimum register 25, a second gating circuit 26 and a limited maximum register 27.
  • the inputs of said time marker circuit 16 are connected to a group E of input data lines, another input of it is connected via a third transit line t to an input of said first gating circuit 16 and to the output of said first comparator circuit 20.
  • the outputs of said time marker circuit 16 are applied via an enabler line i to an input of said counter 17, via a reset line s to another input of said counter 17, via a write line h to anothe input of said first gating circuit 24 and to an input of said second gating circuit 26, respectively.
  • a further input of said counter 17 is connected to a synchronizer line g, constituting part of a group A of central lines.
  • the outputs of said counter 17 are applied via a group H of internal data lines to inputs of said first, second, third and fourth comparator circuit (20, 21, 22, 23) , furthermore to inputs of said limited minimum reg ⁇ ister 25 and to those of said limited maximum register 27.
  • the inputs' of said minimum limit register 18 are connected partly to a first addressing line b, partly, via a group Q of data lines being a subset of a group A of central lines to inputs of said maximum limit register 19.
  • the outputs of said minimum limit register 18 are applied via a first group J of transit lines to further inputs of said first comparator circuit 20.
  • a further input of said maximum limit register 19 is connected to a second addressing line d, its outputs are applied via a second group K of transit lines to further inputs of said second comparator circuit 21.
  • a further input of said first gating circuit 24 is applied via a fifth transit line v to the output of said third comparator circuit 22, its output is connected via a first transit line k to a further input of said limited minimum register 25.
  • Further input of said limited minimum register 25 is connected to a third addressing line, its outputs are connected via a first bunch F of data lines to further inputs of said third comparator circuit 22. Further inputs of said second gating circuit 26 are connected via a fourth transit line u to the output of said second comparator circuit 21, and via a sixth transit line y to the output of said fourth comparator circuit 23, respectively. The output of said second gating circuit 26 is applied via a second transit line m to an input of said limited maximum register 27. A further input of said limited maximum register 27 is connected to a fourth addressing line f, its outputs are connected to a second bunch G of data lines, and via second bunch G of data lines to further inputs of said fourth comparator circuit 23.
  • Said minimum limit register 18 will be loaded with data being present on group Q of data lines by a pulse arriving on first addressing line b. Data being stored in such a way in said minimum limit register 18 (that is: the actual minimum limit) appears on its outputs, that is on said first group J of transit lines, and on inputs of said first comparator circuit 20. Said maximum limit register 19 will be loaded in a similar way with data being present on group Q of data lines by a pulse arriving on second addressing line d. Data being stored in such a way in said maximum limit register 19 appears on its outputs, that * is on said second group K of transit lines, and will also be present on inputs of said second comparator circuit 21.
  • said time marker circuit 16 will generate pulses on its outputs, and these pulses will reach via said enabler line i and reset line s the inputs of said counter 17, and via said write lines h the inputs of said first gating circuit 24 and second gating circuit 26.
  • said counter 17 When a pulse arrives on said reset lin said counter 17 will be cleared (set to zero) , and as an effect of a pulse applied to said enabler line i; said counter 17 will be enabled, that is, in its enabled state, contents of said counter 17 will be incremented (the counter will count up) when ⁇ ever a pulse arrives on said synchronizer line g.
  • Said first comparator circuit 20 will generate a logical 1 state on its output, if the value being present on outputs of said counter 17 is greater than that of the outputs of said minimum limit reg ⁇ ister 18.
  • said second comparator circuit 21 will show a logical 1 state on its output, whenever value on outputs of said counter 17 is less than value on outputs of said maximum limit register 19.
  • Said minimum limit register 25 holds always the previously stored limited minimum value, and in a similar way said limited maximum register 27 contains the limited maximum value previously stored.
  • Said third comparator circuit 22 will present on its output a logical 1 level, when ⁇ ever value on outputs of said counter 17 is less than the previous stored limited minimum value, represented by the outputs of said limited minimum register 25.
  • Value on output of said fourth comparator circuit 23 will be a logical 1, every time the value represented by outputs of said counter 17 is greater than the previously stored limited maximum value, represented by outputs of said limited maximum register 27.
  • Said first gating circuit 24 will generate a pulse on its output concurrently with any pulse arriving on said write line h, if said first comparator circuit 20 and third comparator circuit 22 concurrently have logical 1 states on their outputs during the pulse arriving on said write line h.
  • the pulse arriving on said first tarnsit line k, being generated by said first gating unit loads said limited minimum register 25 with data being present on said group H of internal data lines, which represent the value of time interval measured (counted) between the last two examined signal changes.
  • Said second gating circuit 26 will generate a pulse on its output concurrently with any pulse arriving on said write line h, if said second comparator circuit 21 and fourth comparator circuit 23 concurrently have logical 1 states on their outputs during the pulse arriving on said write line h.
  • the pulse generated by said second gating circuit 26 and appearing on said second transit line loads said limited maximum register 27 with data being present on said group H of internal data lines, which as mentioned above, represent the value of time interval measured (counted) between the last two examined signal changes. Contents of said limited maximum register, representing the previously stored limited maximum value, appear on said second bunch G of data lines.
  • Said limited maximum register 27 will be cleared (all bits of said limited maximum register 27 will be set to zero, that is to the minimum absolute value, that can be stored by it) , if a pulse arrives on said fourth addressing line f. (On said fourth addressing line f a pulse appears, when said control unit 11 - see fig.2. - reads contents of said limited maximum register 27. In such a way, if measuring lasted long enough, said limited minimum register 25 and said limited maximum register 27 will hold minimum and maximum values, statistically characterizing the input data stream arriving on said group E of ' input data lines.
  • Said time marker circuit 16 is in this case a signal change indicator circuit constituted by edge-triggered monostable multivibrators.
  • said group E of input data lines is represented by a single input line, on which input data arrive.
  • said signal change indicator circuit 1 After every signal change (signal edge) said signal change indicator circuit 1 generates two successive pulses. First it gives a pulse onto said write line h, and thereafter another one concurrently onto said reset line s and said enabler line i.
  • said third transit line, connected to said time marker circuit 16 is of no importance.
  • said time marker circuit 16 includes a first signal change indicator circuit 28, a second signal change indicator circuit 29 and a storage 30.
  • the inputs of said first signal change indicator circuit 28 comes from a first input data line n, being part of said group E of input data lines, its output is applied via a transit data line r to the input of said storage 30.
  • the input of said second signal change indicator circuit 29 is connected to a second input data line p, also being part of said group E of input data lines, the outputs of said second signal change indicator circuit is partly connected via said reset line s to a further input of said storage 30, partly to said write line h. respectively.
  • the output of said storage 30 is applied to said enabler line i.
  • said group E of input data lines consist of two lines. These two lines are: first input data line n and second input data line p.
  • Said first signal change indicator circuit 28 gives a pulse onto said transit data line r after every signal change occuring on said first input data line n.
  • Said second signal change indicator circuit 29 gives a pulse onto said reset line s and said write line h after every signal change occuring on said second input data line p.
  • Said storage 30 is set to logical 1 state, and gives a logical 1 onto said enabler line i, whenever a pulse arrives on said transit data line r; it will be cleared (set to zero) and gives a logical 0, whenever a pulse arrives on said reset line s.
  • the minimum/maximum values of time distances between signal changes on two different signal lines can be determined.
  • signal skew can be determined.
  • said time marker circuit 16 comprises a signal change and start/stop bit indicator circuit 31 and a bistable multivibrator 32.
  • the input of said signal change and start/stop bit indicator circuit 31 is connected to an input data line o, being part of said group E of input data lines, its outputs are connected partly via a reset line s to an input of said bistabl multivibrator 32, partly via a stop signal line q to another input of said bistable multivibrator 32 and partly to. said write line h, respectively.
  • the output of said bistable multivibrator . is connected to said enabler line i.
  • said group E of input data lines consists of a single input data line o.
  • a serial data stream arrives and given to the input of said signal change and start/stop bit indicator circuit 31.
  • said signal change and start/stop bit indicator circuit 31 detects a START bit, on the first (leading) edge of the START bit it gives a pulse onto said reset line s.
  • said signal change and start/stop bit indicator circuit detects a STOP-bit (that is, it detects a 0-*l signal change in an appropriate neighbourhood of the probable position of the leading edge of the STOP bit; this o * *"l change will only occur, when STOP bit is preceeded by a bit, having a value of logical 0 in the data stream) , it gives a pulse onto said stop signal line q.
  • said signal change and start/stop bit indicator circuit 31 detects any other signal changes between respective START and STOP signal edges, it gives a pulse onto said write line h on every appropriate signal change.
  • Said bistable multi ⁇ vibrator 32 will be set to logical 1 state, and will give a logical 1 signal onto said enabler line i, whenever a pulse arrives on said reset line s.
  • Said bistable multivibrator 32 will be cleared, and will give a logical 0 signal onto said enabler line i, when a pulse arrives on said stop signal line q.
  • Said third transit line t shown in fig. 3 is in this embodiment of no importance. A further preferred embodiment of said time marker circuit 16 will be described with respect to fig. 6.
  • said time marker circuit 16 comprises a signal change and start bit indicator circuit 33, a bistabil multivibrator circuit 34 and on AND gate 35.
  • the input of said signal change and start bit indicator circuit is connected to said input data line o, being part of said group E of input data lines, its outputs are connected partly to said reset line s, and via said reset line s to an input of said bistable multivibrator circuit 34, partly to said write line h, and via said write line h to an input of said AND-gate 35.
  • Another input of said AND-gate 35 comes from said third transit line t, its output is connected via a stopping line z to another input of said bistable multivibrator circuit 34.
  • the output of said bistable multivibrator circuit 34 is connected to said enabler line i.
  • said group E of input data lines consists of an input data line o.
  • Said signal change and start bit indicator circuit monitors input signal stream arriving on said input data line o, and whenever it detects any signal change, it gives a pulse onto said write line h. Furthermore, if said signal change and start bit indicator circuit detects a START bit (that is: on leading edge of any START bit) , it gives a pulse onto said reset line s, and in such a way it sets said bistable multivibrator circuit 34 to a logical 1 state. Thereafter , said bistable multi ⁇ vibrator 34 gives a logical 1 signal onto said enabler line i. Said bistable multivibrator circuit 34 will be cleared (that is: set to logical 0 state) when a pulse arrives on said stopping line z.
  • Said AND gate 35 generates a pulse on its outputs, and gives this pulse onto said stopping line, when a pulse arrives on said write line h (generated by said signal change and start bit indicator circuit 33) , and at the same time a logical 1 state is present on said third transit line t.
  • a./ Data transmission rate and signal distortion may be deter ⁇ mined by using the same method and same device.
  • Data transmission rate may not only be determined at the beginning of the data transmission, if at first special predetermined characters are transmitted, but at any time during the data transmission, without any constraints with respect to the transmitted characters, supposing that within a limited time interval at least one character is transmitted in which a signal change will be followed by another within a time interval according to a single bit-time. This enables data transmission rate to be determined for example by signal- and protocol anlyzer devices, "listening to" a given data channel in a discretional time interval.
  • the invented device may be realized in a single LSI integrated circuit that may be programmed by a microprocessor.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)

Abstract

Dans le procédé, l'intervalle de temps entre deux changements de signaux successifs est déterminé et éventuellement stocké de manière que l'intervalle de temps mesuré entre les deux derniers changements de signaux est comparé avec la valeur minimum stockée antérieurement, et en même temps avec une limite minimum postulée et stockée au préalable; la valeur de l'intervalle de temps mesuré ne sera stockée comme nouvelle valeur minimum que si elle est inférieure à la valeur stockée antérieurement, mais en même temps supérieure à la limite minimum postulée (dans ce cas la valeur minimum stockée antérieurement est perdue); et/ou dans le cas de comparaison on étudiera si la valeur mesurée en dernier est supérieure à la valeur maximum stockée antérieurement et en même temps, si elle est inférieure à la limite maximum postulée et stockée au préalable, après quoi la nouvelle valeur ne sera stockée qu'en tant que nouvelle valeur maximum, si les conditions établies ci-dessus sont remplies (dans ce cas, cependant, la valeur maximum stockée antérieurement est perdue). Le dispositif de l'invention comprend une unité de commande (11), un décodeur d'adresses (13), une première unité de déclenchement (14), et un décodeur de distorsion de signaux et de débit (en bauds) (12) et une seconde unité de déclenchement (15). Les entrées de l'unité de distorsion de signaux et de débit en bauds (12) sont connectées via la première ligne d'adressage (b) et via la seconde ligne d'adressage (d) aux sorties respectives du décodeur d'adresses (13), une autre entrée via la troisième ligne d'adressage (e) à une autre sortie du décodeur d'adresse (13) et à une entrée de la première unité de déclenchement (14), une autre entrée via la quatrième ligne d'adressage (f) à une autre sortie du décodeur d'adresse (13) et à une entrée de la seconde unité de déclenchement (15), d'autres entrées de celle-ci étant connectées au groupe de lignes de données d'entrée (E) constituant la borne d'entrée du dispositif, les entrées restantes via le groupe de lignes
EP19870900248 1985-12-20 1986-12-19 Procede et dispositif pour determiner la vitesse de transmission de donnees et la distorsion de signaux de lignes de transmission de donnees serielles synchrones et asynchrones Withdrawn EP0277952A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
HU490985A HU195378B (en) 1985-12-20 1985-12-20 Method and device for determining signal transfer rate and/or signal distortion of the synchronous and/or asynchronous serial data transfer lines
HU490985 1985-12-20

Publications (1)

Publication Number Publication Date
EP0277952A1 true EP0277952A1 (fr) 1988-08-17

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EP19870900248 Withdrawn EP0277952A1 (fr) 1985-12-20 1986-12-19 Procede et dispositif pour determiner la vitesse de transmission de donnees et la distorsion de signaux de lignes de transmission de donnees serielles synchrones et asynchrones

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EP (1) EP0277952A1 (fr)
AU (1) AU6779987A (fr)
HU (1) HU195378B (fr)
WO (1) WO1987004030A1 (fr)

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US7292578B1 (en) * 2001-06-19 2007-11-06 Cisco Technology, Inc. Flexible, high performance support for QoS on an arbitrary number of queues

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DE1285499B (de) * 1966-09-23 1968-12-19 Siemens Ag Schaltungsanordnung zum Messen der Verzerrung von hintereinander folgenden Zeitintervallen, insbesondere von Telegrafie-Signalen mit grosser Schrittgeschwindigkeit, und Anzeige der Verzerrung auf dem Bildschirm eines Oszillographen
DE2358296B2 (de) * 1973-11-22 1977-05-26 Siemens AG, 1000 Berlin und 8000 München Schaltungsanordnung zum messen der verzerrung von datensignalen
DE2940271A1 (de) * 1979-10-04 1981-04-16 Helmut Dr. 5481 Nierendorf Hißen Verfahren zur automatischen messung der schrittgeschwindigkeit

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See references of WO8704030A1 *

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Publication number Publication date
AU6779987A (en) 1987-07-15
HUT42217A (en) 1987-06-29
HU195378B (en) 1988-04-28
WO1987004030A1 (fr) 1987-07-02

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